IEEE International Conference on Microelectronic Test Structures
ICMTS 2023 Program
Day 2 - March 29
| 08:30 | How to make better abstract |
Session 5: Matching & Variability
| 09:00 | [5-1] Measurement of Temperature Effect on Comparator Offset Voltage Variation Yuma Iwata, Takehiro Kitamura, and Mahfuzul Islam Department of Electrical Engineering, Graduate School of Engineering, Kyoto University, JAPAN Comparator offset voltage often limits the performance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100 degree C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100 degree C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures. |
| 09:20 | [5-2] Variability of MOSFET Series Resistance Extracted from Individual Devices: Is Direct Variability Measurement Possible? Kiyoshi Takeuchi1, Tomoko Mizutani1, Takuya Saraya1, Masaharu Kobayashi1,2, and Toshiro Hiramoto1 1 Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 2 System Design Research Center (d.lab), The University of Tokyo, Tokyo, Japan Source-to-drain series resistance (R SD) of a large number of identically designed MOSFETs was extracted using a recently proposed single-device method. By examining statistical correlations with other device parameters, it was confirmed that variability of the extracted R SD values does not correspond to real series resistance variability, but is mainly caused by some non-R SD variability sources. This suggests that, for the single-device method to work, non-R SD variability needs to be reduced by averaging multiple devices, or using wide channel devices. |
| 09:40 | [5-3] Variability Evaluation of MOS-gated PNPN Diode for Hardware Spiking Neural Network Toshihiro Takada, Takayuki Mori, and Jiro Ida Division of Electrical Engineering, Kanazawa Institute of Technology, Ishikawa, Japan The variability of the neuronal function device of a metal oxide semiconductor-gated PNPN diode was evaluated. The variability of neurons is known to affect the inference accuracy of spiking neural networks (SNNs). The device has stochastic operation on its own, and the spike requency can be controlled by the gate voltage, which has the possibility to improve the accuracy of SNNs. |
| 10:00 | [5-4] Effect of Quadruple Size Transistor on SRAM Physically Unclonable Function Stabilized by Hot Carrier Injection Shufan Xu1, Kunyang Liu2, Yichen Tang1, Ruilin Zhang1, and Hirofumi Shinohara2 1 Information, Production and Systems Research Center, Waseda University, Kitakyushu, Japan 2 Graduate School of Information, Production and Systems, Kitakyushu, Japan This article presents a bitcell of a static randomaccess memory (SRAM)-based physically unclonable function (PUF) with quadruple-size transistor, which reduces the ‘tail’ of mismatch distribution after hot carrier injection (HCI) burn-in. A statistical mismatch distribution model after HCI application for a certain time is proposed by combining native mismatch distribution before HCI and mismatch shift distribution after HCI. Model calculation shows that quadruple-size transistor SRAM PUF needs 15-min HCI burn-in time to achieve cryptographic level requirement, which is more than 3 times shorter than normal-size transistor SRAM PUF of 46-min. The effect of utilizing the quadruple-size transistor with respect to HCI burn-in for stability reinforcement is also confirmed by measuring chips fabricated in a 130-nm CMOS process. Experimental results show that the ‘tail’ in mismatch distribution is significantly eliminated after 18-min HCI burnin time of quadruple-size transistor SRAM PUF, which meets our expectations. The presented statistical model also matches the measurement data well. |
| 10:20 | Break |
Session 6: Yield and Device Optimization
| 10:50 | [6-1] Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications Hao-Chiao Hong1,2, Long-Yi Lin1,3, and Bo-Chang Chen2 1 Institute of Electrical and Computer Engineering, 2 Institute of Electrical and Control Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan 3 Novatek MicroElectronics Corp., Hsinchu, Taiwan Computing-in-memory (CIM) is a promising technique for energy-efficiently conducting the massive amount of required multiply-and-accumulate (MAC) calculations in neural networks (NNs). The read-decoupled 8T (RD8T) SRAM cell is popular in the CIM designs because of being read disturbance free. However, local process variations may lead significant errors to the CIM results. This work proposes an accurate on-chip test circuit design for characterizing the output current of every RD8T SRAM cell in a 8-kb RD8T SRAM array fabricated in 90nm CMOS. The experimental results show the detailed and accurate spatial distribution of the RD8T cells which helps optimize the CIM circuit design. |
| 11:10 | [6-2] Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation V.Vidya1, N. Zamdmer1, T. Mechler1, K. Onishi1, D. Chidambarao1, B. W. Jeong2, Y. G. Ko2, C. H. Lee1, J. Sim1, M. Angyal1, E. Crabbe1 1 IBM Systems, IBM Corp, 2070 Route 52, B300-A, Hopewell Junction, NY 12533, USA 2 Samsung Electronics Co. Ltd, San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, 445-701, Republic of Korea This paper presents two phenomena captured by product-like analog layout design of experiments (DOEs) that are otherwise difficult to capture in foundry baseline test structures. Such product driven test structures are critical for early detection of yield detractors and robustly validating a technology in a fabless design environment. |
| 11:30 | [6-3] An Electrical Inline-Testable Structure to Monitor Gate-Source/Drain Short Defect Caused by Imperfect Fin-Cut Patterning in FinFET Technology Hai Zhu1, Katsunori Onishi1, Stephen Wu1, Adam Yang1, Byoung-Wook Jeong2, Seong-Joon Lim2, Nan Jing1, Choong-Ho Lee1, David Conrady1, and Dureseti Chidambarrao1 1 IBM Systems, IBM Corp, 2070 Route 52, B300A, Hopewell Junction, NY 12533, USA 2 Samsung Electronics Co. Ltd., San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, 445-701, Republic of Korea On semiconductor IC chips, non-functional test structures are often designed along with the functional circuits in order to monitor the process quality even when the wafers are running in the line. This paper introduces an inline electrical test structure to monitor a systematic gate-source/drain short defect that degrades chip product yield. This area efficient, test time friendly, and insightful test structure is ideal to monitor process quality for the forementioned failure mode and help with the diagnosis of chip functional failures. |
| 11:50 | [6-4] Wafer Level Reliability Monitoring of NBTI Using Polysilicon Heater Structures for Production Measurements Yu-Hsing Cheng Central Engineering, onsemi 1900 South County Trail, East Greenwich, RI 02818, USA The use of polysilicon heater structures provides a useful tool for fast NBTI assessment of wafer level reliability. In this work NBTI characterization for 1.2V PMOS devices in a 65 nm technology using polysilicon heaters in a parametric tester was performed without changing the chuck temperature to demonstrate NBTI reliability assessment with a short test time for production measurements. |
| 12:10 | Lunch |
| 13:40 | How to make better presentation |
| 14:10 | ICMTS 2024 |
| 14:25 | Break |
Session 7: MEMS & Sensors
| 14:55 | [7-1] Application of Greek cross structures for process development of electrochemical sensors Minxing Zhang1, Shan Zhang1,2, Camelia Dunare1,2, Jamie R. K. Marland1,2, Jonathan G. Terry1,2, Stewart Smith1,3 1 School of Engineering, The University of Edinburgh, Edinburgh, Scotland, UK 2 Research Institute for Micro and Nano Systems 3 Research Institute for Bio-Engineering Using a test structure chip designed to assist in process development for reference electrode fabrication for integrated electrochemical sensors, this paper reports measurements of Greek cross test structures and compares them to measurements of bridge resistor structures on the same chip. The correct application of these structures requires careful consideration of the measurement parameters to provide accurate results and different force current values have been investigated. Results from platinum structures suggest there is measureable variation in the feature size when Greek cross results are used to extract electrical critical dimension from the bridge resistor measurements. Similar measurements of silver structures were less conclusive. While the bridge structures show a significant effect of oxidation of silver which has been exposed to air since fabrication, the Greek cross results are highly variable and may not be reliable. |
| 15:15 | [7-2] Test Structures for Studying Coplanar Reverse- Electrowetting for Vibration Sensing and Energy Harvesting Anotidaishe Moyo1, Muhammad Wakil Shahzad1, Jonathan G. Terry2, Stewart Smith2, Yoshio Mita3, Yifan Li1 1 Department of Mechanical and Construction Engineering, Faculty of Engineering and Environment, Northumbria University, UK 2 School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, UK 3 Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan Reverse electrowetting on dielectric (REWOD) has emerged to be a promising energy harvesting technology from low frequency vibrations. This study aims to use test structures to characterize a unique form of REWOD using a coplanar electrode configuration. This configuration allows for better versatility in system integration, device packaging and applications. |
| 15:35 | [7-3] Damage Assessment Structure of Thermal-Annealing Post-Processing on CMOS LSIs Yuki Okamoto1, Natsumi Makimoto1, Kei Misumi2, Takeshi Kobayashi1, Yoshio Mita2, Masaaki Ichiki1 1 Sensing System Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan 2 School of Electrical Engineering, The University of Tokyo, Tokyo, Japan We assessed the degradation of MOSFET and CMOS LSI circuit characteristics induced by the hightemperature annealing, especially for the PZT deposition process. The test structure consists of ring oscillators having different numbers of stages and single PMOSFETs and NMOEFETs designed with 0.6 um CMOS technology. We observed the ring oscillator (RO) oscillating frequencies and the Id-Vg characteristics of the MOSFETs before and after the annealing post-process. The result indicated that such an annealing process involving high temperatures of around 575 degree C is possible unless the wiring on the CMOS components is mechanically broken. In addition, annealing temperature affected the MOSFET characteristics more than annealing times. Therefore, the effects of the CMOSMEMS monolithic integration using PZT thin films be optimized using the proposed test structures. |
| 15:55 | [7-4] Improving Performance of FBARs by Advanced Low-Temperature High-Pressure Technology Yu-Fa Tu1, Ting-Chang Chang2,3, Kuan-Ju Zhou2, Wei-Chun Hung2, Ting-Tzu Kuo4, and Chen-Hsin Lien1 1 Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan 2 Department of Physics, National Sun Yat-sen University, Kaohsiung 80424, Taiwan 3 Center of Crystal Research, National Sun Yat-sen University, Kaohsiung 80424, Taiwan 4 Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan In this study, a unique supercritical fluid (SCF) treatment is utilized to improve the resonance properties of thin film bulk acoustic resonators (FBARs) composed of a piezoelectric material of AlN. In an etching process of the sacrificial oxide, FBARs suffered from severe surface tension of etching acid solvent, resulting in structural bonding and residues generation. These impact on FABR’s structural integrity would influence its resonance properties. Therefore, a SCF treatment with low surface tension and high penetrability can effectively carry out residues from the release gap in a FBAR, observed from SEM images. The results show that the reflection coefficient, the quality factor, and the effective coupling coefficient are all improved in FABRs. |
| 16:15 | [7-5] Solderable Multisided Metal Patterns Enables 3D Integrable Direct Laser Written Polymer MEMS Landon Ivy and Amit Lal The SonicMEMS Laboratory, School of Electrical and Computer Engineering, Cornell University, USA This work describes a new process for realizing arbitrarily complex polymer structures which feature unique metal patterns on multiple sides. Characterizations were performed to achieve reliable metal covereage, microvia continuity, solderability, and releasability. To showcase this process’ capabilities, three characterization devices, including a functional comb-drive (CD) actuator, will be presented. |
| 16:35 | Break |
| 18:00 | Banquet Chinzanso - Tokyo 2 Chome-10-8 Sekiguchi, Bunkyo City, Tokyo 112-8680 https://hotel-chinzanso-tokyo.com (EN) https://hotel-chinzanso-tokyo.jp (JP) |
| 20:00 | End |
