IEEE International Conference on Microelectronic Test Structures
ICMTS 2023 Program
Day 3 - March 30
Session 8: Modeling
| 09:00 | [8-1] Accurate Gate Charge Modeling of HV LDMOS Transistors for Power Circuit Applications Xiaorui Jie, Ronald van Langevelde, Kejun Xia1, Lei Chao, Colin C. McAndrew, Qilin Zhang, Matthew Bacchi2, and Wuxia Li NXP Semiconductors, Front End Innovation 1 TSMC, Special Technology Product Engineering 2 NXP Semiconductors, Business Line Advanced Analog Accurate modeling of the gate-drain capacitance Cgd for HV LDMOS transistors is important but is challenging because of its strong bias dependence. We present an improved Cgd model, based on the physics that the drift region under the poly-gate is fully depleted at high Vdg, and validate our model against gate charge measurements for both n- and p-type 90V LDMOS transistors. |
| 09:20 | [8-2] Introducing Transfer Learning Framework on Device Modeling by Machine Learning Kota Niiyama, Hiromitu Awano, and Takashi Sato Graduate School of Informatics, Kyoto University In this study, we propose a novel transistor modeling method using machine learning techniques, with a focus on extrapolation performance. Our method leverages knowledge from a base model that is related to the target model, instead of relying solely on device-specific information. The results show that our approach outperforms other transistor modeling methods based on machine learning, particularly in modeling similar but different transistors that belong to the same device family. Our method was able to reduce the root mean squared error (RMSE) by up to 80.0% compared to other methods. |
| 09:40 | [8-3] Technology-Dependent Modeling of MOSFET Parasitic Capacitances for Circuit Simulation Dondee Navarro, Chika Tanaka, Kanna Adachi1, Takeshi Naito, Kenshi Tada and Akira Hokazono Memory Division, KIOXIA Corporation, Yokohama, Japan 1 Institute of Memory Technology Research and Development, KIOXIA Corporation, Yokohama, Japan Models for parasitic capacitances in the MOSFET overlap region are developed for circuit simulation. In particular, the overlap capacitance (Cov) model considers the modulation of the overlap length due to the dynamic depletion of channel/LDD junction, which is the physical origin of the Cov bias-dependence. The models are implemented in Verilog-A, and incorporated in a MOSFET model for circuit simulation. Reproduction of device simulation results and RF-CMOS gatedrain capacitance measurements are verified. |
| 10:00 | Break |
Session 9: Novel Materials
| 10:30 | [9-1] Bridging Large-Signal and Small-Signal Responses of Hafnium-Based Ferroelectric Tunnel Junctions M. Massarotto1, M. Segatto1, F. Driussi1, A. Affanni1, S. Lancaster2, S. Slesazeck2, T. Mikolajick2,3, D. Esseni1 1 DPIA, University of Udine, Udine, Italy 2 NaMLab gGmbH, Dresden, Germany 3 Chair of Nanoelectronics, IHM, TU–Dresden, Germany Ferroelectric Tunnel Junctions (FTJs) operating as memristors are promising electron devices to realize artificial synapses for neuromorphic computing. But the understanding of their operation requires an in-depth electrical characterization. In this work, an inhouse experimental setup is employed along with novel experimental methodologies to investigate the largesignal (LS) and small-signal (AC) responses of FTJs. For the first time, our experiments and physics-based simulations help to explain the discrepancies between LS and AC experiments reported in previous literature. |
| 10:50 | [9-2] Demonstration of frequency doubler application using ZnO–DNTT anti-ambipolar switch device Yongsu Lee, Hyeon Jun Hwang, and Byoung Hun Lee Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, Gyeongbuk 37673, Republic of Korea This paper presents the demonstration of an antiambipolar switch (AAS) using a ZnO–dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (DNTT) heterojunction structure. The proper combination of n- and p-type thin-film semiconductors achieved a high peak-to-valley ratio of ~10^5 at a low process temperature compatible with the back-end-of-line process. Using the electrical characteristic of positive-to-negative transconductance switching at the peak current point, a frequency doubler was implemented with only one device. The excellent electrical performance of the ZnO–DNTT AAS device resulted in a high conversion gain of -5 dB and an output frequency purity of 97%. |
| 11:10 | [9-3] Identifying nano-Schottky diode currents in silicon diodes with 2D interfacial layers Tihomir Knežević1, Lis K. Nanver2 1 Ruđer Bošković Institute, Zagreb, Croatia 2 MESA+ Institute of Nanotechnology, University of Twente, Enschede, The Netherlands In silicon technology, Schottky diodes mainly exhibit high current levels, and attempts are regularly made to reduce these by introducing 2D layers between the metal contact and the silicon. Defects in such interfacial layers, from weakly bonded structures to actual pinholes, can lead to high, localized metal-semiconductor Schottky currents. Using the example of diodes with an interfacial layer of pure boron (PureB) between an aluminum metallization layer and the Si, a signature for such “nano-Schottky’s” is determined by evaluating the results of several different test-structure arrays and measurement techniques. An adapted bipolar-type measurement is introduced as an additional method to determine whether any high current characteristics originate from a low Schottky barrier height over the entire diode surface or from a localized nano-Schottky structure. |
| 11:30 | Close + Best Paper Award |
