IEEE International Conference on Microelectronic Test Structures

ICMTS 2023 Program

Day 1 - March 28

Session 1: Emerging Memory

09:00	[1-1] Discrete current limiting circuit for emerging memory programming Léo Laborie¹, Paola Trotti¹, Killian Veyret¹, Carlo Cagli^² ¹ Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France ² STMicroelectronics, Grenoble, France This work presents a novel, discrete-component circuit for the electrical characterisation of Resistive Random Access Memory (RRAM). The cycling of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transistor. The presented DCL circuit is furthermore benchmarked versus other discrete and integrated typologies, showing dramatic improvement over existing discrete solutions, and comparable performances with integrated architectures. Finally, multi-bit storage is experimentally demonstrated through modulation of the programming current amplitude.
09:20	[1-2] Test Methodology Development for Investigating CeRAM at Elevated Temperatures A. A. Gruszecki¹, R. Prasad¹, S. V. Suryavanshi³, G. Yeric³, and C. D. Young^1,2 ¹ Electrical and Computer Engineering Department, The University of Texas at Dallas, Richardson, Texas, USA ² Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, Texas, USA ³ Cerfe Labs, Austin, Texas, USA Correlated electron RAM (CeRAM) device test structures utilizing C-doped NiO were fabricated and electrically characterized to determine functionality in extreme environments. CeRAM devices were demonstrated to repeatedly cycle at temperatures up to 200oC while maintaining a substantial memory window of over 1000x. Careful selection of compliance current when sweeping the high resistance state (OFF) is required for optimal device performance. The presence of a temperature dependent leakage current in the OFF state results in reducing OFF resistance at elevated temperatures.
09:40	[1-3] Real-time electrical measurements during laser attack on STT-MRAM Nicole Yazigy¹, Jeremy Postel-Pellerin¹, Vincenzo Della Marca¹, Ricardo. C. Sousa², Anne-Lise Ribotta³, Gregory Di Pendina², Pierre Canet¹ ¹ Aix-Marseille Université, IM2NP, CNRS, UMR 7334, 5 rue Enrico Fermi, 13397 Marseille, France ² SPINTEC, University Grenoble Alpes, CNRS, CEA, SPINTEC, 38000 Grenoble, France. ³ Mines Saint-Etienne, CEA, Leti, Centre CMP, 13541 Gardanne, France The goal of the study is to monitor the device’s response during laser injection while being able to track pre- and post-attack conditions. We show the irradiation power affects the STT-MRAM behavior. Our electrical/optical setup enables to know the memory cell behavior to study real-time laser attack countermeasures and device reliability. We have highlighted the possibility to switch, to degrade or even to destruct the cell, depending on the laser power.
10:00	[1-4] Automated RRAM measurements using a semi-automated probe station and ArC ONE interface Alin G. Panca¹, Alexantrou Serb¹, Spyros Stathopoulos¹, Suresh K. Garlapati², Themis Prodromakis¹ ¹ Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh, UK ² Materials Science And Metallurgical Engineering, Indian Institute of Technology Hyderabad, Telangana, India Resistive Random Access Technology (RRAM) is quickly reaching industrial maturity. A key element towards achieving lasting commercial success, however, is automated testing; useful for performance benchmarking and rapid prototyping of new flavours of technology. Here we present a wafer-scale semi-automated RRAM device testing platform.
10:20	[1-5] Analysis of Critical Schottky Distance Effect and Distributed Set Voltage in HfO2-based 1T-1R Device Shih-Kai Lin¹, Ting-Chang Chang^2,3, Wei-Chen Huang², Yung-Fang Tan⁴, and Chen-Hsin Lien¹ ¹ Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan ² Department of Physics, National Sun Yat-Sen University, Kaohsiung, 80424, Taiwan ³ College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 80424, Taiwan ⁴ Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan High resistance state (HRS) resistance on the set voltage in hafnium oxide-based resistance random access memory (RRAM) is investigated. Set voltage has a positive correlation to HRS in statistics. For analyzing the switching characteristics at different HRS resistance level, filament properties in the switching layer are analyzed by current-fitting technique. The fitting results show that Schottky distance becomes saturated at high resistance HRS. Finally,
10:40	Break

Session 2: Noise

11:10	[2-1] Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure Owen Gauthier^1,2, Sébastien Haendler¹, Ronan Beucher¹, Patrick Scheer¹, Quentin Rafhay², and Christoforos Theodorou² ¹ STMicroelectronics, Crolles, France ² Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP, IMEP-LAHC, Grenoble, France The use of an addressable array test structure designed on a 28 nm FD-SOI technology for the variability analysis of static, low frequency noise (LFN) and Random Telegraph Noise (RTN) matching is presented. The experimental setup was validated, and a statistical analysis of the above electrical quantities is provided. Using such structures, combined with a switching matrix, local and global variability analysis can be performed while significantly increasing the number of samples, thus enabling a better description of the variations in LFN and RTN, especially when RTN signatures can be scarce. We show that local variations dominate the noise variability compared to global variations.
11:30	[2-2] An Extended Method to Analyze Boron Diffusion Defects in 16 nm Node High-Voltage FinFETs Ting-Tzu Kuo¹, Ying-Chung Chen¹, Ting-Chang Chang²,Fong-Min Ciou³, Chien-Hung Yeh⁴, Po-Hsun Chen⁵, and Simon M. Sze⁶ ¹ Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan ² Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan ³ Department of Physics, National Sun Yat-sen University, Kaohsiung, 80424, Taiwan ⁴ Department of Photonics, National Sun Yat-sen University, Kaohsiung 804, Taiwan ⁵ Department of Applied Science, R. O. C. Naval Academy, Kaohsiung 813, Taiwan ⁶ Department of Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, 300, Taiwan This work proposed extended methods, which can analyze kinds of defects more easily with power spectrum density (PSD) and weighted time lag plot (W-TLP), to decouple single or multi-traps. To get additional high voltage tolerance, it is common to design different kinds of structures dispersing the electric field. In this work, boron and fluorine were doped in the source and drain extension regions to achieve higher voltage operation. However, boron diffusion could worsen the interface quality. Interestingly, after different stress conditions of hot carrier degradation (HCD) and positive bias temperature instability (PBTI), the degradation trends of the two devices show opposite behaviors. It is because the boron can bear the high voltage operation, but also weak the devices’ interface quality. Therefore, to analyze the influence of these defects plays an important role. With Agilent B1530A WGFMU and RTSDataAnalysis software, varied defects response to frequency can be simply detected. It can also use W-TLP to decouple single trap and multi-traps behaviors at the same time.
11:50	[2-3] Vss-Bias-Based Measurement of Random Telegraph Noise in Hybrid SRAM PUF after Hot Carrier Injection Burn-In Kunyang Liu, Yichen Tang, Shufan Xu, and Hirofumi Shinohara Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan In this paper, a method to observe random telegraph noise in a hybrid SRAM PUF array is presented. This allows low-cost observation of RTN in a number of bitcells by applying VSS bias voltages to measure their temporal mismatches. Also, the changes in RTN amplitude after hot carrier injection burn-in, which is used for PUF stabilization, have been measured and analyzed. Experimental results from a 130-nm CMOS test chip show that the average RTN amplitude across 80-run measurements increases from 1.46 mV before HCI to 9.72 mV after 18-min HCI. The maximum RTN amplitude also increases from 10.13 mV to 84.50 mV. These results indicate that RTN is not an omittable factor especially for a PUF using a hot carrier injection-based stabilization technique and should be carefully considered when deciding the burn-in strategy.
12:10	Lunch

Session 3: Power Devices

14:10	[3-1] Distributed field plate effects in split-gate trench MOSFETs R. Tambone^1,2, A. Ferrara¹, F. Magrini³, A. Hoffmann³, A. Wood¹, G. Noebauer¹, E. Gondro³, and R.J.E. Hueting² ¹ Infineon Technologies Austria AG, Siemenstrasse 2, 9500 Villach, Austria ² University of Twente, Drienerlolaan 5, 7522 NB Enschede, The Netherlands ³ Infineon Technologies AG, Am Campeon 1, 85579 Neubiberg, Germany Fast electric transients can cause distributed effects inside trench MOSFETs possibly resulting in device failure. A new test structure to study those distributed effects, combined with a new Transmission-Line Pulse (TLP) setup, is presented. On-wafer TLP measurements are performed and combined with TCAD and SPICE simulations to predict the space and time evolution of the field plate potential during transients.
14:30	[3-2] Measuring of parasitic resistance of stacked chip of Si power device Tatsuya Ohguro¹, Hideharu Kojima¹, Takuma Hara¹, Tatsuya Nishiwaki² and Kenya Kobayashi¹ ¹ Toshiba Electronic Devices & Storage Corporation, 1-1, Iwauchi-Machi, Nomi, Ishikawa, Japan ² Toshiba Electronic Devices & Storage Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan Stacked chip of Si power device is useful for both lower on-resistance and small packaged size for reduction of system size and high power efficiency. In this paper, some structures and procedure to measure parasitic resistance of the stacked chip are described.
14:50	[3-3] New Extraction Method for Intrinsic Qrr of Power MOSFETs T. Hara, S. Nakajima, T. Ohguro and K. Miyashita Advanced Semiconductor Device Development Center, Toshiba Electronic Devices & Storage Corporation We provide the method to estimate intrinsic Qrr(Qrr_int) without parasitic inductance in the measurement system for the first time. In this paper, we analyze parasitic inductance dependence of Qrr by TCAD simulation and we propose the method for removing the parasitic inductance effect as well as calculating the carrier of recombination and discharge (qrr_int0).
15:10	[3-4] On-Resistance Measurements of Low Voltage MOS-FET at wafer level Kohei Oasa¹, Tatsuya Nishiwaki¹, Tatsuya Ohguro², Yasunobu Saito¹, and Yusuke Kawaguchi² ¹ Toshiba Electronic Devices & Storage Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan ² Toshiba Electronic Devices & Storage Corporation, 1-1, Iwauchi-Machi, Nomi, Ishikawa, Japan To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.
15:30	[3-5] Comparative study on characteristics of GaN-based MIS-HEMTs with Al2O3 and Si3N4 gate insulators under Hot Carrier Degradation Pei-Yu Wu¹, Xin-Ying Tsai², Ting-Chang Chang³, Tsung-Ming Tsai¹ and Simon M. Sze² ¹ Pei-Yu Wu and Tsung-Ming Tsai are with the Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan ² Xin-Ying Tsai and Simon M. Sze are with the Department of Electronics Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan ³ Ting-Chang Chang is with Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan In GaN-based metal-insulator-semiconductor high electron mobility transistors (GaN based MIS HEMTs), Al2O3/Si3N4 bilayer-gate insulator-MIS HEMTs (Al2O3/Si3N4-MIS HEMTs) are considered to have the advantages of low gate leakage and low interface defects. This study will compare Si3N4 gate insulator-MIS HEMTs (Si3N4-MIS HEMTs) to discuss and clarify the abnormal deterioration mechanism of Al2O3/Si3N4-MIS HEMTs under Hot Carrier Effect (HCE). Therefore, in this study, the results of HCE between Si3N4-MIS HEMTs and Al2O3/Si3N4-MIS HEMTs are compared, and the abnormal HCS degradations in Al2O3/Si3N4-MIS HEMTs are discussed and explained in depth. A series of electrical and simulation analysis is conducted in order to verify the degradation mechanism model proposed in this study.
15:50	Break

Session 4: Measurement Technique

16:20	[4-1] The Pressing Probe Needle Technique for Characterizing Mechanical Stress Sensitivity of Semiconductor Devices Hans Tuinhout, Oliver Dieball NXP Semiconductors, Eindhoven, The Netherlands This paper discusses the so called Pressing Probe Needle (PPN) technique for characterizing out-of-plane mechanical stress sensitivity of arbitrary semiconductor devices, implemented on a standard parametric test system. By utilizing a motorized probe positioner and a force calibrated standard tungsten parametric probe needle, this fast and high-spatial-resolution technique provides valuable insights into mechanical stress effects of process and device layout options. Such results are highly beneficial for high-precision analog circuit design and layout optimization.
16:40	[4-2] A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact Yen-Ling Chen, Shih-Hao Lai, Jian-Hao Lin, and Bing-Yue Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C. A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure is proposed to characterize the Ti-Al alloy/p-type 4H-SiC contact. It is confirmed that the test structure can judge the uniformity of the contact interface without destructive analysis such as cross-sectional transmission electron microscopy. Comparing with the results of singlecontact CBKR structure, it is observed that the contact interface is non-uniform and the formation of low resistivity interface depends on the contact area. This area-dependence issue should be solved in order to improve the SiC power devices and CMOS ICs.
17:00	[4-3] Test Structure for Evaluation of Pad Size for Wafer Probing Brad Smith¹, Donald Hall¹, and Garrett Tranquillo² ¹ NXP Semiconductors, Austin, TX, USA ² Celadon Systems, Inc., Burnsville, MN, USA A new, cage-like structure is presented and is shown to be able to electrically identify a probe needle that has fallen slightly off its probe pad, even when the standard probe resistance structure (pads shorted together) reports “good” probe resistance. Using both structures together enables a more accurate evaluation of a probe system’s capabilities. Both test structures were used to compare three types of probe cards, reporting the smallest probe pad size that provides 100% probe yield.
17:20	[4-4] Test Bench for Biopotential Instrumentation Amplifier using Single-Ended to Differential Amplifiers Surachoke Thanapitak, Pongsatorn Sedtheetorn, Pornchai Chanyagorn, Tatcha Chulajata, Somnida Bhatranand, and Phattanard Phattanasri Department of Electrical Engineering, Faculty of Engineering, Mahidol University Nakhon Pathom, Thailand A practical test bench for dry electrode bio-signal instrumentation amplifier is presented and demonstrated. By modifying the on-the-shelf single-ended to differential amplifier, the common-mode rejection ratio and distortion under electrodes offset scenario can be characterized. The other essential parameters such as input impedance and power supply rejection ratio can also be determined.
17:40	End

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