ICMTS 2023 Program

Program

Session 1: Emerging Memory

09:00	1‑1 🏆	Discrete current limiting circuit for emerging memory programming Léo Laborie1, Paola Trotti1, Killian Veyret1, Carlo Cagli2 1 Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France 2 STMicroelectronics, Grenoble, France Abstract (click to expand) This work presents a novel, discrete-component circuit for the electrical characterisation of Resistive Random Access Memory (RRAM). The cycling of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transistor. The presented DCL circuit is furthermore benchmarked versus other discrete and integrated typologies, showing dramatic improvement over existing discrete solutions, and comparable performances with integrated architectures. Finally, multi-bit storage is experimentally demonstrated through modulation of the programming current amplitude.
09:20	1‑2	Test Methodology Development for Investigating CeRAM at Elevated Temperatures A. A. Gruszecki1, R. Prasad1, S. V. Suryavanshi3, G. Yeric3, and C. D. Young1,2 1 Electrical and Computer Engineering Department, The University of Texas at Dallas, Richardson, Texas, USA 2 Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, Texas, USA 3 Cerfe Labs, Austin, Texas, USA Abstract (click to expand) Correlated electron RAM (CeRAM) device test structures utilizing C-doped NiO were fabricated and electrically characterized to determine functionality in extreme environments. CeRAM devices were demonstrated to repeatedly cycle at temperatures up to 200oC while maintaining a substantial memory window of over 1000x. Careful selection of compliance current when sweeping the high resistance state (OFF) is required for optimal device performance. The presence of a temperature dependent leakage current in the OFF state results in reducing OFF resistance at elevated temperatures.
09:40	1‑3	Real-time electrical measurements during laser attack on STT-MRAM Nicole Yazigy1, Jeremy Postel-Pellerin1, Vincenzo Della Marca1, Ricardo. C. Sousa2, Anne-Lise Ribotta3, Gregory Di Pendina2, Pierre Canet1 1 Aix-Marseille Université, IM2NP, CNRS, UMR 7334, 5 rue Enrico Fermi, 13397 Marseille, France 2 SPINTEC, University Grenoble Alpes, CNRS, CEA, SPINTEC, 38000 Grenoble, France. Abstract (click to expand) The goal of the study is to monitor the device's response during laser injection while being able to track pre- and post-attack conditions. We show the irradiation power affects the STT-MRAM behavior. Our electrical/optical setup enables to know the memory cell behavior to study real-time laser attack countermeasures and device reliability. We have highlighted the possibility to switch, to degrade or even to destruct the cell, depending on the laser power.
10:00	1‑4	Automated RRAM measurements using a semi-automated probe station and ArC ONE interface Alin G. Panca1, Alexantrou Serb1, Spyros Stathopoulos1, Suresh K. Garlapati2, Themis Prodromakis1 1 Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh, UK 2 Materials Science And Metallurgical Engineering, Indian Institute of Technology Hyderabad, Telangana, India Abstract (click to expand) Resistive Random Access Technology (RRAM) is quickly reaching industrial maturity. A key element towards achieving lasting commercial success, however, is automated testing; useful for performance benchmarking and rapid prototyping of new flavours of technology. Here we present a wafer-scale semi-automated RRAM device testing platform.
10:20	1‑5	Analysis of Critical Schottky Distance Effect and Distributed Set Voltage in HfO2-based 1T-1R Device Shih-Kai Lin1, Ting-Chang Chang2,3, Wei-Chen Huang2, Yung-Fang Tan4, and Chen-Hsin Lien1 1 Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan 2 Department of Physics, National Sun Yat-Sen University, Kaohsiung, 80424, Taiwan 3 College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 80424, Taiwan 4 Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan Abstract (click to expand) High resistance state (HRS) resistance on the set voltage in hafnium oxide-based resistance random access memory (RRAM) is investigated. Set voltage has a positive correlation to HRS in statistics. For analyzing the switching characteristics at different HRS resistance level, filament properties in the switching layer are analyzed by current-fitting technique. The fitting results show that Schottky distance becomes saturated at high resistance HRS. Finally,
10:40		Break

Session 2: Noise

11:10	2‑1	Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure Owen Gauthier1,2, Sébastien Haendler1, Ronan Beucher1, Patrick Scheer1, Quentin Rafhay2, and Christoforos Theodorou2 1 STMicroelectronics, Crolles, France 2 Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP, IMEP-LAHC, Grenoble, France
11:30	2‑2	An Extended Method to Analyze Boron Diffusion Defects in 16 nm Node High-Voltage FinFETs Ting-Tzu Kuo1, Ying-Chung Chen1, Ting-Chang Chang2,Fong-Min Ciou3, Chien-Hung Yeh4, Po-Hsun Chen5, and Simon M. Sze6 1 Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan 2 Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan 3 Department of Physics, National Sun Yat-sen University, Kaohsiung, 80424, Taiwan 4 Department of Photonics, National Sun Yat-sen University, Kaohsiung 804, Taiwan 5 Department of Applied Science, R. O. C. Naval Academy, Kaohsiung 813, Taiwan 6 Department of Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, 300, Taiwan
11:50	2‑3	Vss-Bias-Based Measurement of Random Telegraph Noise in Hybrid SRAM PUF after Hot Carrier Injection Burn-In Kunyang Liu, Yichen Tang, Shufan Xu, and Hirofumi Shinohara Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan
12:10		Lunch

Session 3: Power Devices

14:10	3‑1	Distributed field plate effects in split-gate trench MOSFETs R. Tambone1,2, A. Ferrara1, F. Magrini3, A. Hoffmann3, A. Wood1, G. Noebauer1, E. Gondro3, and R.J.E. Hueting2 1 Infineon Technologies Austria AG, Siemenstrasse 2, 9500 Villach, Austria 2 University of Twente, Drienerlolaan 5, 7522 NB Enschede, The Netherlands 3 Infineon Technologies AG, Am Campeon 1, 85579 Neubiberg, Germany
14:30	3‑2	Measuring of parasitic resistance of stacked chip of Si power device Tatsuya Ohguro1, Hideharu Kojima1, Takuma Hara1, Tatsuya Nishiwaki2 and Kenya Kobayashi1 1 Toshiba Electronic Devices & Storage Corporation, 1-1, Iwauchi-Machi, Nomi, Ishikawa, Japan 2 Toshiba Electronic Devices & Storage Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
14:50	3‑3	New Extraction Method for Intrinsic Qrr of Power MOSFETs T. Hara, S. Nakajima, T. Ohguro and K. Miyashita Advanced Semiconductor Device Development Center, Toshiba Electronic Devices & Storage Corporation
15:10	3‑4	On-Resistance Measurements of Low Voltage MOS-FET at wafer level Kohei Oasa1, Tatsuya Nishiwaki1, Tatsuya Ohguro2, Yasunobu Saito1, and Yusuke Kawaguchi2 1 Toshiba Electronic Devices & Storage Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan 2 Toshiba Electronic Devices & Storage Corporation, 1-1, Iwauchi-Machi, Nomi, Ishikawa, Japan
15:30	3‑5	Comparative study on characteristics of GaN-based MIS-HEMTs with Al2O3 and Si3N4 gate insulators under Hot Carrier Degradation Pei-Yu Wu1, Xin-Ying Tsai2, Ting-Chang Chang3, Tsung-Ming Tsai1 and Simon M. Sze2 1 Pei-Yu Wu and Tsung-Ming Tsai are with the Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan 2 Xin-Ying Tsai and Simon M. Sze are with the Department of Electronics Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan 3 Ting-Chang Chang is with Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan
15:50		Break

Session 4: Measurement Technique

16:20	4‑1	The Pressing Probe Needle Technique for Characterizing Mechanical Stress Sensitivity of Semiconductor Devices Hans Tuinhout, Oliver Dieball NXP Semiconductors, Eindhoven, The Netherlands
16:40	4‑2	A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact Yen-Ling Chen, Shih-Hao Lai, Jian-Hao Lin, and Bing-Yue Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C.
17:00	4‑3	Test Structure for Evaluation of Pad Size for Wafer Probing Brad Smith1, Donald Hall1, and Garrett Tranquillo2 1 NXP Semiconductors, Austin, TX, USA 2 Celadon Systems, Inc., Burnsville, MN, USA
17:20	4‑4	Test Bench for Biopotential Instrumentation Amplifier using Single-Ended to Differential Amplifiers Surachoke Thanapitak, Pongsatorn Sedtheetorn, Pornchai Chanyagorn, Tatcha Chulajata, Somnida Bhatranand, and Phattanard Phattanasri Department of Electrical Engineering, Faculty of Engineering, Mahidol University Nakhon Pathom, Thailand
17:40		End of Day 1

Session 5: Matching & Variability

08:30	Bonus	How to make better abstract
09:00	5‑1	Measurement of Temperature Effect on Comparator Offset Voltage Variation Yuma Iwata, Takehiro Kitamura, and Mahfuzul Islam Department of Electrical Engineering, Graduate School of Engineering, Kyoto University, JAPAN
09:20	5‑2	Variability of MOSFET Series Resistance Extracted from Individual Devices: Is Direct Variability Measurement Possible? Kiyoshi Takeuchi1, Tomoko Mizutani1, Takuya Saraya1, Masaharu Kobayashi1,2, and Toshiro Hiramoto1 1 Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 2 System Design Research Center (d.lab), The University of Tokyo, Tokyo, Japan
09:40	5‑3	Variability Evaluation of MOS-gated PNPN Diode for Hardware Spiking Neural Network Toshihiro Takada, Takayuki Mori, and Jiro Ida Division of Electrical Engineering, Kanazawa Institute of Technology, Ishikawa, Japan
10:00	5‑4	Effect of Quadruple Size Transistor on SRAM Physically Unclonable Function Stabilized by Hot Carrier Injection Shufan Xu1, Kunyang Liu2, Yichen Tang1, Ruilin Zhang1, and Hirofumi Shinohara2 1 Information, Production and Systems Research Center, Waseda University, Kitakyushu, Japan 2 Graduate School of Information, Production and Systems, Kitakyushu, Japan
10:20		Break

Session 6: Yield and Device Optimization

10:50	6‑1	Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications Hao-Chiao Hong1,2, Long-Yi Lin1,3, and Bo-Chang Chen2 1 Institute of Electrical and Computer Engineering, 2 Institute of Electrical and Control Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan 3 Novatek MicroElectronics Corp., Hsinchu, Taiwan
11:10	6‑2	Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation V.Vidya1, N. Zamdmer1, T. Mechler1, K. Onishi1, D. Chidambarao1, B. W. Jeong2, Y. G. Ko2, C. H. Lee1, J. Sim1, M. Angyal1, E. Crabbe1 1 IBM Systems, IBM Corp, 2070 Route 52, B300-A, Hopewell Junction, NY 12533, USA 2 Samsung Electronics Co. Ltd, San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, 445-701, Republic of Korea
11:30	6‑3	An Electrical Inline-Testable Structure to Monitor Gate-Source/Drain Short Defect Caused by Imperfect Fin-Cut Patterning in FinFET Technology Hai Zhu1, Katsunori Onishi1, Stephen Wu1, Adam Yang1, Byoung-Wook Jeong2, Seong-Joon Lim2, Nan Jing1, Choong-Ho Lee1, David Conrady1, and Dureseti Chidambarrao1 1 IBM Systems, IBM Corp, 2070 Route 52, B300A, Hopewell Junction, NY 12533, USA 2 Samsung Electronics Co. Ltd., San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, 445-701, Republic of Korea
11:50	6‑4	Wafer Level Reliability Monitoring of NBTI Using Polysilicon Heater Structures for Production Measurements Yu-Hsing Cheng Central Engineering, onsemi 1900 South County Trail, East Greenwich, RI 02818, USA
12:10		Lunch
13:40	Bonus	How to make better presentation
14:10		ICMTS 2024
14:25		Break

Session 7: MEMS & Sensors

14:55	7‑1	Application of Greek cross structures for process development of electrochemical sensors Minxing Zhang1, Shan Zhang1,2, Camelia Dunare1,2, Jamie R. K. Marland1,2, Jonathan G. Terry1,2, Stewart Smith1,3 1 School of Engineering, The University of Edinburgh, Edinburgh, Scotland, UK 2 Research Institute for Micro and Nano Systems 3 Research Institute for Bio-Engineering
15:15	7‑2	Test Structures for Studying Coplanar Reverse- Electrowetting for Vibration Sensing and Energy Harvesting Anotidaishe Moyo1, Muhammad Wakil Shahzad1, Jonathan G. Terry2, Stewart Smith2, Yoshio Mita3, Yifan Li1 1 Department of Mechanical and Construction Engineering, Faculty of Engineering and Environment, Northumbria University, UK 2 School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, UK 3 Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan
15:35	7‑3	Damage Assessment Structure of Thermal-Annealing Post-Processing on CMOS LSIs Yuki Okamoto1, Natsumi Makimoto1, Kei Misumi2, Takeshi Kobayashi1, Yoshio Mita2, Masaaki Ichiki1 1 Sensing System Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan 2 School of Electrical Engineering, The University of Tokyo, Tokyo, Japan
15:55	7‑4	Improving Performance of FBARs by Advanced Low-Temperature High-Pressure Technology Yu-Fa Tu1, Ting-Chang Chang2,3, Kuan-Ju Zhou2, Wei-Chun Hung2, Ting-Tzu Kuo4, and Chen-Hsin Lien1 1 Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan 2 Department of Physics, National Sun Yat-sen University, Kaohsiung 80424, Taiwan 3 Center of Crystal Research, National Sun Yat-sen University, Kaohsiung 80424, Taiwan 4 Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan
16:15	7‑5	Solderable Multisided Metal Patterns Enables 3D Integrable Direct Laser Written Polymer MEMS Landon Ivy and Amit Lal The SonicMEMS Laboratory, School of Electrical and Computer Engineering, Cornell University, USA
16:35		Break
18:00		Banquet Chinzanso - Tokyo 2 Chome-10-8 Sekiguchi, Bunkyo City, Tokyo 112-8680 https://hotel-chinzanso-tokyo.com
20:00		End of Day 2

Session 8: Modeling

09:00	8‑1	Accurate Gate Charge Modeling of HV LDMOS Transistors for Power Circuit Applications Xiaorui Jie, Ronald van Langevelde, Kejun Xia1, Lei Chao, Colin C. McAndrew, Qilin Zhang, Matthew Bacchi2, and Wuxia Li NXP Semiconductors, Front End Innovation 1 TSMC, Special Technology Product Engineering 2 NXP Semiconductors, Business Line Advanced Analog
09:20	8‑2	Introducing Transfer Learning Framework on Device Modeling by Machine Learning Kota Niiyama, Hiromitu Awano, and Takashi Sato Graduate School of Informatics, Kyoto University
09:40	8‑3	Technology-Dependent Modeling of MOSFET Parasitic Capacitances for Circuit Simulation Dondee Navarro, Chika Tanaka, Kanna Adachi1, Takeshi Naito, Kenshi Tada and Akira Hokazono Memory Division, KIOXIA Corporation, Yokohama, Japan 1 Institute of Memory Technology Research and Development, KIOXIA Corporation, Yokohama, Japan
10:00		Break

Session 9: Novel Materials

10:30	9‑1	Bridging Large-Signal and Small-Signal Responses of Hafnium-Based Ferroelectric Tunnel Junctions M. Massarotto1, M. Segatto1, F. Driussi1, A. Affanni1, S. Lancaster2, S. Slesazeck2, T. Mikolajick2,3, D. Esseni1 1 DPIA, University of Udine, Udine, Italy 2 NaMLab gGmbH, Dresden, Germany 3 Chair of Nanoelectronics, IHM, TU–Dresden, Germany
10:50	9‑2	Demonstration of frequency doubler application using ZnO–DNTT anti-ambipolar switch device Yongsu Lee, Hyeon Jun Hwang, and Byoung Hun Lee Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, Gyeongbuk 37673, Republic of Korea
11:10	9‑3	Identifying nano-Schottky diode currents in silicon diodes with 2D interfacial layers Tihomir Knežević1, Lis K. Nanver2 1 Ruđer Bošković Institute, Zagreb, Croatia 2 MESA+ Institute of Nanotechnology, University of Twente, Enschede, The Netherlands
11:30		Close + Best Paper Award