IEEE International Conference on Microelectronic Test Structures
ICMTS 2026 Tutorials
Monday, Mar 23
| 08:30 | Registration Desk Opens | ||
| 08:55 | Tutorials Welcome Takayuki Mori (Tutorial Chair) Kanazawa Institute of Technology | ||
| 09:00 | T1 | Fundamentals of Test Structures and Measurement Stewart Smith The University of Edinburgh William Thomson (Lord Kelvin) made many statements applicable to measurement as well as having his name applied to test structures and measurement techniques widely used by ICMTS attendees. Whether or not he actually said “If you can not measure it, you cannot improve it” is unclear but it definitely applies to the field of microelectronic test structures. This tutorial will begin with a short review of test structures detailing their history and hot topics over the past 40+ years. Test structures, instrumentation and measurement techniques for the resistive, capacitive and active devices will be introduced and discussed, as well as some of the measurement issues you may encounter. |  |
| 09:50 | T2 | Device and Process technologies for advanced logic semiconductor Masaharu Kobayashi The University of Tokyo High performance computing enabled by semiconductor integrated circuits is the infrastructure for AI technologies. Recent advancement of generative AI technologies demand high computing performance than ever before. On the other hand, power composition accompanied by AI technologies becomes the challenge for sustainable society. Scaling of the semiconductor technology is expected to contribute to higher performance and lower power computing. In this presentation, I will overview the device and process technologies in advanced logic semiconductor, which will be the key for tackling the challenges. |  |
| 10:40 | Break | ||
| 11:00 | T3 | Advanced Packaging Technologies Enabling Chiplet-Based Systems Fumihiro Inoue Yokohama National University The rapid growth of cloud AI has driven extreme requirements for compute density, memory bandwidth, and energy efficiency, exposing the physical and economic limits of monolithic system-on-chip (SoC) scaling. Chiplet-based architectures have therefore emerged as a scalable integration approach, enabling functional partitioning and heterogeneous system design. In this context, advanced packaging technologies, particularly hybrid bonding, play a central role. Hybrid bonding provides ultra-fine-pitch, low-resistance interconnects with energy efficiency approaching on-die wiring, making it a key enabler for tightly coupled logic–memory integration and high-performance AI systems. This tutorial introduces advanced packaging technologies with a focus on hybrid bonding for chiplet-based integration. Core concepts of 2.5D and 3D integration are outlined, followed by discussion of hybrid bonding processes, design considerations, and reliability challenges. The impact of bonding technology on power delivery, thermal management, and system scalability is examined through examples from cloud AI accelerators. The tutorial also extends the discussion from cloud AI to edge AI systems, where power efficiency, form factor, and cost constraints further emphasize the importance of fine-pitch, low-overhead interconnect technologies. Future trends toward die-to-wafer hybrid bonding and system-level co-design are briefly discussed. |  |
| 11:50 | Lunch | ||
| 13:20 | T4 | Fundamentals of RF measurements, modeling, and test structure design Shuhei Amakawa Hiroshima University This tutorial will cover basic concepts in RF, related to measurements, modeling, and test structure design. It will first introduce the basic physical picture of wave propagation along a transmission line in a way understandable to IC designers not necessarily specializing in RF. It will then discuss the concept of S-parameters and how measurement/simulation reference planes should be defined. Some practical measurement and modeling issues will be presented that the speaker encountered and dealt with when working with frequencies above 100 GHz, together with design recommendations. |  |
| 14:10 | T5 | Next Generation Power Electronics Technologies Based on Wide Bandgap Semiconductors Yasunori Tanaka National Institute of Advanced Industrial Science and Technology The advancement of next-generation power electronics technologies based on wide-bandgap semiconductors has accelerated dramatically over the past two to three years. In particular, SiC power semiconductors, owing to their superior material properties, have been rapidly put into practical use as key devices that significantly contribute to higher efficiency and reduced size and weight of power converters in the field of electric mobility, including railway systems and electric vehicles (EVs). As a result, SiC power devices are steadily establishing their position as a fundamental technology underpinning an electrified society. In this presentation, an overview will be provided of the characteristics of next-generation power semiconductor devices, focusing on SiC, as well as related device process and design technologies. |  |
| 15:00 | Break | ||
| 15:20 | T6 | Key Device Technologies and Challenges for 3D Non-Volatile Memory Masumi Saitoh Kioxia Corporation This tutorial provides an overview of recent research trends in 3D non-volatile memory. Non-volatile memory is moving to 3D stacking for increasing the bit density to meet the demand for large datasets of AI. There are two main 3D approaches: vertical stacking (e.g. 3D flash memory) and horizontal stacking (e.g. cross-point memory). 3D flash memory has been leading aggressive multi-layer stacking of non-volatile memory. Stacked ReRAM (Resistive RAM) and PCM (Phase Change Memory) have been proposed for various applications including in-memory computing. Ferroelectric memory with ferroelectric HfO film has been widely studied for various 3D structures such as FeFET (Ferroelectric FET), FeRAM (Ferroelectric RAM), and FTJ (Ferroelectric Tunnel Junction). MRAM (Magnetic RAM) with advanced MTJ has been developed for high-speed and high-density cross-point memory. There remain key challenges such as process integration, reliability, and device variability, requiring tight collaboration between basic research and manufacturing to deliver low-cost and high-performance 3D non-volatile memory. |  |
| 16:10 | T7 | Silicon quantum computer and cryo-CMOS technologies Takahiro Mori National Institute of Advanced Industrial Science and Technology Quantum computers aim to solve some computational problems that are difficult for conventional technologies to solve. There are currently some candidates for their hardware, and we can use some prototype machines. However, their performance is insufficient to solve practical problems, so no clear winners have emerged yet, because the number of available qubits is still low. Therefore, large-scale integration is highly desired. From this perspective, silicon qubit technology is promising because we can use mature fabrication technologies developed for LSI technology. This talk introduces silicon quantum computer technology, its research trends, and its outlook. It also introduces cryo-CMOS technology, which will be used to control qubits to realize quantum gate operation. |  |
| 17:00 | Close of Tutorials | ||
| 17:30 | Welcome Reception for All ICMTS Attendees |
