ICMTS 2018 Program

2018 Program Booklet

By Session

Bonus Talks

1	How To Write A Good Paper And Get It Published C. McAndrew NXP Semiconductors	PDF
2	Making Good Presentations B. Smith NXP Semiconductors	PDF

Session 1: Process Characterization

1.1	Test structures for debugging variation of critical devices caused by layout-dependent effects in FinFETs Q. Lin, H. Pan, J. Chang Xilinx Inc., San Jose, CA DOI: 10.1109/ICMTS.2018.8383751 ABSTRACT: The increasing stress engineering in FinFETs raises concerns about performance variation caused by the strong layout-dependent effect (LDE). The challenge is that it is difficult to decouple the combination of LDEs in a layout. As a result, it is challenging for Fab to reduce the variation induced by LDE. In this paper, we present a set of test structures for monitoring and debugging the variation of critical devices caused by LDEs. These test structures were verified in 16nm FinFET technology. We also present two case studies of debugging FinFET device variation by using these test structures.	PDF Xplore
1.2	Passive permutation multiplexer to detect hard and soft open fails on short flow characterization vehicle test chips C. Hess, S. Yu PDF Solutions Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2018.8383752 ABSTRACT: Short flow characterization vehicle test chips are a major contributor to fast learning cycles especially for BEOL process steps. While hard open fails can be easily detected even in large via chains, it is very difficult to detect soft open fails like a 100 times larger via resistance of just one via within a large chain of vias. A Passive Permutation Multiplexer (PPM) is presented to optimize the signal to noise ratio for detecting soft open fails. The PPM implements a balanced routing access to a local population of resistive Devices Under Test (DUT) such as via or contact chains. Thus, soft open fail are easily recognizable as outliers of all measured resistance values within such a local population of DUTs. Compared to traditional passive multiplexers, the PPM contains up to twice as many DUTs. Furthermore, significantly larger Design of Experiments (DOE) can be implemented, since the PPM can hold more than just one DOE level within the same array.	PDF Xplore
1.3	Novel test structures for extracting interface state density of advanced CMOSFETs using optical charge pumping H. -S. Song, D. -J. Oh, S. -Y. Kim, S. -K. Kwon, S. Choi1, D. H. Kim1, D. -H. Lim2, C. -H. Choi2, D. M. Kim1, H. -D. Lee Department of Electronics Engineering, Chungnam National University 1School of Electrical Engineering, Kookmin University 2Division of Materials Science and Engineering, Hanyang Universit DOI: 10.1109/ICMTS.2018.8383753 ABSTRACT: In this paper, we proposed novel test structures to evaluate the distribution of interface state density of MOSFETs by using optical charge pumping method. Unlike other measurement methods to extract interface state density (Dit), which have a limited range of measurable energy states and influenced by gate area and gate leakage, Dit can be extracted without these problems by using the proposed test structures. Test structures were fabricated using a 0.18μm CMOS process or FD-SOI technology with high-k dielectric, respectively. Optical charge pumping was performed in proposed test structures and Dit is extracted from 109 cm-2· eV-1 to 1013 cm-2· eV-1.	PDF Xplore
1.4	Test structures to evaluate the impact of parasitic edge FET on circuits operating in weak inversion D. McQuirk, C. Baker, B. Smith NXP Semiconductors N.V, TX DOI: 10.1109/ICMTS.2018.8383754 ABSTRACT: Precision analog circuit accuracy in a microcontroller product was impacted by unmodeled behavior across the temperature range. Three critical analog circuits from the microcontroller were built and tested in discrete parametric test structures. It was shown that a process with reduced parasitic edge FET leakage dramatically improved the accuracy of the analog circuits, which were operating in the subthreshold region.	PDF Xplore

Session 2: Modeling and Extraction

2.1	Comprehensive investigation on parameter extraction methodology for short channel amorphous-InGaZnO thin-film transistors C. Tanaka, K. Ikeda Future Memory Development Department, Institute of Memory Technology Research & Development, Saiwai-ku, Kawasaki, Japan DOI: 10.1109/ICMTS.2018.8383756 ABSTRACT: We proposed a comprehensive parameter extraction method for short channel amorphous InGaZnO (α-InGaZnO) thin-film transistors (TFTs) on the basis of measurement data and TCAD simulations. Single parameter set were successfully extracted for channel length down to 500nm by using RPI α-Si TFT model with channel length modulation modeling. It makes possible to more accurate and scalable circuit performance characterization, since the extracted parameters correspond to the physical behavior of α-InGaZnO TFTs.	PDF Xplore
2.2	Modeling split-gate flash memory cell for advanced neuromorphic computing M. Tadayoni, S. Hariharan, S. Lemke, T. Pate-Cazal, B. Bertello, V. Tiwari, N. Do Silicon Storage Technology, A Subsidiary of Microchip Technology Inc, San Jose, California, USA DOI: 10.1109/ICMTS.2018.8383757 ABSTRACT: Split-gate flash memory technology had recently been used in neuromorphic computation where a non-volatile memory array is designed in such a way that enables high-precision tuning of individual memory elements. This work proposes for the first time a SPICE model of the two-transistor, select gate and floating gate, of the split-gate flash memory cell, implemented in a 180 nm CMOS technology, that allows the users to set the individual memory cell to any precise analog state.	PDF Xplore
2.3	Validation of the BSIM4 irregular LOD SPICE model by characterization of various irregular LOD test structures B. Peddenpohl, M. Otrokov, J. Wells Cypress Semiconductor, Lexington, Kentucky DOI: 10.1109/ICMTS.2018.8383758 ABSTRACT: Stress from FET Isolation regions affects the electrical behavior of transistors in modern technologies. Characterization and modeling of stress effects have primarily been done for transistor layouts that have rectangular (regular) shaped source and drains. However, circuits may include transistor layouts that have non-rectangular (irregular) shaped source and drains. This paper presents test structures to evaluate the effects caused by isolation stress on irregular source/drain transistor layouts, and shows that the standard way of calculating the effective distances for modeling stress effects is also reasonable for irregular source/drain transistor layouts.	PDF Xplore
2.4	Efficient parameter-extraction of SPICE compact model through automatic differentiation M. Shintani, M. Hiromoto1, T. Sato1 Graduate School of Information Science, Nara Institute of Science and Technology (NAIST), Japan 1Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2018.8383759 ABSTRACT: A novel parameter extraction method for compact MOSFET models is proposed. The proposed method exploits automatic differentiation (AD) technique that is widely used in the training of artificial neural networks. In the AD technique, gradient of all the parameters of the MOSFET model is analytically calculated as a graph to reduce computational cost. On the basis of the calculated gradient, the model parameters are efficiently optimized. Through experiments using SPICE models, the parameter extraction using the proposed method achieved 7.01x speedup compared to that using the numerical-differentiation method.	PDF Xplore

Session 3: Reliability

3.1	Test structure design for model-based electromigration E. Demircan, M. D. Shroff, H. -C. Lee NXP Semiconductors, Austin, TX, USA DOI: 10.1109/ICMTS.2018.8383761 ABSTRACT: As VLSI technology features are pushed to the limit with every generation and with the introduction of new materials and increased current densities to satisfy performance demands, failure risk due to Electromigraton (EM) is ever-increasing. In this paper, we present experimental results using a novel set of test structures to validate a new model-based EM risk assessment approach. In this method, EM risk can be assessed for any interconnect geometry through an exact solution of the fundamental stress equations. This approach eliminates the need for complex look-up tables for different geometries and can be implemented in CAD tools very easily as we demonstrate on real design examples.	PDF Xplore
3.2	Electrostatic test structures for transmission line pulse and human body model testing at wafer level R. Ashton, S. Fairbanks1, A. Bergen, E. Grund2 Minotaur Labs, Mesa, Arizona, USA 1SRF Technologies, Mesa, Arizona, USA 2Grund Technical Solutions, Milpitas, California, USA DOI: 10.1109/ICMTS.2018.8383762 ABSTRACT: New two two-pin ESD testers are capable of doing both Transmission Line Pulse (TLP) and Human Body Model (HBM) testing at wafer level. These systems facilitate using test structures to link fundamental circuit element parameters measured with TLP and expected HBM results on final products.	PDF Xplore

Session 4: Materials Characterization

4.1	Reliability analysis of the metal-graphene contact resistance extracted by the transfer length method S. Venica, F. Driussi, A. Gahoi1, S. Kataria1, P. Palestri, M. C. Lenirne1, L. Scimi Universita degli Studi di Udine, Udine, Friuli-Venezia Giulia, IT 1Rheinisch-Westfalische Technische Hochschule Aachen, Aachen, Nordrhein-Westfalen, DE DOI: 10.1109/ICMTS.2018.8383765 ABSTRACT: The transfer length method is a well-established experimental technique to characterize the contact resistance of semiconductor devices. However, its dependability is questionable for metal-graphene contacts. We investigate in-depth the statistical error of the extracted contact resistance values and we devise strategies to limit such error and to obtain reliable results. The method has been successfully applied to samples with different contact metals.	PDF Xplore
4.2	Test structures for seed layer optimisation of electroplated ferromagnetic films C. M. M. Dover, A. W. S. Ross, S. Smith, J. G. Terry, A. R. Mount, A. J. Walton School of Engineering, University of Edinburgh, UK DOI: 10.1109/ICMTS.2018.8383766 ABSTRACT: This paper presents a full wafer test structure, designed to quantify the effect of seed layer thickness and conductivity on the plating uniformity of patterned electroplated structures. The test structure enables the effect of IR drop on the electroplated film to be evaluated and provides information to help facilitate the optimisation of seed layer thickness.	PDF Xplore
4.3	Test structures without metal contacts for DC measurement of 2D-materials deposited on silicon L. K. Nanver, X. Liu, T. Knezevic1 MESA+ Institute for Nanotechnology, University of Twente, Enschede, Netherlands 1Faculty of Electrical Engineering and Computing, Micro and Nano Electronics Laboratory, Croatia DOI: 10.1109/ICMTS.2018.8383767 ABSTRACT: A set of ring-shaped test structures is presented for electrical characterization of 2D as-deposited layers on Si that electrically interact with the substrate. The test method is illustrated by investigation of 3 different nm-thin layers that are expected to form an interfacial layer of negative fixed charge. A test procedure is described that gives a low turnaround time and non-destructive way of evaluating different deposition methods in terms of diode characteristics, interface conductance, and electron carrier injection into the deposited layer.	PDF Xplore
4.4	Test structures for evaluating Al2O3 dielectrics for graphene field effect transistors on flexible substrates X. Yang, M. Bonmann, A. Vorobiev, K. Jeppson, J. Stake Department of Microtechnology and Nanoscience, Chalmers University of Technology Gothenburg, Sweden DOI: 10.1109/ICMTS.2018.8383768 ABSTRACT: We have developed a test structure for evaluating the quality of Al2O3 gate dielectrics grown on graphene for graphene field effect transistors on flexible substrates. The test structure consists of a metal/dielectric/ graphene stack on a PET substrate and requires only one lithography step for the patterning of the topside metal electrodes. Results from measurements of leakage current, capacitance and loss tangent are presented.	PDF Xplore
4.5	Design of ultraflexible organic differential amplifier circuits for wearable sensor technologies M. Kondo, T. Uemura, M. Akiyama, N. Namba, M. Sugiyama, Y. Noda, T. Araki, S. Yoshimoto1, T. Sekitani The Institute of Scientific and Industrial Research, Osaka, Japan 1The Institute of Scientific and Industrial Research, 8-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan DOI: 10.1109/ICMTS.2018.8383769 ABSTRACT: We have designed and evaluated ultraflexible organic differential amplifier circuits for wearable sensor technologies. Transistor modeling for both p-type and n-type organic thin-film transistors was prepared for circuit simulations. The developed organic amplifier shows high gain of 60 dB and operates with 3 V: it can be applied to imperceptible sensor circuits for biomedical applications.	PDF Xplore

Session 5: Mismatch and Variability

5.1	A test structure to reveal short-range correlation effects of mismatch fluctuations in backend metal fringe capacitors H. Tuinhout, A. Z. -v. Duijnhoven1, I. Brunets NXP Semiconductors, AE Eindhoven, The Netherlands 1NXP Semiconductors, High Tech Campus 46, 5656 AE Eindhoven, The Netherlands DOI: 10.1109/ICMTS.2018.8383771 ABSTRACT: This paper presents a set of test structures that revealed a thus far unknown (or at least unreported) CMP-related short-range correlated mismatch fluctuation effect on the matching of backend metal fringe capacitors. It is shown that an apparent degradation of mismatch standard deviations at medium-range distances is in fact due to an improvement of matching for devices placed at very small distances.	PDF Xplore
5.2	Monte Carlo analysis by direct measurement using Vth-shiftable SRAM cell TEG S. Yamaguchi, D. Nishikata, H. Imi, K. Nakamura Center for Microelectronic Systems, Kyushu Institute of Technology, Iizuka, Fukuoka, JAPAN DOI: 10.1109/ICMTS.2018.8383772 ABSTRACT: The measurement system in which the Monte Carlo analysis of SRAM operation can be performed in actual measurement using Vth-shiftable SRAM cell TEG (VTST) was developed. The dynamic Vth-shift circuit (DVSC) using electrolytic capacitors and mechanical relays for setting individual Vth-shift voltages for six MOSFETs in a memory cell enables to share a programmable external voltage source. The measured results of the Monte Carlo analysis for SRAM function test and the static noise margin evaluation were agreed well with the simulated results. The proposed method can compactly cope with the recently proposed SRAM with a larger number of transistors.	PDF Xplore
5.3	Process variation estimation using a combination of ring oscillator delay and FlipFlop retention characteristics T. Konno, S. Nishizawa, K. Ito Faculty of Engineering, Saitama Univesity 255, Sakura-Ku Saitama, Japan DOI: 10.1109/ICMTS.2018.8383773 ABSTRACT: We propose an extraction method of process variation utilizing D-Flip-Flop (DFF) data retention characteristics and Ring Oscillator(RO) oscillation delay. Extracted process variation is modeled as PMOS and NMOS threshold voltage variations. Retention characteristics of the DFF circuit has different sensitivity to threshold voltage variation from the RO circuit. A DFF circuit is newly introduced as a complementary test structure of the conventional RO circuit for process variation extraction. By combining the RO circuit and the DFF circuits, we can accurately estimate the shift of global process variation. The test structure is implemented into silicon chip and the amount of global variation shift is extracted from measured data.	PDF Xplore
5.4	NPN mismatch dependence on layout C. Compton Macom, Newport Beach, CA DOI: 10.1109/ICMTS.2018.8383774 ABSTRACT: Mismatch structures are normally designed to look at pairs of identical devices with near ideal layouts. In this paper we look into the effects of orientation and NPN density on the mismatch results of NPNs in two 0.18um SiGe BiCMOS process. The mismatch structures were added to scribeline PCM modules, which allowed us to look at the results from multiple mask sets.	PDF Xplore

Session 6: On-Chip Characterization

6.1	On-chip reconfigurable monitor circuit for process variation and temperature estimation T. Kishimoto, T. Ishihara, H. Onodera Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2018.8383777 ABSTRACT: This paper proposes a monitor circuit that can estimate process variation and temperature by circuit reconfiguration. The circuit topology of the temperature monitoring is crafted such that the oscillation frequency is determined by the amount of leakage current which has an exponential dependency to temperature. The voltage dependence of this circuit is small in the configuration for temperature measurement, and the temperature dependence is small in the configuration for process variation estimation. A test chip fabricated in a 65 nm CMOS process demonstrates the temperature estimation capability with accuracy within -0.3 °C to 0.4 °C over a temperature range of 10 ° C to 100 °C, as well as the ability for estimating process variations.	PDF Xplore
6.2	DFT-enabled within-die AC uniformity and performance monitor structure for advanced process N. Chong, I. -R. Chen1, D. Cheng, A. Majumdar1, P. -C. Yeh1, J. Chang1 Xilinx Inc, San Jose, CA, US 1Xilinx Inc., San Jose, California, USA DOI: 10.1109/ICMTS.2018.8383778 ABSTRACT: An on-chip ring oscillator based process monitoring vehicle embedded within host automatic place and route digital blocks and accessed through design for testability (DFT) circuit is introduced and characterized. Within-wafer AC uniformity (ACU), performance and power consumption for the ring oscillator are analyzed in a 7 nanometer technology testchip. The design and analysis techniques described are suitable to monitor process variation, real-time power fluctuation and performance proxy of host digital blocks in products.	PDF Xplore
6.3	Versatile chip-level integrated test vehicle for dynamic thermal evaluation S. Parameswaran, S. Balakrishnan, B. Ang Silicon Technology Group Xilinx, Inc. 2100 Logic Drive, San Jose, CA, USA DOI: 10.1109/ICMTS.2018.8383779 ABSTRACT: Thermal management of semiconductor chips is becoming very important as the demand for chip performance increases. It is necessary to evaluate/manage the thermal aspects of a chip throughout the development cycle - starting from initial planning stage to deployment on customer board and beyond. In this paper, we present a versatile thermal evaluation vehicle that addresses the above requirements. This paper describes the circuit architecture/implementation, details of operation, programming aspects, usage model and various applications of a silicon chip that is successfully used as a thermal evaluation tool. The chip has 1600 sectors with programmable heat-generation and temperature-sensing capability - enabling it to generate up to 3W per mm2 and has a temperature detection range of 30C to 125C with an accuracy of +/-2C. It has a simple implementation and is easy to program and test - yet has substantial thermal evaluation capabilities. It was fabricated in 0.18um technology and packaged as flip-chip. The chip has ability to do automated on-chip temperature measurements through a tester-friendly interface and has been successfully controlled through a simple and inexpensive test-platform. The ability to generate heat on-die and monitor spatial & temporal on-die temperature makes this chip suitable to emulate many different use cases of a product during the development stage ahead of product silicon availability. The capabilities of this test-vehicle make it a suitable candidate for demonstrating power-aware/thermal-aware testing. Silicon measurement data and comparison to simulation results based on numerical models are also presented in this paper.	PDF Xplore
6.4	All-digital on-chip heterogeneous sensors for tracking the minimum energy point of processors S. Hokimoto, J. Shiomi, T. Ishihara, H. Onodera Graduate School of Informatics, Kyoto University, Kyoto, JAPAN DOI: 10.1109/ICMTS.2018.8383780 ABSTRACT: Dynamically scaling the supply voltage (VDD) and the threshold voltage (VTH) is one of the most effective approaches for reducing the energy consumption of processors. However, since the best pair of VDD and VTH, which minimizes the energy consumption of processors is strongly dependent on the operating condition such as an activity factor and a performance required for the processor, it is not trivial to find the best pair of the voltages at runtime when the operating condition widely varies. With all-digital on-chip heterogeneous sensors, we propose a simple runtime method to accurately identify the best pair of VDD and VTH, which minimizes the energy consumption of a processor under a specific operating condition which is determined by a process variation, an activity factor, and a performance requirement for the processor. Measured results for a 32-bit RISC processor integrating the heterogeneous sensors show that the proposed method successfully tracks the minimum energy operating point (i.e. the best pair of VDD and VTH) of the processor even in a case that the operating condition widely varies.	PDF Xplore

Session 7: Test Parallelism

7.1	Addressable test structure design enabling parallel testing of reliability devices L. DeBruler, D. Pretti, M. Violette, D. Peterson, S. Mujumdar, X. Li, K. Marr Micron Technology Inc., Boise, Idaho DOI: 10.1109/ICMTS.2018.8383783 ABSTRACT: This new design enabled an efficient layout of breakdown test devices for parametric and reliability testing. These reliability circuits consisted of interlocking combs of routing layers with varying widths and spaces that were representative of the design rules. These were accessed through multiplexer controlled pass gates. All addresses could be simultaneously enabled for stress biasing and addressed individually for failure detection. Once a breakdown was detected, as current leakage of the comb, each device could be addressed sequentially to find the failing structure. This was an improvement over previous designs which either grouped many devices in parallel, but could not electrically identify which device was failing, or only had a single device enabled, but suffered from poor pad efficiency. The grouping of these devices allows for simultaneous parallel stressing of each force and ground pad pair on the parametric testers. Electrical measurement showed that the same breakdown voltage values measured on this mux design were the same as standalone devices.	PDF Xplore
7.2	Algorithm based adaptive parametric testing for outlier detection and test time reduction V. Katragadda, M. Muthee, A. Gasasira, F. Seelmann, J. -H. Liao GLOBALFOUNDRIES, New York, USA DOI: 10.1109/ICMTS.2018.8383784 ABSTRACT: Parallel test capability, enabled by numerous independent measurement channels has significantly increased throughput in parametric testing. It involves testing of numerous devices simultaneously synchronously or asynchronously. The number of devices tested for a given pad layout is increased by using higher dimensional arrays, the hallmark of which is pad sharing. Parallel testing of multiple devices with shared pads is vulnerable to device fails, where a failing device adversely affects measurement of all other devices. Information about this failing device or compromised measurement would only be evident at post analysis where a retest with a recipe change can then be ordered. In some cases retest is impossible as wafers would have already moved on to subsequent processing steps, thereby losing valuable learning opportunity. On the other hand, having to wait for post analysis requires time. Ideally failure detection and subsequent re-measure is done dynamically while the device is under test. This would require that decision making capability to be implemented in an automated tester equipment. In this work, we will discuss an algorithm based approach to adaptively change the test program allowing testing or skipping devices based on data collected real time while device is under test. The adaptive algorithm is also extended to aid in test time efficiency by eliminating tests based on measurement results of preceding tests.	PDF Xplore

Session 8: Device Characterization

8.1	Evaluation of Qss on SOI back Si/SiO2 interface by newly designed charge pumping method-TEG K. Takeda, J. Ida, T. Mori, Y. Arai1 Division of Electrical Engineering, Kanazawa Institute of Technology, Ishikawa, Japan 1High Energy Accelerator Research Org.,(KEK), Tsukuba, Japan DOI: 10.1109/ICMTS.2018.8383786 ABSTRACT: The surface state density (Qss) of SOI back Si/SiO2 interface was evaluated by newly designed Charge Pumping (CP) method-TEG. The CP method was also re-examined to apply to the thick oxide MOS. It was noted that the high voltage amplitude and attention on the slope on the gate pulse are necessary to evaluate the Qss of SOI back interface made of the thick oxide. It was founded out that the Qss of SOI back interface (bonded wafer interface) is comparable to that of the thermal oxidation interface and also that the Qss of Floating Zone (FZ) wafer is larger than that of Czochralski (CZ) wafer, and the Qss of FZ wafer varies from lot to lot.	PDF Xplore
8.2	Quantitative model of CMOS inverter chain ring oscillator's effective capacitance and its improvements in 14nm FinFET technology S. Y. Mun, J. Cho1, B. Zhu, P. Agnihotri, C. Y. Wong, T. J. Lee, V. Mahajan, B. W. Liu, Y. J. Shi, W. Hong, J. Ciavatti, J. G. Lee, S. B. Samavedam, D. K. Sohn ATD 14NM Device Globalfoundries, NY, Malta 12Global TCAD, Santa Clara, CA DOI: 10.1109/ICMTS.2018.8383787 ABSTRACT: The quantitative model of effective total capacitance, Ceff, of a CMOS ring oscillator (R/O) inverter chain in a 14nm node FinFET 3D structure using advanced Replacement Metal Gate (RMG) is successfully extracted using all the unit capacitance components comprising the R/O, such as inverter, fan-out (F/O) MOSCAP, and metal routing. The extracted Ceff model is well validated by perfect matching to the measured Si Ceff in the R/O. This paper provides a concise and clear Ceff quantitative model of inverter R/O chain using individual transistor capacitance components such as channel capacitance (Cgc), overlap capacitance (Cov), junction capacitance (Cj) and metal wire capacitance (Cwire) considering the R/O layout and its operation mechanism, which has never been reported before. Furthermore, Cov is decomposed with the gate to contact capacitance (Cmol), EPI source-drain (S/D) to gate on Fin top (Cft), EPI S/D to gate on Fin sidewall (Cfb) and intrinsic gate to S/D overlap capacitance (Cdo) with Si data and simulation. Contribution to Ceff by all the capacitor components from Cgc, Cmol, Cj, Cwire, Cft, Cfb and Cdo is extracted with Si validation. Cov reduction without DC performance degradation is also provided in this paper.	PDF Xplore
8.3	Measurement of IGBT trench MOS-gated region characteristics using short turn-around-time MOSFET test structures K. Takeuchi, M. Fukui, T. Saraya, K. Itou, S. Suzuki, T. Takakura, T. Hiramoto Institute of Industrial Science the University of Tokyo Tokyo, Japan DOI: 10.1109/ICMTS.2018.8383788 ABSTRACT: Trench MOSFET test structures were fabricated for evaluating IGBT MOS-gated region performance. It was found that the test structures can be used for measuring saturation and sub-threshold current, though accurate estimation of linear resistance is difficult. Charge pumping measurement can be used to evaluate the oxide/substrate interface quality, for possible application to process optimization.	PDF Xplore
8.4	Sensitivity of high-k encapsulated MoS2 transistors to I-V measurement execution time P. Bolshakov, A. Khosravi, P. Zhao, R. M. Wallace, C. D. Young, P. K. Hurley1 Department of Materials Science and Engineering, The University of Texas at Dallas, TX, USA 1Tyndall National Institute, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.2018.8383789 ABSTRACT: High-k encapsulated MoS2 field-effect-transistors were fabricated and electrically characterized. Comparison between HfO2 and Al2O3 encapsulated MoS2 FETs and their I-V response to execution time are shown. Changes in gate voltage step and integration time demonstrate that electrical characterization parameters can significantly impact device parameters such as the subthreshold swing and the threshold voltage.	PDF Xplore
8.5	Total ionizing dose effects on analog performance of 65 nm bulk CMOS with enclosed-gate and standard layout M. Bucher, A. Nikolaou, A. Papadopoulou, N. Makris, L. Chevas, G. Borghello1, H. D. Koch2, F. Faccio3 School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece 1DPIA, Universit degli Studi di Udine, Udine, Italy 2SEMi, Université de Mons, Mons, Belgium 3EP Dept., CERN, Geneva, Switzerland DOI: 10.1109/ICMTS.2018.8383790 ABSTRACT: High doses of ionizing irradiation cause significant shifts in design parameters of standard bulk silicon CMOS. Analog performance of a commercial 65 nm CMOS technology is examined for standard and enclosed gate layouts, with Total Ionizing Dose (TID) up to 500 Mrad(SiO2). The paper provides insight into geometrical and bias dependence of key design parameters such as threshold voltage, DIBL, transconductance efficiency, slope factor, and intrinsic gain. A modeling approach for an efficient representation of saturation transfer characteristics under TID from weak through moderate and strong inversion and over channel length is discussed.	PDF Xplore

Session 9: MEMS

9.1	An on-chip test structure for studying the frictional behavior of deep-RIE MEMS sidewall surfaces R. R. Reddy, Y. Okamoto1, Y. Mita1 Tokyo Daigaku, Bunkyo-ku, Tokyo, JP 1Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2018.8383792 ABSTRACT: In this paper, an on-chip micro-mechanical test structure has been developed to investigate the frictional behavior of Deep-RIE sidewall contacting surfaces of single crystal silicon which is most widely used in micromechanical systems (MEMS). The test structure is fabricated on Silicon on Insulator (SOI) wafer using standard MEMS process. Two orthogonally placed electrostatic comb-drive actuators are adopted, one comb drive is used to align a contact with the friction surfaces under a certain normal load and another one is used to generate the tangential motion on contacted sidewall surfaces. To assess the frictional behavior, both static and dynamic friction coefficients were observed on the contacted surfaces during the experiment with different DRIE process parameters. Through experiments, it was found that with the increment of normal forces, the static friction coefficient is no longer a constant value and it has less effect on dynamic friction coefficient. DRIE process parameters greatly influence the frictional properties on both static and dynamic friction coefficients.	PDF Xplore
9.2	Test structure for electrical assessment of UV laser direct fine patterned material N. Usami, A. Higo1, A. Mizushima1, Y. Okamoto, Y. Mita Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Japan 1VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2018.8383794 ABSTRACT: We propose a test structure to electrically assess direct laser fine patterning, which is entering a microelectronic era (below 10μm). Indium-Tin-Oxide (ITO) was used as a material example. High speed ITO patterning with laser ablation can contribute short turn-around-time development of opto-electrical devices, such as organic light emitting diode. However, not only machine-induced line-edge fluctuation but also the process (e.g. heat) induced material degradation may affect electrical linewidth. The aim of our test structure is to assess such critical dimension change through measurement of electrical property (i.e. conductivity). It consists of Kelvin-connection straight lines and Greek crosses with various widths. Ultraviolet (UV) laser process as well as lithography and plasma etching were applied with the same test structure. The measurement revealed that the applied direct patterning condition induced small damage, showing applicability of direct patterning in microelectronics R&D.	PDF Xplore
9.2	Wafer level characterisation of microelectrodes for electrochemical sensing applications E. O. Blair, L. P. Basanta1, I. Schmueser2, J. R. K. Marland, A. Buchoux3, A. Tsiamis4, C. Dunare, M. Normand, A. A. Stokes, A. J. Walton, S. Smith4 School of Engineering, Institute for Integrated Micro and Nanosystems 1The University of Edinburgh, Edinburgh, Edinburgh, GB 2School of Chemistry 3School of Engineering, The University of Edinburgh, Edinburgh, UK 4School of Engineering, Institute for Bioengineering DOI: 10.1109/ICMTS.2018.8383793 ABSTRACT: This work presents a system for the in-line wafer-level characterisation of electrochemical sensors. Typically, such sensors are first diced and packaged before being electro-chemically tested. By integrating their characterisation into the manufacturing process, the production of electrochemical sensors becomes more efficient and less expensive as they can be parametrically tested midway through the fabrication process, without the need to package them. This enables malfunctioning or failed devices to be identified before dicing and reduces costs as only functional devices are packaged (in many cases this can be more expensive than the sensor fabrication). This study describes wafer-level characterisation of a simple electrochemical sensor design using a photoresist hydrophobic corralling film for the electrolyte and a probe station for contacting to individual dies.	PDF Xplore
9.3	Open model for external mechanical stress of semiconductors and MEMS R. T. Buhler, R. C. Giacomini Department of Electrical Engineering, Centro Universitä¡rio FEI, SP, Brazil DOI: 10.1109/ICMTS.2018.8383795 ABSTRACT: This paper defines the details of the bending equipment solution and the calibration required for characterization of external mechanical stress in semiconductors and MEMS. The equipment is suited for use in probe station for electrical characterization of devices under controlled external mechanical stress.	PDF Xplore

Session 10: Noise and RF

10.1	Importance of complete characterization setup on on-wafer TRL calibration in sub-THz range C. Yadav, M. Deng, M. De Matos, S. Fregonese, T. Zimmer IMS Laboratory, University of Bordeaux, Talence cedex, France DOI: 10.1109/ICMTS.2018.8383798 ABSTRACT: In this paper, we present the effect of different sub-mm and mm-wave probe geometry and topology on the measurement results of dedicated test-structures calibrated with on-wafer TRL. These results are compared against 3D EM simulation of the intrinsic test-structures. To analyze difference between the measured and intrinsic EM simulation results, on-wafer TRL calibration performed on EM simulation results of a dedicated test-structure is also presented.	PDF Xplore
10.2	Measurement time reduction technique for input referred noise of dynamic comparator Y. Ishijima, S. Nakagawa, H. Ishikuro Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japan DOI: 10.1109/ICMTS.2018.8383799 ABSTRACT: Time reduction technique for the measurement of input referred noise of dynamic comparator is presented. By using binary search technique, the proposed method can reduce the measurement time of comparator input referred noise to (log2n)/n, where n is a required resolution. Experimental results obtained by the developed measurement system shows good correspondence with the simulated input referred noise.	PDF Xplore
10.3	System aware DUT design for optimum on-wafer noise measurement C. -H. Chen, B. Yang, P. -H. Chu, G. Brown, S. Das Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, Canada DOI: 10.1109/ICMTS.2018.8383800 ABSTRACT: This paper presents a system-aware design of device-under-tests (DUT) for optimum high-frequency (HF) on-wafer noise measurement. It overcomes the challenges in modeling the bias and geometry dependence of noise sources due to the voltage drop in the interconnections at the output port of a large DUT. It also prevents the measurement inaccuracy resulted from insufficient noise from a small DUT. Experimental data and suggested device sizes for different technologies are presented.	PDF Xplore
10.4	Measurement of temperature effect on random telegraph noise induced delay fluctuation A. K. M. M. Islam, M. Oka1, H. Onodera1 Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan 1Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2018.8383801 ABSTRACT: We present detailed measurement results of temperature effect on Random Telegraph Noise (RTN) induced delay fluctuation using a test chip fabricated in a 65-nm Silicon-On-Thin-Buried-Oxide process. Skewed ring oscillators (ROs) are used to characterize pMOFSET and nMOSFET specific RTN effects. Distributions of overall threshold fluctuation of a device have been extracted such that the simulated delay distribution matches with the measured delay distribution. For worst-case delay prediction, circuit analysis with Δντ distribution model for low temperature is necessary. Estimation results reveal that RTN amplitude decreases slightly with the increase of temperature. However, low correlation of 0.3 to 0.4 has been observed across temperatures ranging from 0 °C to 80 °C for delay paths. We find appearing and disappearing of traps across the temperature range causing the low correlation. Low correlation poses challenges in realizing robust runtime performance compensation techniques such as replica critical path based delay compensation.	PDF Xplore

By First Author

1	How To Write A Good Paper And Get It Published C. McAndrew NXP Semiconductors HOVER FOR ABSTRACT
2	Making Good Presentations B. Smith NXP Semiconductors HOVER FOR ABSTRACT
3.2	Electrostatic test structures for transmission line pulse and human body model testing at wafer level R. Ashton, S. Fairbanks1, A. Bergen, E. Grund2 Minotaur Labs, Mesa, Arizona, USA 1SRF Technologies, Mesa, Arizona, USA 2Grund Technical Solutions, Milpitas, California, USA DOI: 10.1109/ICMTS.2018.8383762 HOVER FOR ABSTRACT	PDF Xplore
9.2	Wafer level characterisation of microelectrodes for electrochemical sensing applications E. O. Blair, L. P. Basanta1, I. Schmueser2, J. R. K. Marland, A. Buchoux3, A. Tsiamis4, C. Dunare, M. Normand, A. A. Stokes, A. J. Walton, S. Smith4 School of Engineering, Institute for Integrated Micro and Nanosystems 1The University of Edinburgh, Edinburgh, Edinburgh, GB 2School of Chemistry 3School of Engineering, The University of Edinburgh, Edinburgh, UK 4School of Engineering, Institute for Bioengineering DOI: 10.1109/ICMTS.2018.8383793 HOVER FOR ABSTRACT	PDF Xplore
8.4	Sensitivity of high-k encapsulated MoS2 transistors to I-V measurement execution time P. Bolshakov, A. Khosravi, P. Zhao, R. M. Wallace, C. D. Young, P. K. Hurley1 Department of Materials Science and Engineering, The University of Texas at Dallas, TX, USA 1Tyndall National Institute, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.2018.8383789 HOVER FOR ABSTRACT	PDF Xplore
8.5	Total ionizing dose effects on analog performance of 65 nm bulk CMOS with enclosed-gate and standard layout M. Bucher, A. Nikolaou, A. Papadopoulou, N. Makris, L. Chevas, G. Borghello1, H. D. Koch2, F. Faccio3 School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece 1DPIA, Universit degli Studi di Udine, Udine, Italy 2SEMi, Université de Mons, Mons, Belgium 3EP Dept., CERN, Geneva, Switzerland DOI: 10.1109/ICMTS.2018.8383790 HOVER FOR ABSTRACT	PDF Xplore
9.3	Open model for external mechanical stress of semiconductors and MEMS R. T. Buhler, R. C. Giacomini Department of Electrical Engineering, Centro Universitä¡rio FEI, SP, Brazil DOI: 10.1109/ICMTS.2018.8383795 HOVER FOR ABSTRACT	PDF Xplore
10.3	System aware DUT design for optimum on-wafer noise measurement C. -H. Chen, B. Yang, P. -H. Chu, G. Brown, S. Das Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, Canada DOI: 10.1109/ICMTS.2018.8383800 HOVER FOR ABSTRACT	PDF Xplore
6.2	DFT-enabled within-die AC uniformity and performance monitor structure for advanced process N. Chong, I. -R. Chen1, D. Cheng, A. Majumdar1, P. -C. Yeh1, J. Chang1 Xilinx Inc, San Jose, CA, US 1Xilinx Inc., San Jose, California, USA DOI: 10.1109/ICMTS.2018.8383778 HOVER FOR ABSTRACT	PDF Xplore
5.4	NPN mismatch dependence on layout C. Compton Macom, Newport Beach, CA DOI: 10.1109/ICMTS.2018.8383774 HOVER FOR ABSTRACT	PDF Xplore
7.1	Addressable test structure design enabling parallel testing of reliability devices L. DeBruler, D. Pretti, M. Violette, D. Peterson, S. Mujumdar, X. Li, K. Marr Micron Technology Inc., Boise, Idaho DOI: 10.1109/ICMTS.2018.8383783 HOVER FOR ABSTRACT	PDF Xplore
3.1	Test structure design for model-based electromigration E. Demircan, M. D. Shroff, H. -C. Lee NXP Semiconductors, Austin, TX, USA DOI: 10.1109/ICMTS.2018.8383761 HOVER FOR ABSTRACT	PDF Xplore
4.2	Test structures for seed layer optimisation of electroplated ferromagnetic films C. M. M. Dover, A. W. S. Ross, S. Smith, J. G. Terry, A. R. Mount, A. J. Walton School of Engineering, University of Edinburgh, UK DOI: 10.1109/ICMTS.2018.8383766 HOVER FOR ABSTRACT	PDF Xplore
1.2	Passive permutation multiplexer to detect hard and soft open fails on short flow characterization vehicle test chips C. Hess, S. Yu PDF Solutions Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2018.8383752 HOVER FOR ABSTRACT	PDF Xplore
6.4	All-digital on-chip heterogeneous sensors for tracking the minimum energy point of processors S. Hokimoto, J. Shiomi, T. Ishihara, H. Onodera Graduate School of Informatics, Kyoto University, Kyoto, JAPAN DOI: 10.1109/ICMTS.2018.8383780 HOVER FOR ABSTRACT	PDF Xplore
10.2	Measurement time reduction technique for input referred noise of dynamic comparator Y. Ishijima, S. Nakagawa, H. Ishikuro Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japan DOI: 10.1109/ICMTS.2018.8383799 HOVER FOR ABSTRACT	PDF Xplore
10.4	Measurement of temperature effect on random telegraph noise induced delay fluctuation A. K. M. M. Islam, M. Oka1, H. Onodera1 Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan 1Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2018.8383801 HOVER FOR ABSTRACT	PDF Xplore
7.2	Algorithm based adaptive parametric testing for outlier detection and test time reduction V. Katragadda, M. Muthee, A. Gasasira, F. Seelmann, J. -H. Liao GLOBALFOUNDRIES, New York, USA DOI: 10.1109/ICMTS.2018.8383784 HOVER FOR ABSTRACT	PDF Xplore
6.1	On-chip reconfigurable monitor circuit for process variation and temperature estimation T. Kishimoto, T. Ishihara, H. Onodera Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2018.8383777 HOVER FOR ABSTRACT	PDF Xplore
4.5	Design of ultraflexible organic differential amplifier circuits for wearable sensor technologies M. Kondo, T. Uemura, M. Akiyama, N. Namba, M. Sugiyama, Y. Noda, T. Araki, S. Yoshimoto1, T. Sekitani The Institute of Scientific and Industrial Research, Osaka, Japan 1The Institute of Scientific and Industrial Research, 8-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan DOI: 10.1109/ICMTS.2018.8383769 HOVER FOR ABSTRACT	PDF Xplore
5.3	Process variation estimation using a combination of ring oscillator delay and FlipFlop retention characteristics T. Konno, S. Nishizawa, K. Ito Faculty of Engineering, Saitama Univesity 255, Sakura-Ku Saitama, Japan DOI: 10.1109/ICMTS.2018.8383773 HOVER FOR ABSTRACT	PDF Xplore
1.1	Test structures for debugging variation of critical devices caused by layout-dependent effects in FinFETs Q. Lin, H. Pan, J. Chang Xilinx Inc., San Jose, CA DOI: 10.1109/ICMTS.2018.8383751 HOVER FOR ABSTRACT	PDF Xplore
1.4	Test structures to evaluate the impact of parasitic edge FET on circuits operating in weak inversion D. McQuirk, C. Baker, B. Smith NXP Semiconductors N.V, TX DOI: 10.1109/ICMTS.2018.8383754 HOVER FOR ABSTRACT	PDF Xplore
8.2	Quantitative model of CMOS inverter chain ring oscillator's effective capacitance and its improvements in 14nm FinFET technology S. Y. Mun, J. Cho1, B. Zhu, P. Agnihotri, C. Y. Wong, T. J. Lee, V. Mahajan, B. W. Liu, Y. J. Shi, W. Hong, J. Ciavatti, J. G. Lee, S. B. Samavedam, D. K. Sohn ATD 14NM Device Globalfoundries, NY, Malta 12Global TCAD, Santa Clara, CA DOI: 10.1109/ICMTS.2018.8383787 HOVER FOR ABSTRACT	PDF Xplore
4.3	Test structures without metal contacts for DC measurement of 2D-materials deposited on silicon L. K. Nanver, X. Liu, T. Knezevic1 MESA+ Institute for Nanotechnology, University of Twente, Enschede, Netherlands 1Faculty of Electrical Engineering and Computing, Micro and Nano Electronics Laboratory, Croatia DOI: 10.1109/ICMTS.2018.8383767 HOVER FOR ABSTRACT	PDF Xplore
6.3	Versatile chip-level integrated test vehicle for dynamic thermal evaluation S. Parameswaran, S. Balakrishnan, B. Ang Silicon Technology Group Xilinx, Inc. 2100 Logic Drive, San Jose, CA, USA DOI: 10.1109/ICMTS.2018.8383779 HOVER FOR ABSTRACT	PDF Xplore
2.3	Validation of the BSIM4 irregular LOD SPICE model by characterization of various irregular LOD test structures B. Peddenpohl, M. Otrokov, J. Wells Cypress Semiconductor, Lexington, Kentucky DOI: 10.1109/ICMTS.2018.8383758 HOVER FOR ABSTRACT	PDF Xplore
9.1	An on-chip test structure for studying the frictional behavior of deep-RIE MEMS sidewall surfaces R. R. Reddy, Y. Okamoto1, Y. Mita1 Tokyo Daigaku, Bunkyo-ku, Tokyo, JP 1Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2018.8383792 HOVER FOR ABSTRACT	PDF Xplore
2.4	Efficient parameter-extraction of SPICE compact model through automatic differentiation M. Shintani, M. Hiromoto1, T. Sato1 Graduate School of Information Science, Nara Institute of Science and Technology (NAIST), Japan 1Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2018.8383759 HOVER FOR ABSTRACT	PDF Xplore
1.3	Novel test structures for extracting interface state density of advanced CMOSFETs using optical charge pumping H. -S. Song, D. -J. Oh, S. -Y. Kim, S. -K. Kwon, S. Choi1, D. H. Kim1, D. -H. Lim2, C. -H. Choi2, D. M. Kim1, H. -D. Lee Department of Electronics Engineering, Chungnam National University 1School of Electrical Engineering, Kookmin University 2Division of Materials Science and Engineering, Hanyang Universit DOI: 10.1109/ICMTS.2018.8383753 HOVER FOR ABSTRACT	PDF Xplore
2.2	Modeling split-gate flash memory cell for advanced neuromorphic computing M. Tadayoni, S. Hariharan, S. Lemke, T. Pate-Cazal, B. Bertello, V. Tiwari, N. Do Silicon Storage Technology, A Subsidiary of Microchip Technology Inc, San Jose, California, USA DOI: 10.1109/ICMTS.2018.8383757 HOVER FOR ABSTRACT	PDF Xplore
8.1	Evaluation of Qss on SOI back Si/SiO2 interface by newly designed charge pumping method-TEG K. Takeda, J. Ida, T. Mori, Y. Arai1 Division of Electrical Engineering, Kanazawa Institute of Technology, Ishikawa, Japan 1High Energy Accelerator Research Org.,(KEK), Tsukuba, Japan DOI: 10.1109/ICMTS.2018.8383786 HOVER FOR ABSTRACT	PDF Xplore
8.3	Measurement of IGBT trench MOS-gated region characteristics using short turn-around-time MOSFET test structures K. Takeuchi, M. Fukui, T. Saraya, K. Itou, S. Suzuki, T. Takakura, T. Hiramoto Institute of Industrial Science the University of Tokyo Tokyo, Japan DOI: 10.1109/ICMTS.2018.8383788 HOVER FOR ABSTRACT	PDF Xplore
2.1	Comprehensive investigation on parameter extraction methodology for short channel amorphous-InGaZnO thin-film transistors C. Tanaka, K. Ikeda Future Memory Development Department, Institute of Memory Technology Research & Development, Saiwai-ku, Kawasaki, Japan DOI: 10.1109/ICMTS.2018.8383756 HOVER FOR ABSTRACT	PDF Xplore
5.1	A test structure to reveal short-range correlation effects of mismatch fluctuations in backend metal fringe capacitors H. Tuinhout, A. Z. -v. Duijnhoven1, I. Brunets NXP Semiconductors, AE Eindhoven, The Netherlands 1NXP Semiconductors, High Tech Campus 46, 5656 AE Eindhoven, The Netherlands DOI: 10.1109/ICMTS.2018.8383771 HOVER FOR ABSTRACT	PDF Xplore
9.2	Test structure for electrical assessment of UV laser direct fine patterned material N. Usami, A. Higo1, A. Mizushima1, Y. Okamoto, Y. Mita Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Japan 1VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2018.8383794 HOVER FOR ABSTRACT	PDF Xplore
4.1	Reliability analysis of the metal-graphene contact resistance extracted by the transfer length method S. Venica, F. Driussi, A. Gahoi1, S. Kataria1, P. Palestri, M. C. Lenirne1, L. Scimi Universita degli Studi di Udine, Udine, Friuli-Venezia Giulia, IT 1Rheinisch-Westfalische Technische Hochschule Aachen, Aachen, Nordrhein-Westfalen, DE DOI: 10.1109/ICMTS.2018.8383765 HOVER FOR ABSTRACT	PDF Xplore
10.1	Importance of complete characterization setup on on-wafer TRL calibration in sub-THz range C. Yadav, M. Deng, M. De Matos, S. Fregonese, T. Zimmer IMS Laboratory, University of Bordeaux, Talence cedex, France DOI: 10.1109/ICMTS.2018.8383798 HOVER FOR ABSTRACT	PDF Xplore
5.2	Monte Carlo analysis by direct measurement using Vth-shiftable SRAM cell TEG S. Yamaguchi, D. Nishikata, H. Imi, K. Nakamura Center for Microelectronic Systems, Kyushu Institute of Technology, Iizuka, Fukuoka, JAPAN DOI: 10.1109/ICMTS.2018.8383772 HOVER FOR ABSTRACT	PDF Xplore
4.4	Test structures for evaluating Al2O3 dielectrics for graphene field effect transistors on flexible substrates X. Yang, M. Bonmann, A. Vorobiev, K. Jeppson, J. Stake Department of Microtechnology and Nanoscience, Chalmers University of Technology Gothenburg, Sweden DOI: 10.1109/ICMTS.2018.8383768 HOVER FOR ABSTRACT	PDF Xplore