ICMTS 2026 Program

Mar 23-26, 2026 in Matsue, Japan

Papers By Session

Session 1: Circuits for Test and Computation

1.1	Ultra-low leakage power switch for RO array characterization in 18nm FD-SOI technology platform validation C. Cagli, H. Degoirat, M. Lamy, F. Pourchon, J. B. Moulard, F. Granoux, M. Dahmani, R. Wilson STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS69943.2026.11471708 ABSTRACT: In [1] we proposed the architecture of a novel power switch implemented within a test chips (TC) in 18nm FD-SOI technology that provides DUT selection in ring oscillators (RO) array. We further improved the proposed selection circuit with a novel architecture that uses mainly thick-oxide NMOS with a level-shifter (LS). Although the footprint of the LS counts for 25% of the power switch area, this solution proves to decrease the leakage current substantially, bringing the signal-to-noise ratio up by more than two orders of magnitude, enabling the characterization of ultra-low leakage ROs.	PDF Xplore
1.2	Statistical Capacitance Measurement of Si Trench Capacitors Using 3D Stacked Array Test Circuit R. Nishimaki, K. Saito, T. Mawaki, R. Kuroda Graduate School of Engineering, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS69943.2026.11471660 ABSTRACT: A 3D stacked array test circuit is demonstrated in this paper. The array test circuit and the device under test (DUT) chip were fabricated separately, and the DUT chip was stacked on the array test circuit chip using cell-wise connections using micro-bumps. DUTs can be fabricated without the need to consider their impact on the measurement circuit chip, enabling comprehensive statistical evaluation. As DUTs, Si trench capacitors (TCs) were fabricated and a total of 9,516 TCs were measured. The measured Capacitance-Voltage characteristics showed close agreement with those of a conventional analyzer, and the coefficients of variation were less than 0.31 percent. Moreover, the influence of the micro-bump 3D interconnects was estimated and found to be negligible in this work. These results indicate the feasibility of the proposed 3D stacked array test circuit.	PDF Xplore
1.3	Influence of solder bumps-induced mechanical constraint on the performance of BJT ring oscillators M. Dahmani, S. Gallois-Garreignot, M. Dugor, B. Van-Haaren, L. Broussous, C. Boutonnat, F. Belfils, C. Cagli STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS69943.2026.11471722 ABSTRACT: We built four BJT-based ring oscillators (RO) in 55nm BiCMOS technology to study the impact of solder bumps deposition on the electrical performance of embedded devices (BJT and poly resistors). We observed that the PNP-based RO, embedded under solder bumps, displays an increase of frequency and power consumption in the order of 5%. We assumed this increase to the thermomechanical stress caused by the deposition thermal profile of the solder bump. To demonstrate it, we run thermomechanical simulations and showed that a resistor component in the RO is subject to enough compressive mechanical constraint that its resistance value could shift by a few % points affecting the RO oscillation frequency. The performance shift is anyway small to be of any concern for applications. Overall, our test structures prove to be very sensitive to mechanical stress and are excellent tools to evaluate the influence of solder bumps on technology performance.	PDF Xplore
1.4	Improving Robustness of Leakage-Based MOSFET Reservoir Computing Using Adaptive Pulse-Width Control R. Seki, M. Utsunomiya, Y. -G. Chen1, H. Awano, T. Sato Graduate School of Informatics, Kyoto University Yoshida-Hon-Machi, Sakyo, Kyoto, Japan 1Department of Electrical Engineering, National Central University, Taoyuan City, Taiwan DOI: 10.1109/ICMTS69943.2026.11471724 ABSTRACT: This paper proposes a method to enhance the robustness of Leakage-based MOSFET Echo State Network (LMESN) against environmental variations. LMESN is a hardware reservoir computing architecture that exploits MOSFET subthreshold leakage currents. The proposed method consists of two components: adaptive tuning of the minimum input pulse width based on temperature to compensate for leakage-current change, and the use of Lasso regression for output-weight training to suppress errors arising from temperature-coefficient variations. Simulation results on a time-series classification task confirm that the inference accuracy is maintained across temperatures ranging from 5 to 75ºC without requiring retraining over this temperature range.	PDF Xplore

Session 2: AI and Machine Learning

2.1	Machine Learning-Based Failure Mode Detection in 3D-DRAM Gate-All-Around Select Transistors J. Mitard, H. M. Kocak1, R. Ritzenthaler, P. Eyben, N. Rassoul2, E. Canga2, A. Belmonte Compute Technology Device Department, Imec, Leuven, Belgium 1Department of Computer Science, KU Leuven, Belgium 2Process Integration Department DOI: 10.1109/ICMTS69943.2026.11471719 ABSTRACT: We present a multi level CNN that classifies four terminal I-V curves of 3D DRAM GAA select transistors on 300 mm wafers with >95% accuracy, resolving up to 14 failure modes, including all currents to the substrate, revealing process dependent patterns and unknown defect clusters to accelerate process maturity of future high density 3D DRAM memory.	PDF Xplore
2.2	Speeding Up Capacitance-Voltage Measurements Using Gaussian Processes and Active Learning H. M. Kocak, H. Arimura1, J. Mitard1, J. Davis Department of Computer Science, KU Leuven, Belgium 1Compute Technology Device Department, IMEC, Belgium DOI: 10.1109/ICMTS69943.2026.11471661 ABSTRACT: Capacitance-Voltage (C-V) measurement is an important but slow device testing technique. We introduce an active learning methodology to reduce the required number of measurement needed by using Gaussian Process Regression to predict unmeasured values. The proposed method results in a 4x reduction in the number of needed measurements while generating almost perfectly identical curves with a 0.24% capacitance equivalent thickness error, and 0.9977 R2 score.	PDF Xplore
2.3	Accelerating Load-Pull Measurements Using Attentive Neural Processes J. -Y. Hsu, Y. -T. Chen, B. -Y. Chen, C. -W. Lin, C. -W. Chuang, C. -J. Lin, M. -H. Kao, L. -H. Hsu, W. -H. Huang, K. -M. Chen, G. -W. Huang National Institutes of Applied Research, Taiwan Semiconductor Research Institute, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS69943.2026.11471716 ABSTRACT: We propose Attentive Neural Processes (A-NPs) to accelerate load-pull measurements. Extrapolating the optimal reflection coefficient across various bias conditions is challenging due to the requirement for accurate output power measurements and time-consuming of testing. By leveraging the cross-attention in neural networks, optimal reflection coefficient can be accurately predicted using only a few measured points. This approach can reduce measurement time by approximately 65.7% per bias condition, and enabling effective integration into high-frequency load-pull measurement system.	PDF Xplore
2.4	VQ-VAE-Based Test Structure Selection for Constructing Design-Fabrication Surrogate Models R. Shimamura, S. Yasunaga, T. Nakamura, C. Wang1, M. Kraft1, Y. Mita Department of Electrical Engineering and Information Systems (EEIS), The University of Tokyo, Tokyo, Japan 1Department of Electrical Engineering, KU Leuven, Leuven, Belgium DOI: 10.1109/ICMTS69943.2026.11471659 ABSTRACT: In view of training fabrication surrogate models based on machine learning, we propose a semi-automated representative pattern selection pipeline to mitigate sampling bias caused by ad hoc manual selection. From an arbitrary design, a set of layout patterns is selected as a representative dataset of the design through dimensionality reduction using self-supervised representation learning with Vector Quantization-Variational Autoencoder and clustering with k-center algorithm. A modified U-Net based surrogate model for lithography and deep reactive ion etching trained using a dataset generated with the suggested pipeline was able to predict fabrication deviations with higher accuracy compared to models trained with datasets from other semi-automated sampling methods (7.2-percentage-point improvement in boundary IoU), supporting the validity of this method.	PDF Xplore

Session 3: Device Characterization

3.1	On-Wafer Golden Device and Layout Structures for Long-term Prober Chuck Temperature Verification and Monitoring W. Li, K. Xia1, L. Chao, S. Zhang Front End Innovation, NXP Semiconductors 1Power Management Business Development, TSMC DOI: 10.1109/ICMTS69943.2026.11471711 ABSTRACT: We report the temperature-sensing performance of seven types of on-wafer devices used for verifying prober chuck temperature after calibration, as well as for assessing chuck temperature stability and repeatability. Different types of devices show drastically different stability after twenty full temperature cycles. With optimized biasing, NMOS and its source-drain junctions are the best devices and can achieve less than 1.1ºC instability for the temperature range of -40ºC to 225ºC. We propose binary tree test structures for bench test and 1xN pad frame for probe-card based auto test to overcome the pad wear-out. The proposed method enables easy implementation and excellent stability for long-term monitoring of prober chuck temperature control, ensuring reliable silicon data collection.	PDF Xplore
3.2	Monte Carlo Simulation Method for Distance-Dependent Mismatch and Comparison of Common-Centroid and Dispersion Layouts K. Xia TSMC, Hsinchu, Taiwan DOI: 10.1109/ICMTS69943.2026.11471654 ABSTRACT: We present a Monte Carlo simulation method to model distance-dependent mismatch through randomly distributed long-range imperfections, with explicit inclusion of device-size dependence. The simulation results agree well with the theoretical approximations. We compare mismatch in layouts that use either common-centroid or maximal dispersion structures. At large correlation lengths, common-centroid layouts yield the lowest mismatch, while at short correlation lengths, dispersion plays a more dominant role than common-centroid in reducing mismatch.	PDF Xplore
3.3	Optimum Setting of 1/f Noise System towards Ultra-Low Noise Floor and Best Practice in Multi-Finger MOSFET Noise Characterization L. Chao, S. Zhang, J. Van Beurden, A. J. Scholten, W. Li NXP Semiconductors, Front End Innovation DOI: 10.1109/ICMTS69943.2026.11471712 ABSTRACT: We report a step-by-step approach for on-wafer 1/f noise system optimum setting to identify and minimize the external signal impacts, to achieve the best noise floor when a system is installed at a new lab, or after a certain period of usage. We share our best practice to obtain reliable low-frequency noise spectra for MOSFETs with various gate finger numbers, which are strongly affected by parasitic resistance and thus need special attention. Our approach and results provide insights to ensure reliable 1/f noise data collection.	PDF Xplore
3.4	Evaluation of Dummy Biasing on Leakage and Noise Performance in 4-nm FinFET Process S. Noh, J. Choi, Y. Seon, S. Park, J. Song Samsung Electronics, Republic of Korea DOI: 10.1109/ICMTS69943.2026.11471703 ABSTRACT: In this paper, we propose a dummy biasing guideline to reduce off-state leakage in a 4-nm FinFET process. To evaluate effect of dummy biasing, we compare three dummy biasing schemes using silicon measurements: conventional rail biasing, floating the source and drain terminals, and floating the source, drain, and gate terminals. The results show that floating the source and drain terminals of dummy transistors effectively suppresses the parasitic subthreshold leakage path between active and dummy transistors. Off-state leakage is reduced by up to 62% while maintaining drive current and 1/f noise characteristics within measurement variation. However, floating the gate terminal of dummy transistor can induce an ill-defined gate potential, which can increase drive-current variation. This guideline is particularly useful for analog designs that use dummy transistors to compensate layout-dependent effects and provides an effective leakage power optimization strategy in advanced-node designs.	PDF Xplore

Session 4: Process Characterization

4.1	Defect profiling of Al2O3-passivated InGaP layers via planar test structures P. L. Torraca, P. Kirilenko, R. Bharti, M. Jain, S. Bonam, L. Ansari, F. Gity, K. Cherkaoui, A. Tonkikh1, D. Sizov1, P. Gore1, M. Grundmann1, P. K. Hurley Tyndall National Institute, University College Cork, Cork, Ireland 1Meta Platforms Technologies, LLC, Menlo Park, USA DOI: 10.1109/ICMTS69943.2026.11471662 ABSTRACT: The electrically active defects in Al2O3-passivated InGaP layers, representative of an AlInGaP red micro-light-emitting diodes (μ-LED) sidewall, are characterized by using planar metal/insulator/semiconductor (MIS) capacitors test structures. The use of a planar test structure avoids the complexity of the full μ-LED device analysis and enables the selective InGaP/Al2O3 system characterization. The electrically active defects of InGaP/Al2O3/Ni MIS test structures, subject to different surface treatments, are investigated by multifrequency capacitance-voltage (CV) and conductance-voltage (GV) curves analysis. Trap levels located in the InGaP and in the Al2O3 are detected and profiled. The effect of the surface treatment (either no treatment, wet etching, or dry etching) on the detected traps is reported.	PDF Xplore
4.2	Extraction of Shockley-Read-Hall lifetime at the InGaP/Al2O3 interface using transient capacitance relaxation P. Kirilenko, P. L. Torraca, R. Bharti, M. Jain, S. Bonam, L. Ansari, F. Gity, K. Cherkaoui, E. Pelucchi1, G. Juska1, A. Tonkikh, A. Arnlind, D. Sizov, P. Gore, M. Grundmann, P. K. Hurley MicroNano Systems Department, Tyndall National Institute, Cork, Ireland 1Photonics Department, Tyndall National Institute, Cork, Ireland DOI: 10.1109/ICMTS69943.2026.11471653 ABSTRACT: Shockley-Read-Hall (SRH) generation in a MOS capacitor is analyzed to extract the SRH lifetime near the InGaP/Al2O3 interface. The transient capacitance relaxation is dominated by electron-hole pair generation through InGaP mid-gap states within 10 nm from the InGaP/Al2O3 interface, confirmed using TCAD simulation. The method sensitivity to interface modification is demonstrated.	PDF Xplore
4.3	Accuracy Limits of TLM and CTLM Test Structures for Ultra-Low Contact Resistance Extraction in InGaAs/InP Technologies A. Lubben, Y. Wang, Y. Jiao, J. Klootwijk Eindhoven Hendrick Casimir Institute, Eindhoven University of Technology, Eindhoven, the Netherlands DOI: 10.1109/ICMTS69943.2026.11471713 ABSTRACT: This work investigates the accuracy of Transfer Length Method (TLM) and Circular Transfer Length Method (CTLM) test structures for extracting ultra-low contact resistivities on highly doped n-InGaAs. CTLM reliably reaches the 10-8 Ω ᐧ cm2 regime with high reproducibility, while TLM accuracy is limited by fabrication-dependent effects such as incomplete mesa isolation and current spreading. Structure-dependent deviations between TLM and CTLM are analyzed, and practical guidelines are provided for achieving reliable TLM performance at ultra-low contact resistivities.	PDF Xplore

Session 5: MEMS and Sensors

5.1	A Contact-Closing Test Structure for Electrical In-Chamber Release Endpoint Detection During Vapor HF Etching A. Yoshida, S. Yasunaga, R. Nakane, A. Higo, Y. Mita Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS69943.2026.11471720 ABSTRACT: An electrical gap-closing MEMS test structure was proposed and validated to detect an endpoint of movable structure release in single-lithography silicon-on-insulator (SOI) MEMS with vapor-phase hydrofluoric acid (vHF) etching performed in an opaque process chamber. A body with the same layout as the target structure, suspended by a spiral spring, was co-fabricated on the same chip, and designed to become movable upon release and contact an adjacent fixed electrode across a small gap to generate a distinct electrical signature. Al wire-bonded pads were routed to an external source-measure unit. A clear transition was observed, and release was confirmed by post-etch infrared microscopy, supporting contact closure as a practical indicator for laboratory prototyping.	PDF Xplore
5.2	Comparative Study of Transducer Materials for Sodium-Selective EGISFETs : Stability Improvement and Interference Rejection K. -C. Huang, Y. -Y. Chou, C. -T. Lin Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan DOI: 10.1109/ICMTS69943.2026.11471717 ABSTRACT: Real-time monitoring of trace alkali metal contamination in ultrapure water (UPW) is critical for yield management in advanced semiconductor manufacturing. This study presents a systematic optimization of transducer materials to develop a robust Extended-Gate Ion-Sensitive Field-Effect Transistor (EGISFET) for sodium sensing. We investigated the electrochemical characteristics of SiO2, Al2O3, and TiO2 sensing layers with varying thicknesses. While Al2O3 exhibited the highest intrinsic pH sensitivity, the 200-nm TiO2 film was identified as the optimal interface for process control applications due to its superior device-to-device uniformity and exceptional stability, characterized by the lowest baseline drift variance (σdrift = 0.09$ pNa). Functionalized with a sodiumselective membrane, the optimized TiO2-EGISFET achieved a Nernstian sensitivity of 53.81 mV/pNa. Crucially, mixed-ion interference tests demonstrated that the sensor maintains high selectivity against potassium ions (K+), effectively rejecting interference even in high-background environments. These results establish the proposed TiO2-based test structure as a viable and stable platform for inline contamination monitoring in semiconductor wet processes.	PDF Xplore
5.3	An Ultra-Thin Indium Oxide FET Test Structure for Sweat Ion Sensing J. -R. Wu, Y. -T. Chen1, C. -F. Chen Graduate School of Advanced Technology, National Taiwan University, Taipei, Taiwan 1Nano Electromechanical Systems Research Center, National Taiwan University, Taipei, Taiwan DOI: 10.1109/ICMTS69943.2026.11471655 ABSTRACT: This work presents a dual-mode (back-gate and liquid-gate) 4 nm ultra-thin indium oxide (In2O3) field-effect transistor (FET) test structure for sweat ion sensing. Under back-gate operation, the device shows proper transistor behavior with an on/off current ratio on the order of 105, confirming effective channel formation and gate control. In liquid-gate configuration using an Ag/AgCl reference electrode, the drain current exhibits a concentration-dependent response to Na+ (10-160 mM) with an average sensitivity of ~6.3 nA/mM, demonstrating ion-induced modulation of the ultra-thin In2O3 channel. These results establish the proposed structure as a test platform for evaluating ultra-thin oxide semiconductor channels toward wearable sweat ion sensing.	PDF Xplore

Session 6: Memory

6.1	Read Current in Ferroelectric Tunnel Junctions: Transient versus DC Contributions and Trap Related Effects F. Driussi, M. Segatto, M. Massarotto, L. Carpentieri1, S. Slesazeck1, D. Esseni DPIA, University of Udine, Udine, Italy 1NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS69943.2026.11471657 ABSTRACT: Ferroelectric Tunnel Junctions (FTJs) performance as memristive devices is typically represented by their Tunneling Electro-Resistance Ratio (TER), defined as the ratio between the DC current measured in the low resistance state (LRS) and in the high-resistance state (HRS) of the device. However, during characterization of the FTJ read current and hence of TER, the transient contributions to the current are often overlooked in the literature, possibly causing misleading interpretations of the experimental TER. Here we propose a new, comprehensive characterization of the readout currents of different FTJ stacks, also investigating on their transient components. We report a solid interpretation of the experiments based on the response of traps in the ferroelectric, also supported by physics-based simulations.	PDF Xplore
6.2	MRAM Wafer Level Adaptative Edge Testing for Efficient Yield and Reliability Control M. Liehr, S. Ogden, M. Raymond, K. Funk, H. Elemva, K. Lee, G. Feng, K. Beckmann, A. Chavent1, T. D. Ngoc1, D. Grout1, S. Lequeux1, S. Salimy1 NY Creates, Albany, NY, USA 1Mycronic Hprobe, France DOI: 10.1109/ICMTS69943.2026.11471726 ABSTRACT: Magnetoresistive Random Access Memory (MRAM) offers high-speed, non-volatile storage for advanced embedded and standalone applications, yet wafer-level characterization of switching and reliability remains challenging due to the magnetic nature of device operation. This work presents synchronized magnetic-electrical wafer-level testing using the Hprobe IBEX platform integrated with a Tokyo Electron Limited Precio XL 300 mm probe station. The system enables localized three-dimensional vector magnetic field control and sub-nanosecond pulsed electrical excitation, combined with an adaptive Test/Skip methodology to reduce device stress. Experiments on 300 mm wafers with 14 MTJ pillar (RR) and bottom electrode (V0) geometries quantify resistance screening, R-H loops, DC and pulsed I-V behavior, bit error rate (BER), and endurance across pulse widths from 20 to 200 ns. Statistical analysis across multiple dies demonstrates size dependent switching voltage, yield trends, and pulse-width dependent degradation, consistent with thermal activation models for spin-transfer torque switching. Time savings of up to 28.5% were observed in this paper where overall savings depended heavily on initial device yield time. These results highlight the importance of wafer-level magnetic probing for predictive reliability assessment and scalable high-volume MRAM test methodologies.	PDF Xplore
6.3	Comparison of Addressing Methods for Memory Array Characterization M. A. Castillo, V. Della Marca1, J. Postel-Pellerin1, O. Paulet, L. Welter, M. Vidal-Dho, B. Chatelier, B. Arrazat, M. Bocquet1 Department of Technology and Design Platforms, STMicroelectronics, France 1IM2NP, CNRS, UMR, Aix-Marseille University, Marseille, France DOI: 10.1109/ICMTS69943.2026.11471709 ABSTRACT: The development of Resistive Random-Access Memories (RRAM) technologies relies increasingly on statistical characterization of large memory arrays, due to significant device-to-device variability. However, the electrical addressing of individual cells often becomes a major bottleneck during testing, especially for sequentially decoded test vehicles. This work evaluates four practical methods for generating address signals using equipment commonly available in academic or industrial characterization laboratories. Their performance is compared in terms of switching speed, ease of integration with semiconductor parameter analyzers, implementation complexity, and long term reliability. Experimental results show that FPGA based solutions provide the fastest switching capabilities, closely followed by microcontrollers, while Digital I/O ports of semiconductor analyzers offer a good compromise between speed and usability. Switching matrices, although convenient, exhibit the slowest response and potential reliability concerns when used outside their intended purpose.	PDF Xplore
6.4	On-Chip Learning with EEPROM Based Synapses: Reliability and Performance Assessment T. Bergamaschi, B. Imbert, V. Della Marca, S. Perrin, A. Regnier1, M. Akbal1, C. Rivero1, L. Welter1, T. Kempf1, J. -D. Aguirre-Morales, J. -M. Portal, M. Bocquet CNRS, IM2NP, Aix-Marseille Univ, Université de Toulon, Marseille, France 1STMicroelectronics, France DOI: 10.1109/ICMTS69943.2026.11471706 ABSTRACT: Embedded EEPROM technologies are widely used in industrial microcontrollers and offer excellent reliability, but their potential for analog operation remains under-explored due to the limited observability of cell-level electrical behaviour in standard memory arrays. This work leverages the SuperCAST test structure, a fully addressable 4k-cell EEPROM array, to perform detailed analog characterization of floating-gate devices. The architecture provides individual access to each memory cell, enabling pulse-by-pulse programming analysis, variability extraction, endurance and retention evaluation, and precise readout characterization. These measurements allow assessing the suitability of EEPROM technology for analog synaptic operation in neuromorphic systems. Finally, the experimentally extracted characteristics are incorporated into neural-network simulations to illustrate how device-level non-idealities impact learning performance. The results demonstrate that SuperCAST is a powerful platform for evaluating embedded EEPROM as a candidate for reliable analog in-memory computing.	PDF Xplore

Session 7: Reliability

7.1	Characterization of Non-Conducting RF Hot-Carrier Stress Effects on Transistor Noise from 10 MHz to 26.5 GHz in 5-nm FinFETs G. Niu, X. Ding, E. Tao, H. Zhang1, W. Wang1, K. Imura1 Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, USA 1MaxLinear, Inc., Carlsbad, CA, USA DOI: 10.1109/ICMTS69943.2026.11471729 ABSTRACT: This work presents, for the first time, a systematic investigation of high-frequency flicker noise degradation from 10 MHz to 26.5 GHz in commercial foundry 5-nm FinFETs subjected to non-conducting RF hot-carrier stress. The experimental results demonstrate that, even under an aggressive non-conducting RF stress condition with a maximum drain voltage of Vd,max = 2Vdd, the induced noise degradation exhibits a sufficiently long lifetime. These findings confirm the robustness of 5-nm FinFET technologies for RF circuit applications requiring stringent phase-noise performance.	PDF Xplore
7.2	Impact of Fluorine Incorporation on Boron Diffusion and Reliability in Advanced High Voltage FinFETs J. -H. Lin, P. -H. Chen1, L. Tang2, M. -X. Feng3, T. -C. Chang4 Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan 1Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan 2Institute of Advanced Semiconductor Packaging and Testing, National Sun Yat-Sen University, Kaohsiung, Taiwan 3Department of Microelectronics Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan 4Department of Physics, College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS69943.2026.11471652 ABSTRACT: This work investigates the impact of fluorine incorporation in the lightly doped drain (LDD) region of high-voltage FinFETs, with particular emphasis on device reliability under hot-carrier stress conditions. The experiment results exhibit that the device with higher fluorine doped concentration (B/F+) shows a better hot-carrier reliability. This enhancement is primarily attributed to the formation of robust Si-F bonds at the Si/SiO2 interface, which effectively passivate interface traps and decrease defect generation induced by high electric fields. In addition, boron will diffuse to the interface and form boron interstitial and interface shallow defect states. However, fluorine incorporation is found to suppress boron diffusion in the LDD region. As a result, both device stability and long-term reliability are substantially improved.	PDF Xplore
7.3	Parasitic Characterization of Hot-Carrier-Induced Degradation using Experimental S-Parameters for RF-MOSFETs C. Tanaka, T. Suzuki, A. Sueoka, F. Fujii, K. Matsuzawa1 Memory Division, KIOXIA Corporation, Yokohama, Japan 1Core Technology Research Center, KIOXIA Corporation, Yokohama, Japan DOI: 10.1109/ICMTS69943.2026.11471704 ABSTRACT: This study provides an examination of the impact of hot-carriers induced degradation on the small-signal parameters of MOSFET. Specifically, it focuses on analyzing the source and drain resistances, as well as the gate resistance using experimental S-parameters before and after DC voltage stress. To get the trap distribution of aged MOSFET structure, 2D TCAD simulations were conducted. Observations indicate that the gate resistance of the parasitic components and the distribution of trapped charges within the device structure have changed due to hot-carrier stress, although there are no significant changes in the source and drain resistance with respect to the voltage stress. These results may inform design improvements for RF-MOSFETs through detailed modeling of AC parameters.	PDF Xplore
7.4	Reliability Comparison under Drain Bias Stress for N- and P-Type LTPS Thin-Film Transistors M. -X. Feng, P. -W. Chang, S. -P. Chang, J. -H. Lin1, T. -M. Tsai2 Microelectronics Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan 1Department of Physics, National Sun Yat-sen University, Kaohsiung City, Taiwan 2Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS69943.2026.11471728 ABSTRACT: In the early generations of low-temperature polycrystalline silicon (LTPS) backplanes, p-channel thin-film transistors (TFTs) were predominantly employed due to their lower dopant activation requirements and superior bias-stress stability. With dimension scaling and rising current demand in micro-LED backplanes, n-type LTPS TFTs have become attractive owing to their higher carrier mobility and stronger drive capability.However, when p-type devices are directly replaced with n-type devices, we observe pronounced degradation under off-state drain bias stress (OSS), including severe on-current loss and increased leakage. The degradation mechanism is systematically investigated and confirmed by C-V measurements, transfer characteristics in the saturation region, and SILVACO TCAD simulations. Hot-carrier stress (HCS) reliability is also examined and shown to suffer from similar field-induced damage	PDF Xplore

Session 8: ESD

8.1	Test Structures to Study Interconnection Metal/Via/Contact Reliability under Transient Pulse Stresses of ESD and Surge Events P. -Y. Hsiao, C. -T. Dai1, T. -Y. Chen1, M. -D. Ker Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan 1AIP Technology Corporation DOI: 10.1109/ICMTS69943.2026.11471715 ABSTRACT: In this study, a Transmission Line Pulse (TLP) system and a Surge tester are applied to investigate damage mechanisms of metal/via/contact interconnects in a 0.18-μm CMOS technology. Results indicate that the transient thermal response of these interconnects strongly depends on pulse duration. Failure analysis reveals distinct mechanisms depending on whether damage is caused by short or long pulses. The pulse-dependent damage behavior is crucial for reliable IC design, especially in the advanced CMOS technologies.	PDF Xplore
8.2	The Influence of Skin Effect on Metal Lines in ESD Protection Circuit C. -H. Chiang, C. -Y. Lin Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS69943.2026.11471723 ABSTRACT: The purpose of this paper is to investigate how the skin effect degrades the electrostatic discharge (ESD) robustness of metal interconnects. Metal lines with various widths and lengths were evaluated using an ESD tester. Based on the experimental results and the underlying skin-effect theory, a method for predicting the ESD tolerance of metal lines is proposed. The estimated ESD robustness of some test keys shows good agreement with the measured data. However, the skin effect alone cannot explain the observed trend that longer metal lines exhibit lower ESD robustness.	PDF Xplore
8.3	Investigation on ESD Robustness of SiC Devices by Transmission Line Pulse Measurement for Monolithic Integration Applications H. -Y. Huang, Y. -Z. Hu1, M. -D. Ker1 Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University, Hsinchu, Taiwan 1Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS69943.2026.11471718 ABSTRACT: Electrostatic discharge (ESD) robustness of silicon carbide (SiC) devices using transmission line pulsing (TLP) measurements is studied in this work. The devices under examination include the gate-connected-to-ground NMOS (GGNMOS), the gate-connected-to-VDD PMOS (GDPMOS), N+/PW diode, and P+/NW diode. ESD robustness of the SiC-based diodes and GDPMOS can be enhanced by increasing their device sizes under both breakdown and forward modes. In contrast, ESD robustness of SiC-based GGNMOS can be improved only by increasing total width under the forward mode. Additionally, ESD robustness of the diodes is greater than those of the GGNMOS and GDPMOS. An ESD protection scheme is proposed that utilizes N+/PW and P+/NW diodes under forward mode to enhance protection for positive-to-VDD (PD) and negative-to-VSS (NS) stress modes. Additionally, a power-rail ESD clamp circuit is integrated to further strengthen protection for positive-to-VSS (PS) and negative-to-VDD (ND) stress modes. This approach provides comprehensive ESD protection for the SiC-based monolithic integration circuits.	PDF Xplore

Session 9: Cryogenics

9.1	Impact of Contacts and Heatsinks on Heat Accumulation in Cryogenic SOI MOSFETs K. Hatta, T. Mori, S. Kondo, H. Oka1, T. Mori1, J. Ida Kanazawa Institute of Technology, Ishikawa, Japan 1National Institute of Advanced Industrial Science and Technology, Ibaraki, Japan DOI: 10.1109/ICMTS69943.2026.11471735 ABSTRACT: Addressing heat reduction problems of SOI MOSFETs is important for Cryo-CMOS technology. In this paper, heat dissipation in SOI MOSFETs via the source/drain contacts and the heatsinks on the active silicon layer at cryogenic temperatures was investigated. Measurements and simulations revealed that source/drain contacts contribute to reducing the channel temperature, whereas the heatsinks showed minimal effects. Moreover, these effects at cryogenic temperatures were shown to be more pronounced than at room temperature. These findings highlight that modeling and optimizing heat dissipation pathways proximal to the heat source are critical at cryogenic temperatures.	PDF Xplore
9.2	Maintaining Constant Vth from 1.7 K to 390 K Using Adaptive Back-Gate Bias in 22 nm FDX Technology E. Tao, G. Niu, A. Zhang, Y. Wang, Y. Fan, F. Dai Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, USA DOI: 10.1109/ICMTS69943.2026.11471721 ABSTRACT: This work demonstrates, for the first time, the maintenance of a constant threshold voltage (Vth) over an ultra-wide temperature range from 1.7 K to 390 K using adaptive back-gate biasing in a 22 nm FDSOI technology. Strong correlation is shown between Vth extracted from measured Id- Vgs characteristics and circuit-level extracted Vth across the full temperature range. In addition, the closed-loop Vth regulation performance is experimentally validated.	PDF Xplore
9.3	Characteristics of P-Type Polysilicon Resistors from Cryogenic to High Temperatures and Modeling Y. Wang, K. Xia1, G. Niu, J. Xia2, M. Hamilton Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, USA 1TSMC, Hsinchu, Taiwan, R.O.C. 2BASIS, Chandler, AZ, USA DOI: 10.1109/ICMTS69943.2026.11471714 ABSTRACT: This paper presents cryogenic-to-high-temperature characterization and compact modeling of p-type polysilicon resistors from 18.6 K to 473.15 K. Three resistor families (RPH, RP, and RPL) are characterized using four-terminal Kelvin structures across multiple geometries. RPH exhibits a strong, monotonic negative temperature coefficient of resistance (TCR) over the entire temperature range, whereas RP and RPL show geometry-dependent TCR sign changes and low-temperature saturation; several layouts achieve near-zero TCR over a wide temperature span. To capture these behaviors, a Matthiessen'-rule-based double power law (DPL) temperature model is proposed, combining scattering contributions associated with grain boundaries and bulk/impurity effects. Compared with the conventional TC1/TC2 polynomial model, the proposed DPL model provides improved accuracy over the full temperature range and yields parameters that cluster by doping level and vary smoothly with geometry.	PDF Xplore

Session 10: Power Devices

10.1	Investigation of Crystal-Face-Resolved Gate Switching Instability in 4H-SiC UMOSFETs Enabled by a Source-Separated Single-Cell Structure W. -J. Liao, C. -L. Hong1, Y. -K. Hsiao1, B. -Y. Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C. 1Semiconductor Research Center, Hon Hai Research Institute, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS69943.2026.11471725 ABSTRACT: In this work, we demonstrate the crystal-face-resolved gate switching instability in 4H-SiC UMOSFET. By employing a source-separated single-cell (SSSC) structure, we are able to characterize GSI of each crystal face and revealing reliability discrepancies arising from variations in crystal orientation, interface quality, and process-induced sidewall asymmetry.	PDF Xplore
10.2	Evaluation of Rise-Time Effects on AC-TDDB Characteristics in SiC MOSFETs Using an In-Situ Gate Leakage Measurement Technique S. Nakata, T. Sato Dept. of Electrical Energy Systems Engineering, Kanazawa Institute of Technology, Nonoichi, Japan DOI: 10.1109/ICMTS69943.2026.11471710 ABSTRACT: Reliability evaluation of SiC MOSFETs under realistic switching operation requires accurate characterization of gate oxide degradation during AC time-dependent dielectric breakdown (AC-TDDB) stress. However, under high-frequency rectangular pulse operation with short rise and fall times, large displacement currents originating from the input capacitance obscure the leakage current component, making in-situ monitoring difficult. In this work, a numerical waveform processing technique is developed to compensate for the displacement current by modeling its gate-voltage dependence and subtracting it from the measured current in real time. The proposed method enables accurate in-situ extraction of gate leakage current during AC-TDDB testing at 1 MHz with rise times ranging from 7 to 90 ns. Using commercially available SiC MOSFETs from two manufacturers, AC-TDDB behavior is systematically compared with DC-TDDB results, and the dependence on rise time is investigated. The results show that current decay under AC stress is more gradual than under DC stress, indicating longer lifetime under pulsed operation. Furthermore, shortening the rise time significantly accelerates the decay rate of the gate leakage current in both devices. Quantitative analysis based on the time interval between 90% and 75% of the peak current reveals that the rise-time dependence becomes more pronounced at lower gate voltage. These findings suggest that high-speed switching intended to reduce switching losses may enhance defect generation in the gate oxide. The proposed measurement technique provides a practical framework for dynamic reliability evaluation of SiC MOSFET gate oxides under realistic operating conditions.	PDF Xplore
10.3	Application of a Three-Terminal TCAD Model for Designing Shielded Field-Limiting Ring Edge Termination K. Takeuchi, M. Fukui, T. Saraya, K. Itou, T. Takakura, S. Suzuki, H. Takase, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS69943.2026.11471727 ABSTRACT: Field-limiting ring (FLR) edge termination is widely used in Si and SiC vertical power devices to sustain high lateral off-state voltage and thereby realize strong blocking capability. However, conventional FLR structures are susceptible to fixed oxide charge, which compromises the robustness and reproducibility of termination performance. In this work, we propose a new FLR structure designed to mitigate this charge sensitivity. To efficiently explore the design space, we employ a simplified TCAD model that captures the electrostatic behavior of a representative stripe section of the FLR region.	PDF Xplore
10.4	Optimizing LDMOS Device Performance and Reliability Through Drift-Region Engineering P. -W. Chang, J. -H. Lin1, M. -X. Feng, S. -P. Chang, P. -H. Chen2 Department of Microelectronics Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan 1Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan 2Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS69943.2026.11471707 ABSTRACT: This study investigates the impact of drift-region engineering, including junction depth and doping concentration, on the electrical performance and reliability of LDMOS devices in BCD technology. Experimental results and TCAD simulations show that while deeper drift regions generally enhance performance, the resulting peak electric field can cause strong impact ionization that damages the device. However, by balancing the electric field between the gate and drain edges, the impact ionization becomes balanced between these two sides, effectively suppressing degradation. These findings provide essential guidelines for optimizing performance and reliability in high-voltage automotive and industrial applications.	PDF Xplore

Papers By First Author

6.4	On-Chip Learning with EEPROM Based Synapses: Reliability and Performance Assessment T. Bergamaschi, B. Imbert, V. Della Marca, S. Perrin, A. Regnier1, M. Akbal1, C. Rivero1, L. Welter1, T. Kempf1, J. -D. Aguirre-Morales, J. -M. Portal, M. Bocquet CNRS, IM2NP, Aix-Marseille Univ, Université de Toulon, Marseille, France 1STMicroelectronics, France DOI: 10.1109/ICMTS69943.2026.11471706 HOVER FOR ABSTRACT	PDF Xplore
1.1	Ultra-low leakage power switch for RO array characterization in 18nm FD-SOI technology platform validation C. Cagli, H. Degoirat, M. Lamy, F. Pourchon, J. B. Moulard, F. Granoux, M. Dahmani, R. Wilson STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS69943.2026.11471708 HOVER FOR ABSTRACT	PDF Xplore
6.3	Comparison of Addressing Methods for Memory Array Characterization M. A. Castillo, V. Della Marca1, J. Postel-Pellerin1, O. Paulet, L. Welter, M. Vidal-Dho, B. Chatelier, B. Arrazat, M. Bocquet1 Department of Technology and Design Platforms, STMicroelectronics, France 1IM2NP, CNRS, UMR, Aix-Marseille University, Marseille, France DOI: 10.1109/ICMTS69943.2026.11471709 HOVER FOR ABSTRACT	PDF Xplore
10.4	Optimizing LDMOS Device Performance and Reliability Through Drift-Region Engineering P. -W. Chang, J. -H. Lin1, M. -X. Feng, S. -P. Chang, P. -H. Chen2 Department of Microelectronics Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan 1Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan 2Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS69943.2026.11471707 HOVER FOR ABSTRACT	PDF Xplore
3.3	Optimum Setting of 1/f Noise System towards Ultra-Low Noise Floor and Best Practice in Multi-Finger MOSFET Noise Characterization L. Chao, S. Zhang, J. Van Beurden, A. J. Scholten, W. Li NXP Semiconductors, Front End Innovation DOI: 10.1109/ICMTS69943.2026.11471712 HOVER FOR ABSTRACT	PDF Xplore
8.2	The Influence of Skin Effect on Metal Lines in ESD Protection Circuit C. -H. Chiang, C. -Y. Lin Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS69943.2026.11471723 HOVER FOR ABSTRACT	PDF Xplore
1.3	Influence of solder bumps-induced mechanical constraint on the performance of BJT ring oscillators M. Dahmani, S. Gallois-Garreignot, M. Dugor, B. Van-Haaren, L. Broussous, C. Boutonnat, F. Belfils, C. Cagli STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS69943.2026.11471722 HOVER FOR ABSTRACT	PDF Xplore
6.1	Read Current in Ferroelectric Tunnel Junctions: Transient versus DC Contributions and Trap Related Effects F. Driussi, M. Segatto, M. Massarotto, L. Carpentieri1, S. Slesazeck1, D. Esseni DPIA, University of Udine, Udine, Italy 1NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS69943.2026.11471657 HOVER FOR ABSTRACT	PDF Xplore
7.4	Reliability Comparison under Drain Bias Stress for N- and P-Type LTPS Thin-Film Transistors M. -X. Feng, P. -W. Chang, S. -P. Chang, J. -H. Lin1, T. -M. Tsai2 Microelectronics Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan 1Department of Physics, National Sun Yat-sen University, Kaohsiung City, Taiwan 2Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS69943.2026.11471728 HOVER FOR ABSTRACT	PDF Xplore
9.1	Impact of Contacts and Heatsinks on Heat Accumulation in Cryogenic SOI MOSFETs K. Hatta, T. Mori, S. Kondo, H. Oka1, T. Mori1, J. Ida Kanazawa Institute of Technology, Ishikawa, Japan 1National Institute of Advanced Industrial Science and Technology, Ibaraki, Japan DOI: 10.1109/ICMTS69943.2026.11471735 HOVER FOR ABSTRACT	PDF Xplore
8.1	Test Structures to Study Interconnection Metal/Via/Contact Reliability under Transient Pulse Stresses of ESD and Surge Events P. -Y. Hsiao, C. -T. Dai1, T. -Y. Chen1, M. -D. Ker Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan 1AIP Technology Corporation DOI: 10.1109/ICMTS69943.2026.11471715 HOVER FOR ABSTRACT	PDF Xplore
2.3	Accelerating Load-Pull Measurements Using Attentive Neural Processes J. -Y. Hsu, Y. -T. Chen, B. -Y. Chen, C. -W. Lin, C. -W. Chuang, C. -J. Lin, M. -H. Kao, L. -H. Hsu, W. -H. Huang, K. -M. Chen, G. -W. Huang National Institutes of Applied Research, Taiwan Semiconductor Research Institute, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS69943.2026.11471716 HOVER FOR ABSTRACT	PDF Xplore
5.2	Comparative Study of Transducer Materials for Sodium-Selective EGISFETs : Stability Improvement and Interference Rejection K. -C. Huang, Y. -Y. Chou, C. -T. Lin Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan DOI: 10.1109/ICMTS69943.2026.11471717 HOVER FOR ABSTRACT	PDF Xplore
8.3	Investigation on ESD Robustness of SiC Devices by Transmission Line Pulse Measurement for Monolithic Integration Applications H. -Y. Huang, Y. -Z. Hu1, M. -D. Ker1 Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University, Hsinchu, Taiwan 1Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS69943.2026.11471718 HOVER FOR ABSTRACT	PDF Xplore
4.2	Extraction of Shockley-Read-Hall lifetime at the InGaP/Al2O3 interface using transient capacitance relaxation P. Kirilenko, P. L. Torraca, R. Bharti, M. Jain, S. Bonam, L. Ansari, F. Gity, K. Cherkaoui, E. Pelucchi1, G. Juska1, A. Tonkikh, A. Arnlind, D. Sizov, P. Gore, M. Grundmann, P. K. Hurley MicroNano Systems Department, Tyndall National Institute, Cork, Ireland 1Photonics Department, Tyndall National Institute, Cork, Ireland DOI: 10.1109/ICMTS69943.2026.11471653 HOVER FOR ABSTRACT	PDF Xplore
2.2	Speeding Up Capacitance-Voltage Measurements Using Gaussian Processes and Active Learning H. M. Kocak, H. Arimura1, J. Mitard1, J. Davis Department of Computer Science, KU Leuven, Belgium 1Compute Technology Device Department, IMEC, Belgium DOI: 10.1109/ICMTS69943.2026.11471661 HOVER FOR ABSTRACT	PDF Xplore
3.1	On-Wafer Golden Device and Layout Structures for Long-term Prober Chuck Temperature Verification and Monitoring W. Li, K. Xia1, L. Chao, S. Zhang Front End Innovation, NXP Semiconductors 1Power Management Business Development, TSMC DOI: 10.1109/ICMTS69943.2026.11471711 HOVER FOR ABSTRACT	PDF Xplore
10.1	Investigation of Crystal-Face-Resolved Gate Switching Instability in 4H-SiC UMOSFETs Enabled by a Source-Separated Single-Cell Structure W. -J. Liao, C. -L. Hong1, Y. -K. Hsiao1, B. -Y. Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C. 1Semiconductor Research Center, Hon Hai Research Institute, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS69943.2026.11471725 HOVER FOR ABSTRACT	PDF Xplore
6.2	MRAM Wafer Level Adaptative Edge Testing for Efficient Yield and Reliability Control M. Liehr, S. Ogden, M. Raymond, K. Funk, H. Elemva, K. Lee, G. Feng, K. Beckmann, A. Chavent1, T. D. Ngoc1, D. Grout1, S. Lequeux1, S. Salimy1 NY Creates, Albany, NY, USA 1Mycronic Hprobe, France DOI: 10.1109/ICMTS69943.2026.11471726 HOVER FOR ABSTRACT	PDF Xplore
7.2	Impact of Fluorine Incorporation on Boron Diffusion and Reliability in Advanced High Voltage FinFETs J. -H. Lin, P. -H. Chen1, L. Tang2, M. -X. Feng3, T. -C. Chang4 Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan 1Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan 2Institute of Advanced Semiconductor Packaging and Testing, National Sun Yat-Sen University, Kaohsiung, Taiwan 3Department of Microelectronics Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan 4Department of Physics, College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS69943.2026.11471652 HOVER FOR ABSTRACT	PDF Xplore
4.3	Accuracy Limits of TLM and CTLM Test Structures for Ultra-Low Contact Resistance Extraction in InGaAs/InP Technologies A. Lubben, Y. Wang, Y. Jiao, J. Klootwijk Eindhoven Hendrick Casimir Institute, Eindhoven University of Technology, Eindhoven, the Netherlands DOI: 10.1109/ICMTS69943.2026.11471713 HOVER FOR ABSTRACT	PDF Xplore
2.1	Machine Learning-Based Failure Mode Detection in 3D-DRAM Gate-All-Around Select Transistors J. Mitard, H. M. Kocak1, R. Ritzenthaler, P. Eyben, N. Rassoul2, E. Canga2, A. Belmonte Compute Technology Device Department, Imec, Leuven, Belgium 1Department of Computer Science, KU Leuven, Belgium 2Process Integration Department DOI: 10.1109/ICMTS69943.2026.11471719 HOVER FOR ABSTRACT	PDF Xplore
10.2	Evaluation of Rise-Time Effects on AC-TDDB Characteristics in SiC MOSFETs Using an In-Situ Gate Leakage Measurement Technique S. Nakata, T. Sato Dept. of Electrical Energy Systems Engineering, Kanazawa Institute of Technology, Nonoichi, Japan DOI: 10.1109/ICMTS69943.2026.11471710 HOVER FOR ABSTRACT	PDF Xplore
1.2	Statistical Capacitance Measurement of Si Trench Capacitors Using 3D Stacked Array Test Circuit R. Nishimaki, K. Saito, T. Mawaki, R. Kuroda Graduate School of Engineering, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS69943.2026.11471660 HOVER FOR ABSTRACT	PDF Xplore
7.1	Characterization of Non-Conducting RF Hot-Carrier Stress Effects on Transistor Noise from 10 MHz to 26.5 GHz in 5-nm FinFETs G. Niu, X. Ding, E. Tao, H. Zhang1, W. Wang1, K. Imura1 Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, USA 1MaxLinear, Inc., Carlsbad, CA, USA DOI: 10.1109/ICMTS69943.2026.11471729 HOVER FOR ABSTRACT	PDF Xplore
3.4	Evaluation of Dummy Biasing on Leakage and Noise Performance in 4-nm FinFET Process S. Noh, J. Choi, Y. Seon, S. Park, J. Song Samsung Electronics, Republic of Korea DOI: 10.1109/ICMTS69943.2026.11471703 HOVER FOR ABSTRACT	PDF Xplore
1.4	Improving Robustness of Leakage-Based MOSFET Reservoir Computing Using Adaptive Pulse-Width Control R. Seki, M. Utsunomiya, Y. -G. Chen1, H. Awano, T. Sato Graduate School of Informatics, Kyoto University Yoshida-Hon-Machi, Sakyo, Kyoto, Japan 1Department of Electrical Engineering, National Central University, Taoyuan City, Taiwan DOI: 10.1109/ICMTS69943.2026.11471724 HOVER FOR ABSTRACT	PDF Xplore
2.4	VQ-VAE-Based Test Structure Selection for Constructing Design-Fabrication Surrogate Models R. Shimamura, S. Yasunaga, T. Nakamura, C. Wang1, M. Kraft1, Y. Mita Department of Electrical Engineering and Information Systems (EEIS), The University of Tokyo, Tokyo, Japan 1Department of Electrical Engineering, KU Leuven, Leuven, Belgium DOI: 10.1109/ICMTS69943.2026.11471659 HOVER FOR ABSTRACT	PDF Xplore
10.3	Application of a Three-Terminal TCAD Model for Designing Shielded Field-Limiting Ring Edge Termination K. Takeuchi, M. Fukui, T. Saraya, K. Itou, T. Takakura, S. Suzuki, H. Takase, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS69943.2026.11471727 HOVER FOR ABSTRACT	PDF Xplore
7.3	Parasitic Characterization of Hot-Carrier-Induced Degradation using Experimental S-Parameters for RF-MOSFETs C. Tanaka, T. Suzuki, A. Sueoka, F. Fujii, K. Matsuzawa1 Memory Division, KIOXIA Corporation, Yokohama, Japan 1Core Technology Research Center, KIOXIA Corporation, Yokohama, Japan DOI: 10.1109/ICMTS69943.2026.11471704 HOVER FOR ABSTRACT	PDF Xplore
9.2	Maintaining Constant Vth from 1.7 K to 390 K Using Adaptive Back-Gate Bias in 22 nm FDX Technology E. Tao, G. Niu, A. Zhang, Y. Wang, Y. Fan, F. Dai Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, USA DOI: 10.1109/ICMTS69943.2026.11471721 HOVER FOR ABSTRACT	PDF Xplore
4.1	Defect profiling of Al2O3-passivated InGaP layers via planar test structures P. L. Torraca, P. Kirilenko, R. Bharti, M. Jain, S. Bonam, L. Ansari, F. Gity, K. Cherkaoui, A. Tonkikh1, D. Sizov1, P. Gore1, M. Grundmann1, P. K. Hurley Tyndall National Institute, University College Cork, Cork, Ireland 1Meta Platforms Technologies, LLC, Menlo Park, USA DOI: 10.1109/ICMTS69943.2026.11471662 HOVER FOR ABSTRACT	PDF Xplore
9.3	Characteristics of P-Type Polysilicon Resistors from Cryogenic to High Temperatures and Modeling Y. Wang, K. Xia1, G. Niu, J. Xia2, M. Hamilton Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, USA 1TSMC, Hsinchu, Taiwan, R.O.C. 2BASIS, Chandler, AZ, USA DOI: 10.1109/ICMTS69943.2026.11471714 HOVER FOR ABSTRACT	PDF Xplore
5.3	An Ultra-Thin Indium Oxide FET Test Structure for Sweat Ion Sensing J. -R. Wu, Y. -T. Chen1, C. -F. Chen Graduate School of Advanced Technology, National Taiwan University, Taipei, Taiwan 1Nano Electromechanical Systems Research Center, National Taiwan University, Taipei, Taiwan DOI: 10.1109/ICMTS69943.2026.11471655 HOVER FOR ABSTRACT	PDF Xplore
3.2	Monte Carlo Simulation Method for Distance-Dependent Mismatch and Comparison of Common-Centroid and Dispersion Layouts K. Xia TSMC, Hsinchu, Taiwan DOI: 10.1109/ICMTS69943.2026.11471654 HOVER FOR ABSTRACT	PDF Xplore
5.1	A Contact-Closing Test Structure for Electrical In-Chamber Release Endpoint Detection During Vapor HF Etching A. Yoshida, S. Yasunaga, R. Nakane, A. Higo, Y. Mita Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS69943.2026.11471720 HOVER FOR ABSTRACT	PDF Xplore