ICMTS 2025 Program

Mar 24-27, 2025 in San Antonio, TX, USA

Papers By Session

Session 1: Applications

1.1	Power switch improvement for RO array characterization in 18nm FD-SOI technology platform validation C. Cagli, F. Pourchon, H. Degoirat, J. B. Moulard, F. Granoux, M. Dahmani, R. Wilson STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS63811.2025.11068914 ABSTRACT: We compare two power switches architectures implemented within test chips (18nm FD-SOI) that provide DUT selection in ring oscillators (RO) array, used for technology platform characterization. We first show the performance of a classic switch made of two pmos. Next, we illustrate that this design is largely improved by adding a third pmos and a nmos. We provide extensive data to show that the newer design has a much lower parasitic leakage, improves precision and enlarges temperature-voltage range.	PDF Xplore
1.2	Comparative Study of Switching Dynamics in Ferroelectric-based Capacitors with Different Design Options F. Driussi, E. Rocco, M. Massarotto, S. Lancaster1, S. Slesazeck1, T. Mikolajick1, D. Esseni DPIA, University of Udine, Udine, Italy 1NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS63811.2025.11068911 ABSTRACT: Switching dynamics of ferroelectric (FE) based devices not only depend on the FE material but also on the design options available for the materials stack. However, the impact of the design of the material layers on the FE device properties is not fully understood yet. Here, we report a comprehensive characterization of Ferroelectric Tunnel Junctions based on Metal-Ferroelectric-Dielectric-Metal (MFDM) stacks and a full benchmark of the extracted parameters with those of Metal-Ferroelectric-Metal (MFM) capacitors. MFDM devices show an evident dependence of the extracted coercive voltages on the thickness of the dielectric layer (DE), as well as on the frequency of the signal used to characterize the device, which is not observed in MFM stacks. Finally, the remnant polarization measured in MFDM stacks is lower than in MFM samples. Together, all these evidences suggest that the traps at the FE-DE interface play a fundamental role in the switching dynamics of the device and in the extraction of the ferroelectric parameters.	PDF Xplore
1.3	Enhancement of Synaptic Properties using Ta2O5/ZnO/Ta2O5 Tri-layer Device C. -M. Yeom, S. -H. Kim, Y. -B. Kim, D. -M. Kim, K. -S. Roh1, Y. -S. Kim1, Y. -G. Kim2, H. -M. Kwon3, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejeon, Korea 1LAB of Nano Process Technology, National Nanofab Center, Daejeon, Korea 2Department of Green Semiconductor System, Korea Polytechnic, Daegu, Korea 3School of Electronic & Electrical Engineering, Hankyong National University, Anseong, Korea DOI: 10.1109/ICMTS63811.2025.11068932 ABSTRACT: This paper investigated the electrical characteristics of Ta2O5-based synaptic devices by designing and fabricating a device incorporating a ZnO layer, based on critical parameters for learning in neural network-based algorithms. A comparative analysis was conducted between synaptic devices based on a single and double layer. The results show that inserting ZnO into the Ta2O5-based synaptic device decreases the SET/RESET voltages. Furthermore, the triple-layer in synaptic devices improved yield, switching behavior uniformity, and conductance change uniformity in response to pulse inputs. These findings suggested that the triple-layer structure provided advantages in consistently forming oxygen vacancy-based conductive filaments (CFs) and allowed for better-controlled migration of oxygen ions from a structural perspective.	PDF Xplore

Session 2: Reliability

2.1	The Hot Carrier Injection Induced Degradation in MOS Transistors with Subthreshold Hump and the Corelated Impacts on Low Frequency Noise for Low Power Analog Designs W. Li, K. Xia1, R. Xu, L. Chao NXP Semiconductors, Front End Innovation 1TSMC, Power Management Business Development DOI: 10.1109/ICMTS63811.2025.11068917 ABSTRACT: This paper presents a comparative study of the impact of hot carrier injection (HCI) on the degradation of the electrical performance in low-voltage MOS transistors with a subthreshold hump. DC performance was measured at the device level before and after HCI stress, along with different baking durations to understand the degradation trends of the parasitic edge-MOS device versus the intrinsic-MOS device. Additionally, 1/f noise was measured to investigate the underlying mechanisms. Our findings confirm that the edge-MOS degrades more rapidly than the intrinsic-MOS, offering insights for low-power analog designs.	PDF Xplore
2.2	On-Wafer Characterization of HCI/BTI-induced Threshold Voltage Degradation based Measured Frequency Shift of Ring-Oscillator Circuits C. Tanaka, N. Momo, F. Fujii, O. Kobayashi Memory Division, Kioxia Corporation, Sakae-ku, Yokohama, Japan DOI: 10.1109/ICMTS63811.2025.11068922 ABSTRACT: This paper presents an on-wafer characterization method for transistor threshold voltage degradation caused by hot-carrier injection and bias temperature instability using conventional Ring-Oscillator configurations. One of the key advantages of our proposed method is its ability to estimate the threshold voltage shift of each individual transistor within the gate while operating under AC stress conditions. Additionally, our approach effectively eliminates transistor variability. By employing a method that monitors the collective behavior of multiple transistors simultaneously, we can mitigate the impact of variability–such as differences arising from manufacturing processes and operational conditions. This enhancement not only improves the accuracy of estimations for transistor threshold voltage shift by aging but also leads to more reliable predictions regarding the long-term degradation mechanisms of the circuits. Thus, this characterization method serves as a valuable tool for actual manufacturing processes in terms of both cost and time efficiency.	PDF Xplore
2.3	SiC DMOSFET Real Wafer Level HTRB and HTGB Evaluation N. Hong Seng, T. Ai Heong1, B. Shun Xiar2, L. Johnny3, L. Jia Wei1 Quality, Reliability, X-FAB Sarawak, Kuching, Malaysia 1Marketing, Nexustest, Singapore 2Sales, Nexustest, Singapore 3Customer Project, X-FAB Texas, Lubbock, USA DOI: 10.1109/ICMTS63811.2025.11068904 ABSTRACT: Since 1990s, Silicon Carbide (SiC) was considered as important semiconductor materials for high-power and high-temperature applications due to their superior properties compared to silicon. However, evaluating the long-term reliability of SiC devices under extreme conditions remains critical with conventional packaged level testing approach. This paper presents Wafer Level (WL) reliability evaluation results of SiC double-implanted metal-oxide semiconductor field-effect transistor (DMOSFET) focusing on High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) testing with threshold voltage monitoring (Vth). The evaluation result has showed 500 sites have been assessed successfully. The works demonstrated true wafer level measurement setup with special probe pins directly touching on probe pads without wafer backgrinding, wafer dicing and ceramic or plastic packaging processes at all.	PDF Xplore
2.4	Novel Fractal Points Implementation for Electron Beam Inspection (EBI) and Data Analysis P. J. Mo, T. Y. Ho1, T. Asano1, X. Ji2, K. Y. Chung3, Y. C. Wang3 OMT RAM RDA Application, Micron Technology, Taichiung City, Taiwan 1F15 ADTJ PIE HPM, Micron Technology, Higashi Hiroshima-shi, Japan 2FE CPIE, Micron Technology, Sigapore, Sigapore 3Field Appication, ASML, Taoyuan City, Taiwan DOI: 10.1109/ICMTS63811.2025.11068899 ABSTRACT: In this work, novel fractal points have been introduced for EBI and results analysis in DRAM manufacturing that successfully boost signal resolution from within a die to a fractal point. With the implementation of the EBI recipe, the results show a significant improvement in nuisance defects reduction by 98.1%, as well as an increase in defects of interest (DOI) by 255.7%. Moreover, the Cohen's d value of -1.32 indicates a substantial improvement in data discriminability. On the other hand, defect results with implementing fractal points demonstrate the new capabilities and value for microscopic EBI data analysis. With 10K-fold enhancement for resolution, specific weak region and defective probability for each unit can be identified. They provide new insights into evaluating die quality that indicate explicit direction to shorten the yield learning cycle and accelerate technology development prior to probe readings.	PDF Xplore
2.5	Withdrawn Y.-H. Cheng

Session 3: Device Characterization

3.1	Withdrawn E. A. Diallo
3.2	D-Mode GaN/AlGaN/GaN MOS-HEMT Test Structures for Evaluating Gate Dielectric Impact on Device Performance A. S. Aguirre-Sanchez, R. Aggarwal, C. D. Young, R. A. Rodriguez-Davila, J. Anderson1, E. L. Piner1, M. A. Quevedo Materials Science & Engineering, University of Texas at Dallas, Richardson, U.S.A. 1Materials Application Research Center, Texas State University, San Marcos, U.S.A DOI: 10.1109/ICMTS63811.2025.11068905 ABSTRACT: This study presents a set of standardized test structures designed to systematically investigate the influence of gate dielectric materials on depletion-mode GaN/AlGaN/GaN MOS-HEMTs. By employing D-mode HEMTs, transfer length method (TLM) structures, and MOS capacitor structures, comprehensive characterization of essential device parameters, including maximum drain current (ID,MAX), threshold voltage (VTH), transconductance (GM,MAX), subthreshold swing (SS), interface trap density (DIT), and field-effect mobility (μFE) was conducted. Three distinct gate dielectrics (HfO2, Al2O3, and SiNx) were analyzed, revealing clear correlations among dielectric properties, interface quality, and overall device performance. The integrated approach demonstrated the importance of optimized dielectric deposition and interface engineering, highlighting that despite the superior capacitance of high-κ dielectrics like HfO2, interface quality critically influences device performance. This test-bed approach offers a powerful platform for systematically investigating and optimizing gate dielectric integration processes, advancing the development of high-performance GaN-based MOS-HEMT technologies.	PDF Xplore
3.3	TACHI: Tests as a Chip Identifier R. Sada, R. Shirai, M. Shintani1, T. Sato Kyoto University, Sakyo, Kyoto, Japan 1Kyoto Institute of Technology, Sakyo, Kyoto, Japan DOI: 10.1109/ICMTS63811.2025.11068925 ABSTRACT: This paper proposes a novel method for establishing individual chip traceability in shipped integrated circuits without requiring additional circuit area. The proposed approach leverages inherent characteristic variations present among chips by storing pre-shipment test measurements to enable accurate chip identification. These results are processed to generate criterion vectors that enable accurate chip identification. Evaluation using real wafer test data containing 21,974 chips demonstrated a 99.32% identification accuracy when utilizing criterion vectors constructed from 80 different test items.	PDF Xplore
3.4	Reducing Short-Circuit Current of CMOS Inverter Circuits with "PN-Body Tied SOI-FET" K. Nakahashi, T. Mori, J. Ida Division of Electrical Engineering, Kanazawa Institute of Technology, Nonoichi, Japan DOI: 10.1109/ICMTS63811.2025.11068915 ABSTRACT: We experimentally confirmed that the steep subthreshold slope (SS) device "PN body-tied silicon-on-insulator (SOI) field-effect transistor" can reduce the short-circuit current of a complementary metal-oxide semiconductor (CMOS) inverter. When the NMOS and PMOS steep SS positions overlap, they exhibit nearly right-angled transfer characteristics compared to conventional SOI CMOS. In this situation, the short-circuit current was also observed to be very small. This result confirms the possibility of achieving nearly zero short-circuit current in devices with steep SS.	PDF Xplore

Session 4: Design & Layout

4.1	Layout experiments and test structures to characterize Local Layout Effects due to mechanical stress in FinFET transistors A. Rossoni, T. Brozek1, S. Saxena2, R. Khamankar2, C. Hess1, J. Huang3, Y. Teng3, Z. Kovacs-Vajna4, M. Quarantelli5 Dept. Information Engineering, PDF Solutions, Inc., University of Brescia, Brescia, Italy 1PDF Solutions, Inc., Santa Clara, CA, USA 2PDF Solutions, Inc., Dallas, TX, USA 3PDF Solutions, Inc., Hsinchu, Taiwan 4Dept. Information Engineering, University of Brescia, Brescia, Italy 5PDF Solutions, Inc., Brescia, Italy DOI: 10.1109/ICMTS63811.2025.11068908 ABSTRACT: This paper presents a characterization approach to study Local Layout Effects (LLEs) in FinFET devices. Since mechanical stress is commonly used as a mobility booster in modern transistors, layout-induced stress modulation will cause changes in performance. To investigate devices sensitivities and magnitude of variation a set of test structures with a broad range of Design of Experiment (DoE) factors is proposed, focusing on two layout features: FinFET isolation (diffusion break) and Gate Cut isolation. The test structures were deployed on 7nm test chip as part of PDF Characterization Vehicle CV® and electrical results showed that the magnitude of investigated LLEs could be as high as 13%. TCAD simulation study performed on the designed test structures confirmed that the performance variability can be explained by modulation of the mechanical stress.	PDF Xplore
4.2	Estimating Verticality Parameters in Deep Reactive Ion Etching using MEMS Oscillators S. Yasunaga, Y. Mita Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS63811.2025.11068919 ABSTRACT: In view of characterizing a vertical profile of deep reactive ion etching (DRIE) without making a cross section, we propose a method to estimate representative parameters, namely, the underetched cross-section area and the second moment of area. The test structure consists of a series of MEMS oscillators, the resonance frequency of which was plotted for varied spring stiffness and fitted to a physical model derived from geometry. The estimation from oscillation measurement was compared to the actual profile parameters obtained from visual observation, showing correlation R2=0.556 and 0.913 for the underetch area and the second moment of area, respectively.	PDF Xplore
4.3	Non-uniformities in MOSFET-array characteristics caused by probe-induced mechanical stress P. Sarazá-Canflanca, X. Fan1, S. Van Beek, E. Bury, B. Kaczer imec, Leuven, Belgium 1Chengdu Technological University, Chengdu, Sichuan, P.R.China DOI: 10.1109/ICMTS63811.2025.11068898 ABSTRACT: We study the impact of probe-induced mechanical stress on the characteristics of MOSFETs in transistor arrays by measuring our samples with different probe overdrive, and, thus, different amounts of probe-induced mechanical stress. We demonstrate that, despite the relatively high thickness of the back-end-of line (BEOL) layers of the sample (~10 μm), the mechanical stress can propagate from the pads, through the BEOL and down to the test transistors. This vertical compressive stress enhances the ON-state characteristics of the NFETs located below the probing pads, whereas it degrades those of the PFETs located at the same location. On the other hand, the transistors that are not below the probing pads remain unaffected. We perform finite element simulation of the propagation of mechanical stress through the BEOL layers, which corroborates that the apparent spatial non-uniformity of the transistor characteristics within the array can be attributed to probe-induced mechanical stress. These results highlight the importance of accounting for the impact of probe-induced mechanical stress even when measuring samples with a considerably thick BEOL. Finally, we propose the possibility of exploiting the impact of probe-induced mechanical stress on MOSFET characteristics as a detection mechanism versus probing attacks in the context of hardware security.	PDF Xplore
4.4	Methodology and Test Structures for Studying β-Ga2O3 Dielectric and Contact Interfaces A. A. Gruszecki, J. Roy, K. S. Agrawal1, P. La Torraca1, K. Cherkaoui1, P. K. Hurley1, R. M. Wallace, C. D. Young Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX, USA 1Tyndall National Institute University College Cork, Cork, Ireland DOI: 10.1109/ICMTS63811.2025.11068900 ABSTRACT: An outline of versatile device structures and test methodologies is provided to streamline the fabrication and characterization of β-Ga2O3 and other novel semiconductor materials for the purpose of investigating gate oxide and metal contact interfaces. β-Ga2O3/Al2O3 metal-oxide-semiconductor capacitors (MOSCAPs) and β-Ga2O3/Ti/Au transfer length method (TLM) structures are fabricated for preliminary investigation of dielectric trapping and contact properties as a function of processing. Multifrequency C-V measurements of MOSCAPs show negligible differences in charge trapping at or near the oxide interface following ultraviolet-ozone (UV-O3) surface pretreatment. Additionally, I-V TLM characterization demonstrates improvements in ohmic contact properties after an O2 plasma surface cleaning prior to metallization.	PDF Xplore

Session 5: RF & Power

5.1	A new test structure for charge pumping current measurement in vertical Si power device T. Ohguro, K. Oasa, T. Yasutake, T. Hara, T. Nishiwaki, K. Kobayashi, H. Kato Advanced Semiconductor Device Development Center, Toshiba Electronic Devices & Storage Corporation DOI: 10.1109/ICMTS63811.2025.11068909 ABSTRACT: We propose a novel test structure for charge pumping current (Icp) measurement to estimate the interface state density at gate insulator/Si substrate in vertical Si power MOSFET. In this structure, the source and base of that are separated by modifying the layout of implantation and trench contact, without requiring additional process steps.	PDF Xplore
5.2	A Novel Separated Source Electrodes Kelvin (SSEK) Structure for Extracting Channel Mobility in the 4H-SiC VDMOSFET W. -S. Chen, A. -C. Li, C. -L. Hung1, Y. -K. Hsiao1, B. -Y. Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C. 1Semiconductor Research Center, Hon Hai Research Institute, Hsinchu, Taiwan, R. O. C. DOI: 10.1109/ICMTS63811.2025.11068902 ABSTRACT: A novel Separated Source Electrodes Kelvin (SSEK) structure is proposed to effectively eliminate most of the series resistance in a VDMOSFET, enabling accurate channel mobility extraction. By utilizing the SSEK structure, we can separately measure the resistance of the left and right channels, thereby achieving more precise channel mobility extraction and effectively evaluating process improvements for vertical power MOSFETs.	PDF Xplore
5.3	Modified Angelov Model with Improved Accuracy for RF GaN-on-Si HEMTs D. C. Chen, M. L. Chou, K. Lin, M. Hsieh, P. Lin, H. C. Lin, K. Lee, A. Hou, B. Lin, M. C. Lai Wavetek Microelectronics Corporation (WTK), HsinChu, Taiwan DOI: 10.1109/ICMTS63811.2025.11068906 ABSTRACT: Modified Angelov model with improved accuracy for RF GaN-on-Si HEMTs is proposed and verified. In this work, major model equations for accuracy improvement are analyzed. WTK's GaN-on-Si GS50 dual-gate RF switch technology is applied for the demonstration of model accuracy with the measurement data of DC I-V, S-parameters (SP), and large-signal (LS). Model and Process Design Kit (PDK) are released for customer design and manufacturing already.	PDF Xplore
5.4	Passive and Causal Modeling of 300-GHz-Band IC Capacitors Using Rational Polynomial Approximation S. Beppu, Y. Hirayama, S. Hara1, A. Kasamatsu1, Y. Mita2, K. Tkano Department of Electrical Engineering, Tokyo University of Science, Chiba, Japan 1National Institute of Information and Communications Technology, Tokyo, Japan 2Department of Electrical Engineering and Information systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS63811.2025.11068931 ABSTRACT: This research presents a method to model metal-oxide-metal (MOM) capacitors for 300-GHz band applications using rational polynomial approximation (RPA). While initial approximations often lead to negative element values due to measurement errors, the model is redefined by re-fitting with restrictions to ensure passivity and causality. This approach produces accurate equivalent circuits suitable for high-frequency simulations. The method was validated with measurement with test structure chip fabricated with 0.13 μm SiGe BiCMOS process.	PDF Xplore

Session 6: Cryogenic Measurements

6.1	Oscillation in Cryogenic DC Measurements of High Power LDMOS Devices and Solution Y. Wang, K. Xia1, G. Niu, M. Hamilton, X. Cheng2 ECE Department, Alabama Micro/Nanoelectronics Science and Technology Center, Auburn University, Auburn, AL, USA 1TSMC, Taiwan, R.O.C. 2NXP Semiconductors, Arizona, USA DOI: 10.1109/ICMTS63811.2025.11068933 ABSTRACT: Cryogenic DC measurements of high-power LDMOS devices reveal unique oscillations at low temperatures, which disappear above 200 K. These oscillations are linked to negative differential resistance (NDR) caused by self-heating. To address this, we introduce a resistor between the drain and source terminals, effectively eliminating the oscillations. Combined with DC de-embedding, this method ensures accurate device characterization across a wide temperature range. Our results demonstrate the effectiveness of this approach, providing a reliable solution for cryogenic applications and enhancing the understanding of the behavior of the LDMOS device at low temperatures.	PDF Xplore
6.2	Measurement of Subthreshold Current Variability at 1.5 K Using Addressable MOSFET Array T. Mizutani, K. Takeuchi, T. Saraya, H. Oka1, T. Mori1, M. Kobayashi, T. Hiramoro Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 1National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan DOI: 10.1109/ICMTS63811.2025.11068907 ABSTRACT: Variability of 65 nm bulk MOSFETs in subthreshold region was measured at 300 K and 1.5 K using addressable transistor arrays. It was confirmed that variability of current onset voltage (COV) significantly increases at 1.5 K. It is shown that the cut-off performance of the FETs at 1.5 K is governed by variability of subthreshold current including COV, rather than steep minimum subthreshold slope.	PDF Xplore
6.3	Hysteresis-Induced Neuromorphic Behavior in 180nm Bulk PMOS Devices at 3K F. Imroze, B. Yalagala, M. Ahmad, M. Elsayed, R. Graham, G. Colletta, H. Heidari, M. Weides James Watt School of Engineering, University of Glasgow, Glasgow, United Kingdom DOI: 10.1109/ICMTS63811.2025.11068927 ABSTRACT: There is a growing demand for energy efficient and high-performance computing devices to implement complex and powerful machine learning algorithms for artificial intelligence (AI). One possible solution to achieve the desired high performance by leveraging the mature and standard CMOS technology with the emerging neuromorphic computing operating at cryogenic temperatures. This work investigates the neuromorphic behavior of TSMC 180nm bulk PMOS devices at 3K, focusing on hysteresis and synaptic characteristics. Gated pulsed measurements reveal potentiation and depression behavior, with conductance changes due to pulse amplitude and width variations. These findings contribute to the early-stage development of cryogenic neuromorphic computing systems.	PDF Xplore

Session 7: Process Characterization

7.1	A Test Structure for Analyzing Self-Heating Induced Distortion in On-Chip Current Sensing Resistors H. Ma, S. Karmakar, H. Zhang, Y. Liu, H. Guo1, M. Berkhout2, Q. Fan Delft University of Technology, Delft, The Netherlands 1ams OSRAM, Plano, USA 2Monolithic Power Systems, Enschede, The Netherlands DOI: 10.1109/ICMTS63811.2025.11068913 ABSTRACT: This paper presents a test structure for a 27 mΩ diffusion current sensing resistor, designed to analyze distortion caused by self-heating in audio power amplifiers. A parallel Kelvin connection minimizes parasitic effects, reducing resistance error to 0.4% and temperature coefficient error to 0.7%. A diode-based temperature sensor array enables accurate measurement of temperature variations, allowing the characterization of HD3 with an inaccuracy of <1.4 dB. Eventually, the HD3 is compensated by at least 15 dB through the sensed average temperature.	PDF Xplore
7.2	Novel Test Structures for 3D NAND Array Plasma Damage Monitoring K. Kalia, R. R. Bottini1, K. Marr2, A. Mcteer3, C. Z. Mow4, J. Davis5 Scribe Array Design Micron Technology, Inc., Boise, USA 1CMOS Reliability Micron Technology, Inc., Vimercate, Italy 2Reliability Methods Micron Technology, Inc., Boise, USA 3PD NAND, Micron Technology, Inc., Boise, USA 4ADTS ATI, Micron Technology, Inc., Singapore 5E-Char/TCAD, Micron Technology, Inc., Boise, USA DOI: 10.1109/ICMTS63811.2025.11068924 ABSTRACT: The innovative test structure introduced in this work stems from a specific need to develop an electrical proxy to monitor charge damage induced by the processing of 3DNAND arrays. For the first time, the gates of the NHV and NLV transistor were connected to a portion of the array acting as an antenna. The findings show that, as expected from the literature, the failure mode depends on the thickness of the gate oxide. NHV transistors show charge trapping and no gate leakage, while NLV transistors are heavily damaged with high gate leakage but showing a threshold in the target (SILC - Stress Induced Leakage current). This work demonstrated that by incorporating an appropriate sensor structure, changes in electrical characteristics due to plasma interactions can be detected, to monitor array PID.	PDF Xplore
7.3	Advantage and Challenge of Electrical Critical Dimension Test Structures for Electroplated High Aspect Ratio Nano Structures (HARNS) on Insulating Materials Y. Mita, A. Mizushima, N. Kawai1, T. Shinji1, Y. Inoue1, E. Ohta1, S. Yasunaga, R. Nakane1, D. Bourrier2, A. Beghersa2, H. Granier2, A. Higo1 Department of Electrical Engineering and Information Systems, the University of Tokyo 1Systems Design Lab (d.lab), School of Engineering, the University of Tokyo 2LAAS-CNRS, Toulouse, France DOI: 10.1109/ICMTS63811.2025.11068934 ABSTRACT: Electrical Critical Dimension Test Structures (ECD-TS) have been applied for development of new technology: Metallic High Aspect Ratio Nano Structures (Metal-HARNS). The HARNS refer to electro mechanical structures scaled down to submicron width (as narrow as 260nm confirmed) while keeping its thickness (up to 1500nm confirmed). Two major advantage and challenge have been confirmed through measurement: (1) insulating material showed critical advantage on ECD over Scanning Electron Microscope CD assessment and (2) seed conductive layer affected the measurement as leakage path.	PDF Xplore
7.4	Fabrication of NbO2 based IMT Selector Devices via a 300mm Based Memory Test Vehicle K. Beckmann, M. Rodgers, T. Wallach1, R. Paries1, N. Cady1 Technology Development, NY CREATES, Albany, NY, USA 1College of Nanotechnology Science and Engineering, University at Albany, Albany, NY, USA DOI: 10.1109/ICMTS63811.2025.11068920 ABSTRACT: The demand for differentiated devices in the backend-of-line increases necessitates the need for a test vehicle that enables the integration and electrical characterization of such devices. An Insulator-Metal Transition based NbO2 device was integrated onto the NY CREATES/UAlbany memory test vehicle (MTV) utilizing a 65nm process technology to fabricate nanoscale devices with a footprint down to 120x120 nm2. NbO2, the metastable allotrope of niobium oxide, was deposited onto coupons diced out of the 300mm MTV. This occurred in an oxygen-controlled environment yielding phase-pure NbO2 after a 750 ºC crystallization anneal. An endurance of at least 25x106 cycles was demonstrated with an Roff/Ron ratio above 100 and an extrapolation towards >2000 with further device scaling.	PDF Xplore

Session 8: Test Optimization

8.1	Smart Diagnostics for 3D CFET: A Machine Learning Approach to Failure Analysis J. Mitard, H. M. Kocak1, T. Chiarella, C. Sheng2, S. Demuyck2, N. Horiguchi2 Department IMEC, Compute Technology Device, Belgium 1Imec & Department of Computer Science, KU Leuven, Belgium 2Process Integration Department, IMEC, Belgium DOI: 10.1109/ICMTS63811.2025.11068926 ABSTRACT: This work introduces a novel Convolutional Neural Network for classifying transfer characteristics in emerging Gate-All-Around MOSFET. Trained on vast experimental dataset, the algorithm successfully identifies distinct failure modes across wafers with complex processing variations. The automated analysis enables faster yield enhancement and process optimization for next-generation 3D MOSFET technologies.	PDF Xplore
8.2	Automatic PSP MOSFET model card extraction powered by deep learning A. O. Rodriguez, F. Gilibert1, F. Paolini1, A. Gerard1, E. Vincent1, N. Derrier1, M. Quoirin1, P. Urard1, J. Samuel2, R. Cellier3, L. Labrak3, N. Abouchi3 STMicroelectronics 860, Crolles, France 1STMicroelectronics, Crolles, France 2CPE Lyon, LIRIS CNRS UMR 5205, University of Lyon, France 3CPE Lyon - INL CNRS UMR 5270, University of Lyon, France DOI: 10.1109/ICMTS63811.2025.11068923 ABSTRACT: The semiconductor industry's need for efficient model card extraction is addressed by a Deep-Learning-powered tool that automates this process for PSP MOSFETs. 59 parameters are predicted with an average 2.06% error, reducing extraction time from weeks to one day, enabling statistical analysis and improving workflow efficiency.	PDF Xplore
8.3	Active Sampling of Electrical Characterization Parameters for Efficient Measurement H. M. Kocak, J. Mitard1, A. T. Naskali2, J. Davis Department of Computer Science, KU Leuven, Belgium 1Compute Technology Device Department, IMEC, Belgium 2Department of Computer Engineering, Galatasaray University, Turkey DOI: 10.1109/ICMTS63811.2025.11068930 ABSTRACT: The electrical characterization of semiconductor devices plays an important role in guiding the research on experimental architectures and evaluating the performance of devices. However, testing all the fabricated devices is an exhaustive process, which has become almost impossible due to time and resource constraints. This paper introduces a new way to perform electrical characterization that leverages a combination of Gaussian Process Regression (GPR) and Active Sampling (AS) techniques. The proposed methodology dynamically selects key gate voltages and artificially reconstructs a complete Id-Vg curve to significantly reduce the time required for characterization. The value of the proposed method was verified through a diverse dataset of 5000 N and P MOS devices, including FinFET and CFET architectures under various device design and process variations. We experimentally demonstrate that our approach achieves a reduction in the number of measurements by a factor of three to seven while maintaining a threshold voltage accuracy within a 19 mV error and a subthreshold slope error of 6 mV/dec.	PDF Xplore
8.4	Test Accuracy Improvement of Ensemble Gaussian Process-based IC Outlier Detection Using Temporal Similarity Among Wafers D. Goeda, T. Nakamura1, M. Kajiyama1, M. Eiki1, H. Takayama, T. Sato2, M. Shintani Graduate School of Science and Technology, Kyoto Institute of Technology, Matsugasaki, Sakyo-ku, Kyoto, Japan 1Sony Semiconductor Manufacturing Corporation, Tsukuba-machi, Isahaya-shi, Japan 2Graduate School of Informatics, Kyoto University, Yoshida-hon-machi, Sakyo-ku, Kyoto, Japan DOI: 10.1109/ICMTS63811.2025.11068929 ABSTRACT: The IC outlier detection method, which compares measured and predicted characteristics by ensemble learning with Gaussian processes (EGPR), drastically improves IC test accuracy compared to existing statistical methods. However, detecting faulty chips at the edge of a wafer is still challenging because they exhibit different characteristic trends than others. Moreover, test accuracy degrades when fault clusters exist on a wafer, because the prediction accuracy inevitably degrades due to the effects of faulty chips. In this study, we improve the test accuracy of the EGPR-based method by averaging measurements with values from adjacent wafers, leveraging the similarity in characteristics within the same lot. Experimental results using industrial IC test results indicate that the proposed method reduces test escapes by 6.40% compared to the conventional EGPR-based method while maintaining computation time. We also demonstrate that the proposed method improves the fault detection rate by 27.9% using an artificial dataset with a fault cluster.	PDF Xplore
8.5	Evaluation of Rapid Vt Testing of Wafer-Level MOSFETs M. H. Herman, B. Morris Authors are with Parametric Test Group, Advantest America, San Jose, CA, United States DOI: 10.1109/ICMTS63811.2025.11068928 ABSTRACT: We evaluate applicability of a spot Ids method of rapid Vt test to wafer-level CMOS transistor testing. We discuss reference data requirements vs Vds bias, body bias, and W/L sizes with respect to Vt error. We compare Rapid Vt to full Vgs sweep Vt values on CMOS wafer NMOS and PMOS transistors and demonstrate comparable channel doping results.	PDF Xplore

Session 9: MEMS & Sensors

9.1	Microheater integration in gate dielectric functionalized a-IGZO thin film transistors for methanol sensing M. Calderon-Gonzalez, M. L. Tietze1, S. Mondal, E. Georgitzikis, D. Cheyns, R. Ameloot1, J. Genoe imec, Leuven, Belgium 1Department of Microbial and Molecular Systems (M2S), KU Leuven, Belgium DOI: 10.1109/ICMTS63811.2025.11068903 ABSTRACT: Volatile organic compound sensors continue to face challenges in achieving key requirements for their practical use. In this context, metal-organic framework functionalized field-effect transistors hold great potential as game-changers in gas sensing, however, they are prone to baseline drift as many other gas sensing technologies. To address this issue, we integrated a microheater to facilitate degassing of residual gases. The thermal distribution of the microheater was evaluated by using temperature-sensing test structures. Additionally, the importance of the metal-organic framework as an enabler for methanol sensing was demonstrated. The influence of temperature pulses on the intrinsic characteristics of the a-IGZO channel was further addressed, showing a reversible de-trapping of electrons. By applying heating pulses of 100ºC from the integrated microheater, the baseline drift caused by residual methanol was successfully corrected.	PDF Xplore
9.2	Enhanced Permittivity in PEALD Al2O3/TiO2 Nanolaminates: Investigating Maxwell-Wagner and Interfacial Polarization in IDEs Z. M. Karimi, J. A. Davis Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia DOI: 10.1109/ICMTS63811.2025.11068916 ABSTRACT: This work combines precise nanofabrication methods with quasi-electrostatic finite element method (FEM) simulations to investigate possible enhancement of polarizability of localized dipoles along the interfacial planes of multilayer Al2O3/TiO2 nanolaminates. The dipole formation along these inter-material laminate boundaries is contrasted with non-localized charge movement phenomena that is typically studied in these laminates because of disparate values of the conductivity between Al2O3 and TiO2 which results in Maxwell-Wagner (MW) polarization. This MW polarization is dominant at low frequencies in metal-insulator-metal (MIM) capacitive device structures. In this work, however, electrical measurements from high-density in-plane interdigitated electrode (IDE) structures with Al2O3/TiO2 nanolaminates that are grown using Plasma Enhanced Atomic Layer Deposition (PEALD) are explored. Using FEM electromagnetic simulations suggest that the anomalous capacitance cannot be attributed to just MW effects and must also have a localized dipole effect that occurs at the interfacial boundaries. It is shown that the average relative permittivity in the vicinity of these heterogeneous interfaces (~1 nm) at a frequency of 1 kHz is extracted to be kAl2O3/TiO2 ~ 6615.	PDF Xplore
9.3	Planar FDSOI Reconfigurable Schottky Barrier FETs for Gas Sensing A. Kramer, T. Krauss, M. Reuter, J. Kulenkampff, D. Korner, K. Hofmann Integrated Electronic Systems Lab, Technical University of Darmstadt, Darmstadt, Germany DOI: 10.1109/ICMTS63811.2025.11068921 ABSTRACT: In this work we present experimental data of a gas sensitive thin channel planar Schottky barrier FET based on a thin palladium front-gate, manufactured using a fully depleted SIMOX SOI with a global back-gate. We show that the drain current is sensitive to ambient air and different ammonia concentrations in vacuum with adjustable sensitivity via the back-gate voltage at room temperature.	PDF Xplore

Papers By First Author

3.2	D-Mode GaN/AlGaN/GaN MOS-HEMT Test Structures for Evaluating Gate Dielectric Impact on Device Performance A. S. Aguirre-Sanchez, R. Aggarwal, C. D. Young, R. A. Rodriguez-Davila, J. Anderson1, E. L. Piner1, M. A. Quevedo Materials Science & Engineering, University of Texas at Dallas, Richardson, U.S.A. 1Materials Application Research Center, Texas State University, San Marcos, U.S.A DOI: 10.1109/ICMTS63811.2025.11068905 HOVER FOR ABSTRACT	PDF Xplore
7.4	Fabrication of NbO2 based IMT Selector Devices via a 300mm Based Memory Test Vehicle K. Beckmann, M. Rodgers, T. Wallach1, R. Paries1, N. Cady1 Technology Development, NY CREATES, Albany, NY, USA 1College of Nanotechnology Science and Engineering, University at Albany, Albany, NY, USA DOI: 10.1109/ICMTS63811.2025.11068920 HOVER FOR ABSTRACT	PDF Xplore
5.4	Passive and Causal Modeling of 300-GHz-Band IC Capacitors Using Rational Polynomial Approximation S. Beppu, Y. Hirayama, S. Hara1, A. Kasamatsu1, Y. Mita2, K. Tkano Department of Electrical Engineering, Tokyo University of Science, Chiba, Japan 1National Institute of Information and Communications Technology, Tokyo, Japan 2Department of Electrical Engineering and Information systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS63811.2025.11068931 HOVER FOR ABSTRACT	PDF Xplore
1.1	Power switch improvement for RO array characterization in 18nm FD-SOI technology platform validation C. Cagli, F. Pourchon, H. Degoirat, J. B. Moulard, F. Granoux, M. Dahmani, R. Wilson STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS63811.2025.11068914 HOVER FOR ABSTRACT	PDF Xplore
9.1	Microheater integration in gate dielectric functionalized a-IGZO thin film transistors for methanol sensing M. Calderon-Gonzalez, M. L. Tietze1, S. Mondal, E. Georgitzikis, D. Cheyns, R. Ameloot1, J. Genoe imec, Leuven, Belgium 1Department of Microbial and Molecular Systems (M2S), KU Leuven, Belgium DOI: 10.1109/ICMTS63811.2025.11068903 HOVER FOR ABSTRACT	PDF Xplore
5.2	A Novel Separated Source Electrodes Kelvin (SSEK) Structure for Extracting Channel Mobility in the 4H-SiC VDMOSFET W. -S. Chen, A. -C. Li, C. -L. Hung1, Y. -K. Hsiao1, B. -Y. Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C. 1Semiconductor Research Center, Hon Hai Research Institute, Hsinchu, Taiwan, R. O. C. DOI: 10.1109/ICMTS63811.2025.11068902 HOVER FOR ABSTRACT	PDF Xplore
5.3	Modified Angelov Model with Improved Accuracy for RF GaN-on-Si HEMTs D. C. Chen, M. L. Chou, K. Lin, M. Hsieh, P. Lin, H. C. Lin, K. Lee, A. Hou, B. Lin, M. C. Lai Wavetek Microelectronics Corporation (WTK), HsinChu, Taiwan DOI: 10.1109/ICMTS63811.2025.11068906 HOVER FOR ABSTRACT	PDF Xplore
2.5	Withdrawn Y.-H. Cheng HOVER FOR ABSTRACT
3.1	Withdrawn E. A. Diallo HOVER FOR ABSTRACT
1.2	Comparative Study of Switching Dynamics in Ferroelectric-based Capacitors with Different Design Options F. Driussi, E. Rocco, M. Massarotto, S. Lancaster1, S. Slesazeck1, T. Mikolajick1, D. Esseni DPIA, University of Udine, Udine, Italy 1NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS63811.2025.11068911 HOVER FOR ABSTRACT	PDF Xplore
8.4	Test Accuracy Improvement of Ensemble Gaussian Process-based IC Outlier Detection Using Temporal Similarity Among Wafers D. Goeda, T. Nakamura1, M. Kajiyama1, M. Eiki1, H. Takayama, T. Sato2, M. Shintani Graduate School of Science and Technology, Kyoto Institute of Technology, Matsugasaki, Sakyo-ku, Kyoto, Japan 1Sony Semiconductor Manufacturing Corporation, Tsukuba-machi, Isahaya-shi, Japan 2Graduate School of Informatics, Kyoto University, Yoshida-hon-machi, Sakyo-ku, Kyoto, Japan DOI: 10.1109/ICMTS63811.2025.11068929 HOVER FOR ABSTRACT	PDF Xplore
4.4	Methodology and Test Structures for Studying β-Ga2O3 Dielectric and Contact Interfaces A. A. Gruszecki, J. Roy, K. S. Agrawal1, P. La Torraca1, K. Cherkaoui1, P. K. Hurley1, R. M. Wallace, C. D. Young Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX, USA 1Tyndall National Institute University College Cork, Cork, Ireland DOI: 10.1109/ICMTS63811.2025.11068900 HOVER FOR ABSTRACT	PDF Xplore
8.5	Evaluation of Rapid Vt Testing of Wafer-Level MOSFETs M. H. Herman, B. Morris Authors are with Parametric Test Group, Advantest America, San Jose, CA, United States DOI: 10.1109/ICMTS63811.2025.11068928 HOVER FOR ABSTRACT	PDF Xplore
6.3	Hysteresis-Induced Neuromorphic Behavior in 180nm Bulk PMOS Devices at 3K F. Imroze, B. Yalagala, M. Ahmad, M. Elsayed, R. Graham, G. Colletta, H. Heidari, M. Weides James Watt School of Engineering, University of Glasgow, Glasgow, United Kingdom DOI: 10.1109/ICMTS63811.2025.11068927 HOVER FOR ABSTRACT	PDF Xplore
7.2	Novel Test Structures for 3D NAND Array Plasma Damage Monitoring K. Kalia, R. R. Bottini1, K. Marr2, A. Mcteer3, C. Z. Mow4, J. Davis5 Scribe Array Design Micron Technology, Inc., Boise, USA 1CMOS Reliability Micron Technology, Inc., Vimercate, Italy 2Reliability Methods Micron Technology, Inc., Boise, USA 3PD NAND, Micron Technology, Inc., Boise, USA 4ADTS ATI, Micron Technology, Inc., Singapore 5E-Char/TCAD, Micron Technology, Inc., Boise, USA DOI: 10.1109/ICMTS63811.2025.11068924 HOVER FOR ABSTRACT	PDF Xplore
9.2	Enhanced Permittivity in PEALD Al2O3/TiO2 Nanolaminates: Investigating Maxwell-Wagner and Interfacial Polarization in IDEs Z. M. Karimi, J. A. Davis Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia DOI: 10.1109/ICMTS63811.2025.11068916 HOVER FOR ABSTRACT	PDF Xplore
8.3	Active Sampling of Electrical Characterization Parameters for Efficient Measurement H. M. Kocak, J. Mitard1, A. T. Naskali2, J. Davis Department of Computer Science, KU Leuven, Belgium 1Compute Technology Device Department, IMEC, Belgium 2Department of Computer Engineering, Galatasaray University, Turkey DOI: 10.1109/ICMTS63811.2025.11068930 HOVER FOR ABSTRACT	PDF Xplore
9.3	Planar FDSOI Reconfigurable Schottky Barrier FETs for Gas Sensing A. Kramer, T. Krauss, M. Reuter, J. Kulenkampff, D. Korner, K. Hofmann Integrated Electronic Systems Lab, Technical University of Darmstadt, Darmstadt, Germany DOI: 10.1109/ICMTS63811.2025.11068921 HOVER FOR ABSTRACT	PDF Xplore
2.1	The Hot Carrier Injection Induced Degradation in MOS Transistors with Subthreshold Hump and the Corelated Impacts on Low Frequency Noise for Low Power Analog Designs W. Li, K. Xia1, R. Xu, L. Chao NXP Semiconductors, Front End Innovation 1TSMC, Power Management Business Development DOI: 10.1109/ICMTS63811.2025.11068917 HOVER FOR ABSTRACT	PDF Xplore
7.1	A Test Structure for Analyzing Self-Heating Induced Distortion in On-Chip Current Sensing Resistors H. Ma, S. Karmakar, H. Zhang, Y. Liu, H. Guo1, M. Berkhout2, Q. Fan Delft University of Technology, Delft, The Netherlands 1ams OSRAM, Plano, USA 2Monolithic Power Systems, Enschede, The Netherlands DOI: 10.1109/ICMTS63811.2025.11068913 HOVER FOR ABSTRACT	PDF Xplore
7.3	Advantage and Challenge of Electrical Critical Dimension Test Structures for Electroplated High Aspect Ratio Nano Structures (HARNS) on Insulating Materials Y. Mita, A. Mizushima, N. Kawai1, T. Shinji1, Y. Inoue1, E. Ohta1, S. Yasunaga, R. Nakane1, D. Bourrier2, A. Beghersa2, H. Granier2, A. Higo1 Department of Electrical Engineering and Information Systems, the University of Tokyo 1Systems Design Lab (d.lab), School of Engineering, the University of Tokyo 2LAAS-CNRS, Toulouse, France DOI: 10.1109/ICMTS63811.2025.11068934 HOVER FOR ABSTRACT	PDF Xplore
8.1	Smart Diagnostics for 3D CFET: A Machine Learning Approach to Failure Analysis J. Mitard, H. M. Kocak1, T. Chiarella, C. Sheng2, S. Demuyck2, N. Horiguchi2 Department IMEC, Compute Technology Device, Belgium 1Imec & Department of Computer Science, KU Leuven, Belgium 2Process Integration Department, IMEC, Belgium DOI: 10.1109/ICMTS63811.2025.11068926 HOVER FOR ABSTRACT	PDF Xplore
6.2	Measurement of Subthreshold Current Variability at 1.5 K Using Addressable MOSFET Array T. Mizutani, K. Takeuchi, T. Saraya, H. Oka1, T. Mori1, M. Kobayashi, T. Hiramoro Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 1National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan DOI: 10.1109/ICMTS63811.2025.11068907 HOVER FOR ABSTRACT	PDF Xplore
2.4	Novel Fractal Points Implementation for Electron Beam Inspection (EBI) and Data Analysis P. J. Mo, T. Y. Ho1, T. Asano1, X. Ji2, K. Y. Chung3, Y. C. Wang3 OMT RAM RDA Application, Micron Technology, Taichiung City, Taiwan 1F15 ADTJ PIE HPM, Micron Technology, Higashi Hiroshima-shi, Japan 2FE CPIE, Micron Technology, Sigapore, Sigapore 3Field Appication, ASML, Taoyuan City, Taiwan DOI: 10.1109/ICMTS63811.2025.11068899 HOVER FOR ABSTRACT	PDF Xplore
3.4	Reducing Short-Circuit Current of CMOS Inverter Circuits with "PN-Body Tied SOI-FET" K. Nakahashi, T. Mori, J. Ida Division of Electrical Engineering, Kanazawa Institute of Technology, Nonoichi, Japan DOI: 10.1109/ICMTS63811.2025.11068915 HOVER FOR ABSTRACT	PDF Xplore
5.1	A new test structure for charge pumping current measurement in vertical Si power device T. Ohguro, K. Oasa, T. Yasutake, T. Hara, T. Nishiwaki, K. Kobayashi, H. Kato Advanced Semiconductor Device Development Center, Toshiba Electronic Devices & Storage Corporation DOI: 10.1109/ICMTS63811.2025.11068909 HOVER FOR ABSTRACT	PDF Xplore
8.2	Automatic PSP MOSFET model card extraction powered by deep learning A. O. Rodriguez, F. Gilibert1, F. Paolini1, A. Gerard1, E. Vincent1, N. Derrier1, M. Quoirin1, P. Urard1, J. Samuel2, R. Cellier3, L. Labrak3, N. Abouchi3 STMicroelectronics 860, Crolles, France 1STMicroelectronics, Crolles, France 2CPE Lyon, LIRIS CNRS UMR 5205, University of Lyon, France 3CPE Lyon - INL CNRS UMR 5270, University of Lyon, France DOI: 10.1109/ICMTS63811.2025.11068923 HOVER FOR ABSTRACT	PDF Xplore
4.1	Layout experiments and test structures to characterize Local Layout Effects due to mechanical stress in FinFET transistors A. Rossoni, T. Brozek1, S. Saxena2, R. Khamankar2, C. Hess1, J. Huang3, Y. Teng3, Z. Kovacs-Vajna4, M. Quarantelli5 Dept. Information Engineering, PDF Solutions, Inc., University of Brescia, Brescia, Italy 1PDF Solutions, Inc., Santa Clara, CA, USA 2PDF Solutions, Inc., Dallas, TX, USA 3PDF Solutions, Inc., Hsinchu, Taiwan 4Dept. Information Engineering, University of Brescia, Brescia, Italy 5PDF Solutions, Inc., Brescia, Italy DOI: 10.1109/ICMTS63811.2025.11068908 HOVER FOR ABSTRACT	PDF Xplore
3.3	TACHI: Tests as a Chip Identifier R. Sada, R. Shirai, M. Shintani1, T. Sato Kyoto University, Sakyo, Kyoto, Japan 1Kyoto Institute of Technology, Sakyo, Kyoto, Japan DOI: 10.1109/ICMTS63811.2025.11068925 HOVER FOR ABSTRACT	PDF Xplore
4.3	Non-uniformities in MOSFET-array characteristics caused by probe-induced mechanical stress P. Sarazá-Canflanca, X. Fan1, S. Van Beek, E. Bury, B. Kaczer imec, Leuven, Belgium 1Chengdu Technological University, Chengdu, Sichuan, P.R.China DOI: 10.1109/ICMTS63811.2025.11068898 HOVER FOR ABSTRACT	PDF Xplore
2.3	SiC DMOSFET Real Wafer Level HTRB and HTGB Evaluation N. Hong Seng, T. Ai Heong1, B. Shun Xiar2, L. Johnny3, L. Jia Wei1 Quality, Reliability, X-FAB Sarawak, Kuching, Malaysia 1Marketing, Nexustest, Singapore 2Sales, Nexustest, Singapore 3Customer Project, X-FAB Texas, Lubbock, USA DOI: 10.1109/ICMTS63811.2025.11068904 HOVER FOR ABSTRACT	PDF Xplore
2.2	On-Wafer Characterization of HCI/BTI-induced Threshold Voltage Degradation based Measured Frequency Shift of Ring-Oscillator Circuits C. Tanaka, N. Momo, F. Fujii, O. Kobayashi Memory Division, Kioxia Corporation, Sakae-ku, Yokohama, Japan DOI: 10.1109/ICMTS63811.2025.11068922 HOVER FOR ABSTRACT	PDF Xplore
6.1	Oscillation in Cryogenic DC Measurements of High Power LDMOS Devices and Solution Y. Wang, K. Xia1, G. Niu, M. Hamilton, X. Cheng2 ECE Department, Alabama Micro/Nanoelectronics Science and Technology Center, Auburn University, Auburn, AL, USA 1TSMC, Taiwan, R.O.C. 2NXP Semiconductors, Arizona, USA DOI: 10.1109/ICMTS63811.2025.11068933 HOVER FOR ABSTRACT	PDF Xplore
4.2	Estimating Verticality Parameters in Deep Reactive Ion Etching using MEMS Oscillators S. Yasunaga, Y. Mita Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS63811.2025.11068919 HOVER FOR ABSTRACT	PDF Xplore
1.3	Enhancement of Synaptic Properties using Ta2O5/ZnO/Ta2O5 Tri-layer Device C. -M. Yeom, S. -H. Kim, Y. -B. Kim, D. -M. Kim, K. -S. Roh1, Y. -S. Kim1, Y. -G. Kim2, H. -M. Kwon3, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejeon, Korea 1LAB of Nano Process Technology, National Nanofab Center, Daejeon, Korea 2Department of Green Semiconductor System, Korea Polytechnic, Daegu, Korea 3School of Electronic & Electrical Engineering, Hankyong National University, Anseong, Korea DOI: 10.1109/ICMTS63811.2025.11068932 HOVER FOR ABSTRACT	PDF Xplore