IEEE International Conference on Microelectronic Test Structures

ICMTS 2023 Program

2023 Program Booklet

By Session

1.1	Discrete current limiting circuit for emerging memory programming L. Laborie, P. Trotti, K. Veyret, C. Cagli¹ Univ. Grenoble Alpes,CEA, Leti, Grenoble, France ¹STMicroelectronics, Grenoble, France DOI: 10.1109/ICMTS55420.2023.10094099 ABSTRACT: This work presents a novel, discrete-component circuit for the electrical characterisation of Resistive Random Access Memory (RRAM). The forming of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transistor. The presented DCL circuit is furthermore benchmarked versus other discrete and integrated typologies, showing dramatic improvement over existing discrete solutions, and comparable performances with integrated architectures. Finally, multi-bit storage is experimentally demonstrated through modulation of the programming current amplitude.	PDF Xplore
1.2	Test Methodology Development for Investigating CeRAM at Elevated Temperatures A. A. Gruszecki, R. Prasad, S. V. Suryavanshi¹, G. Yeric¹, C. D. Young Electrical and Computer Engineering Department, The University of Texas at Dallas, Richardson, Texas, USA ¹Cerfe Labs, Austin, Texas, USA DOI: 10.1109/ICMTS55420.2023.10094065 ABSTRACT: Abstract-Correlated electron RAM (CeRAM) device test structures utilizing C-doped NiO were fabricated and electrically characterized to determine functionality in extreme environments. CeRAM devices were demonstrated to repeatedly cycle at temperatures up to 200°C while maintaining a substantial memory window of over 1000 x. Careful selection of compliance current when sweeping the high resistance state (OFF) is required for optimal device performance. The presence of a temperature dependent leakage current in the OFF state results in reducing OFF resistance at elevated temperatures.	PDF Xplore
1.3	Real-time electrical measurements during laser attack on STT-MRAM N. Yazigy, J. Postel-Pellerin, V. D. Marca, R. C. Sousa¹, A. -L. Ribotta², G. D. Pendina¹, P. Canet IM2NP, CNRS, UMR 7334, 5 rue Enrico Fermi, Aix-Marseille Université, Marseille, France ¹CNRS, CEA, SPINTEC, SPINTEC, University Grenoble Alpes, Grenoble, France ²Mines Saint-Etienne, CEA, Leti, Centre CMP, Gardanne, France DOI: 10.1109/ICMTS55420.2023.10094166 ABSTRACT: The goal of the study is to monitor the device’s response during laser injection while being able to track pre- and post-attack conditions. We show the irradiation power affects the STT-MRAM behavior. Our electrical/optical setup enables to know the memory cell behavior to study real-time laser attack countermeasures and device reliability. We have highlighted the possibility to switch, to degrade or even to destruct the cell, depending on the laser power.	PDF Xplore
1.4	Automated RRAM measurements using a semi-automated probe station and ArC ONE interface A. G. Panca, A. Serb, S. Stathopoulos, S. K. Garlapati¹, T. Prodromakis Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh, UK ¹Materials Science And Metallurgical Engineering, Indian Institute of Technology Hyderabad, Telangana, India DOI: 10.1109/ICMTS55420.2023.10094156 ABSTRACT: Resistive Random Access Technology (RRAM) is quickly reaching industrial maturity. A key element towards achieving lasting commercial success, however, is automated testing; useful for performance benchmarking and rapid prototyping of new flavours of technology. Here we present a wafer-scale semi-automated RRAM device testing platform.	PDF Xplore
1.5	Analysis of Critical Schottky Distance Effect and Distributed Set Voltage in HfO2-based 1T-1R Device S. -K. Lin, T. -C. Chang¹, W. -C. Huang¹, Y. -F. Tan², C. -H. Lien Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan ¹Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan ²Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS55420.2023.10094175 ABSTRACT: High resistance state (HRS) resistance on the set voltage in hafnium oxide-based resistance random access memory (RRAM) is investigated. Set voltage has a positive correlation to HRS in statistics. For analyzing the switching characteristics at different HRS resistance level, filament properties in the switching layer are analyzed by current-fitting technique. The fitting results show that Schottky distance becomes saturated at high resistance HRS. Finally, a physical model is proposed to explain our observation.	PDF Xplore

Session 2: Noise

2.1	Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure O. Gauthier, S. Haendler, R. Beucher, P. Scheer, Q. Rafhay¹, C. Theodorou¹ STMicroelectronics, Crolles, France ¹Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP, IMEP-LAHC, Grenoble, France DOI: 10.1109/ICMTS55420.2023.10094087 ABSTRACT: The use of an addressable array test structure designed on a 28 nm FD-SOI technology for the variability analysis of static, low frequency noise (LFN) and Random Telegraph Noise (RTN) matching is presented. The experimental setup was validated, and a statistical analysis of the above electrical quantities is provided. Using such structures, combined with a switching matrix, local and global variability analysis can be performed while significantly increasing the number of samples, thus enabling a better description of the variations in LFN and RTN, especially when RTN signatures can be scarce. We show that local variations dominate the noise variability compared to global variations.	PDF Xplore
2.2	An Extended Method to Analyze Boron Diffusion Defects in 16 nm Node High-Voltage FinFETs T. -T. Kuo, Y. -C. Chen, T. -C. Chang¹, F. -M. Ciou², C. -H. Yeh³, P. -H. Chen⁴, S. M. Sze⁵ Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan ¹Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, Taiwan ²Department of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan ³Department of Photonics, National Sun Yat-sen University, Kaohsiung, Taiwan. ⁴Department of Applied Science, R. O. C. Naval Academy, Kaohsiung, Taiwan ⁵National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS55420.2023.10094125 ABSTRACT: This work proposed extended methods, which can analyze kinds of defects more easily with power spectrum density (PSD) and weighted time lag plot (W-TLP), to decouple single or multi-traps. To get additional high voltage tolerance, it is common to design different kinds of structures dispersing the electric field. In this work, boron and fluorine were doped in the source and drain extension regions to achieve higher voltage operation. However, boron diffusion could worsen the interface quality. Interestingly, after different stress conditions of hot carrier degradation (HCD) and positive bias temperature instability (PBTI), the degradation trends of the two devices show opposite behaviors. It is because the boron can bear the high voltage operation, but also weak the devices’ interface quality. Therefore, to analyze the influence of these defects plays an important role. With Agilent B1530A WGFMU and RTSDataAnalysis software, varied defects response to frequency can be simply detected. It can also use W-TLP to decouple single trap and multi-traps behaviors at the same time.	PDF Xplore
2.3	VSS-Bias-Based Measurement of Random Telegraph Noise in Hybrid SRAM PUF after Hot Carrier Injection Burn-in K. Liu, Y. Tang, S. Xu, H. Shinohara Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan DOI: 10.1109/ICMTS55420.2023.10094138 ABSTRACT: In this paper, a method to observe random telegraph noise in a hybrid SRAM PUF array is presented. This allows low-cost observation of RTN in a number of bitcells by applying VSS bias voltages to measure their temporal mismatches. Also, the changes in RTN amplitude after hot carrier injection burn-in, which is used for PUF stabilization, have been measured and analyzed. Experimental results from a 130-nm CMOS test chip show that the average RTN amplitude across 80-run measurements increases from 1.46 mV before HCI to 9.72 mV after 18-min HCI. The maximum RTN amplitude also increases from 10.13 mV to 84.50 mV. These results indicate that RTN is not an omittable factor especially for a PUF using a hot carrier injection-based stabilization technique and should be carefully considered when deciding the burn-in strategy.	PDF Xplore

Session 3: Power Devices

3.1	Distributed field plate effects in split-gate trench MOSFETs R. Tambone, A. Ferrara, F. Magrini¹, A. Hoffmann¹, A. Wood, G. Noebauer, E. Gondro¹, R. J. E. Hueting² Infineon Technologies Austria AG, Siemenstrasse 2, Villach, Austria ¹Infineon Technologies AG, Am Campeon 1, Neubiberg, Germany ²University of Twente, Drienerlolaan 5, NB Enschede, The Netherlands DOI: 10.1109/ICMTS55420.2023.10094167 ABSTRACT: Fast electric transients can cause distributed effects inside trench MOSFETs possibly resulting in device failure. A new test structure to study those distributed effects, combined with a new Transmission-Line Pulse (TLP) setup, is presented. On-wafer TLP measurements are performed and combined with TCAD and SPICE simulations to predict the space and time evolution of the field plate potential during transients.	PDF Xplore
3.2	Measuring of parasitic resistance of stacked chip of Si power device T. Ohguro, H. Kojima, T. Hara, T. Nishiwaki¹, K. Kobayashi Toshiba Electronic Devices & Storage Corporation, 1-1, Iwauchi-Machi, Nomi, Ishikawa, Japan ¹Toshiba Electronic Devices & Storage Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan DOI: 10.1109/ICMTS55420.2023.10094137 ABSTRACT: Stacked chip of! Si power device is useful for both lower on-resistance and small packaged size for reduction of system size and high power efficiency. In this paper, some structures and procedure to measure parasitic resistance of the stacked chip are described.	PDF Xplore
3.3	New Extraction Method for Intrinsic Qrr of Power MOSFETs T. Hara, S. Nakajima, T. Ohguro, K. Miyashita Advanced Semiconductor Device Development Center, Toshiba Electronic Devices & Storage Corporation DOI: 10.1109/ICMTS55420.2023.10094069 ABSTRACT: We provide the method to estimate intrinsic Qrr ($Q_{r_{-}\text{int}})$ without parasitic inductance in the measurement system for the first time. In this paper, we analyze parasitic inductance dependence of Qrr by TCAD simulation and we propose the method for removing the parasitic inductance effect as well as calculating the carrier of recombination and discharge (qr_into).	PDF Xplore
3.4	On-Resistance Measurements of Low Voltage MOSFET at wafer level K. Oasa, T. Nishiwaki, T. Ohguro¹, Y. Saito, Y. Kawaguchi¹ Toshiba Electronic Devices & Storage Corporation, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan ¹Toshiba Electronic Devices & Storage Corporation, Iwauchi-Machi, Nomi, Ishikawa, 1-1, Japan DOI: 10.1109/ICMTS55420.2023.10094127 ABSTRACT: To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.	PDF Xplore
3.5	Comparative study on characteristics of GaN-based MIS-HEMTs with Al2O3 and Si3N4 gate insulators under Hot Carrier Degradation P. -Y. Wu, X. -Y. Tsai¹, T. -C. Chang², T. -M. Tsai, S. M. Sze¹ Pei-Yu Wu and Tsung-Ming Tsai are with the Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung, Taiwan ¹Xin-Ying Tsai and Simon M. Sze are with the Department of Electronics Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan. ²Ting-Chang Chang is with Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS55420.2023.10094072 ABSTRACT: In GaN-based metal-insulatorsemiconductor high electron mobility transistors (GaNbased MIS HEMTs), Al2O3/Si3N4 bilayer-gate insulator- MIS HEMTs (Al2O3/Si3N4-MIS HEMTs) are considered to have the advantages of low gate leakage and low interface defects. This study will compare Si3N4 gate insulator-MIS HEMTs (Si3N4-MIS HEMTs) to discuss and clarify the abnormal deterioration mechanism of Al2O3/Si3N4-MIS HEMTs under Hot Carrier Effect (HCE). Therefore, in this study, the results of HCE between Si3N4-MIS HEMTs and Al2O3/Si3N4-MIS HEMTs are compared, and the abnormal HCS degradations in Al2O3/Si3N4-MIS HEMTs are discussed and explained in depth. A series of electrical and simulation analysis is conducted in order to verify the degradation mechanism model proposed in this study.	PDF Xplore

Session 4: Measurement Technique

4.1	The Pressing Probe Needle Technique for Characterizing Mechanical Stress Sensitivity of Semiconductor Devices H. Tuinhout, O. Dieball NXP Semiconductors, Eindhoven, The Netherlands DOI: 10.1109/ICMTS55420.2023.10094063 ABSTRACT: This paper discusses the so called Pressing Probe Needle (PPN) technique for characterizing out-of-plane mechanical stress sensitivity of arbitrary semiconductor devices, implemented on a standard parametric test system. By utilizing a motorized probe positioner and a force calibrated standard tungsten parametric probe needle, this fast and highspatial-resolution technique provides valuable insights into mechanical stress effects of process and device layout options. Such results are highly beneficial for high-precision analog circuit design and layout optimization.	PDF Xplore
4.2	A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact Y. -L. Chen, S. -H. Lai, J. -H. Lin, B. -Y. Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS55420.2023.10094097 ABSTRACT: A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure is proposed to characterize the Ti-Al alloy/p-type 4H-SiC contact. It is confirmed that the test structure can judge the uniformity of the contact interface without destructive analysis such as cross-sectional transmission electron microscopy. Comparing with the results of singlecontact CBKR structure, it is observed that the contact interface is non-uniform and the formation of low resistivity interface depends on the contact area. This area-dependence issue should be solved in order to improve the SiC power devices and CMOS ICs.	PDF Xplore
4.3	Test Structure for Evaluation of Pad Size for Wafer Probing B. Smith, D. Hall, G. Tranquillo¹ NXP Semiconductors, Austin, TX, USA ¹Celadon Systems, Inc., Burnsville, MN, USA DOI: 10.1109/ICMTS55420.2023.10094145 ABSTRACT: A new, cage-like structure is presented and is shown to be able to electrically identify a probe needle that has fallen slightly off its probe pad, even when the standard probe resistance structure (pads shorted together) reports “good” probe resistance. Using both structures together enables a more accurate evaluation of a probe system’s capabilities. Both test structures were used to compare three types of probe cards, reporting the smallest probe pad size that provides 100& probe yield.	PDF Xplore
4.4	Test Bench for Biopotential Instrumentation Amplifier using Single-Ended to Differential Amplifiers S. Thanapitak, P. Sedtheetorn, P. Chanyagorn, T. Chulajata, S. Bhatranand, P. Phattanasri Department of Electrical Engineering, Faculty of Engineering, Mahidol University, Nakhon Pathom, Thailand DOI: 10.1109/ICMTS55420.2023.10094130 ABSTRACT: A practical test bench for dry electrode bio-signal instrumentation amplifier is presented and demonstrated. By modifying the on-the-shelf single-ended to differential amplifier, the common-mode rejection ratio and distortion under electrodes offset scenario can be characterized. The other essential parameters such as input impedance and power supply rejection ratio can also be determined.	PDF Xplore

Session 5: Matching and Variability

5.1	Measurement of Temperature Effect on Comparator Offset Voltage Variation Y. Iwata, T. Kitamura, M. Islam Department of Electrical Engineering, Graduate School of Engineering, Kyoto University Kyoto Daigaku Katsura, Nishikyo-ku, Kyoto, JAPAN DOI: 10.1109/ICMTS55420.2023.10094194 ABSTRACT: Comparator offset voltage often limits the perfor-mance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100o C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100o C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures.	PDF Xplore
5.2	Variability of MOSFET Series Resistance Extracted from Individual Devices: Is Direct Variability Measurement Possible? K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS55420.2023.10094106 ABSTRACT: Source-to-drain series resistance (RSD) of a large number of identically designed MOSFETs was extracted using a recently proposed single-device method. By examining statistical correlations with other device parameters, it was confirmed that variability of the extracted RSD values does not correspond to real series resistance variability, but is mainly caused by some non- RSD variability sources. This suggests that, for the single-device method to work, non- RSD variability needs to be reduced by averaging multiple devices, or using wide channel devices.	PDF Xplore
5.3	Variability Evaluation of MOS-gated PNPN Diode for Hardware Spiking Neural Network T. Takada, T. Mori, J. Ida Division of Electrical Engineering, Kanazawa Institute of Technology, Ishikawa, Japan DOI: 10.1109/ICMTS55420.2023.10094054 ABSTRACT: The variability of the neuronal function device of a metal oxide semiconductor-gated PNPN diode was evaluated. The variability of neurons is known to affect the inference accuracy of spiking neural networks (SNNs). The device has stochastic operation on its own, and the spike frequency can be controlled by the gate voltage, which has the possibility to improve the accuracy of SNNs.	PDF Xplore
5.4	Effect of Quadruple Size Transistor on SRAM Physically Unclonable Function Stabilized by Hot Carrier Injection S. Xu, K. Liu¹, Y. Tang, R. Zhang, H. Shinohara¹ Information, Production and Systems Research Center, Waseda University, Kitakyushu, Japan ¹Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan DOI: 10.1109/ICMTS55420.2023.10094187 ABSTRACT: This article presents a bitcell of a static randomaccess memory (SRAM)-based physically unclonable function (PUF) with quadruple-size transistor, which reduces the tail’ of mismatch distribution after hot carrier injection (HCI) burn-in. A statistical mismatch distribution model after HCI application for a certain time is proposed by combining native mismatch distribution before HCI and mismatch shift distribution after HCI. Model calculation shows that quadruple-size transistor SRAM PUF needs 15-min HCI burn-in time to achieve cryptographic level requirement, which is more than 3 times shorter than normal-size transistor SRAM PUF of 46-min. The effect of utilizing the quadruple-size transistor with respect to HCI burn-in for stability reinforcement is also confirmed by measuring chips fabricated in a 130-nm CMOS process. Experimental results show that the ‘tail’ in mismatch distribution is significantly eliminated after 18-min HCI burnin time of quadruple-size transistor SRAM PUF, which meets our expectations. The presented statistical model also matches the measurement data well.	PDF Xplore

Session 6: Yield and Device Optimization

6.1	Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications H. -C. Hong, L. -Y. Lin, B. -C. Chen¹ Institute of Electrical and Computer Engineering ¹Institute of Electrical and Control Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS55420.2023.10094078 ABSTRACT: Computing-in-memory (CIM) is a promising technique for energy-efficiently conducting the massive amount of required multiply-and-accumulate (MAC) calculations in neural networks (NNs). The read-decoupled 8T (RD8T) SRAM cell is popular in the CIM designs because of being read disturbance free. However, local process variations may lead significant errors to the CIM results. This work proposes an accurate on-chip test circuit design for characterizing the output current of every RD8T SRAM cell in a 8-kb RD8T SRAM array fabricated in 90nm CMOS. The experimental results show the detailed and accurate spatial distribution of the RD8T cells which helps optimize the CIM circuit design.	PDF Xplore
6.2	Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation V. Vidya, N. Zamdmer, T. Mechler, K. Onishi, D. Chidambarrao, B. W. Jeong¹, Y. G. Ko¹, C. H. Lee, J. Sim, M. Angyal, E. Crabbe IBM Systems, IBM Corp, 2070 Route 52, B300-A, Hopewell Junction, NY, USA ¹Samsung Electronics Co. Ltd, San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, Republic of Korea DOI: 10.1109/ICMTS55420.2023.10094206 ABSTRACT: This paper presents two phenomena captured by product-like analog layout design of experiments (DOEs) that are otherwise difficult to capture in foundry baseline test structures. Such product driven test structures are critical for early detection of yield detractors and robustly validating a technology in a fabless design environment.	PDF Xplore
6.3	An Electrical Inline-Testable Structure to Monitor Gate-Source/Drain Short Defect Caused by Imperfect Fin-Cut Patterning in FinFET Technology H. Zhu, K. Onishi, S. Wu, A. Yang, B. -W. Jeong¹, S. -J. Lim¹, N. Jing, C. -H. Lee, D. Conrady, D. Chidambarrao IBM Infrastructure, IBM Corp, 2070 Rt 52, B300A, Hopewell Junction, NY, USA ¹Samsung Electronics Co. Ltd., San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, Republic of Korea DOI: 10.1109/ICMTS55420.2023.10094149 ABSTRACT: On semiconductor IC chips, non-functional test structures are often designed along with the functional circuits in order to monitor the process quality even when the wafers are running in the line. This paper introduces an inline electrical test structure to monitor a systematic gate-source/drain short defect that degrades chip product yield. This area efficient, test time friendly, and insightful test structure is ideal to monitor process quality for the forementioned failure mode and help with the diagnosis of chip functional failures.	PDF Xplore
6.4	Wafer Level Reliability Monitoring of NBTI Using Polysilicon Heater Structures for Production Measurements Y. -H. Cheng Central Engineering, onsemi, East Greenwich, 1900 South County Trail, USA DOI: 10.1109/ICMTS55420.2023.10094064 ABSTRACT: The use of polysilicon heater structures provides a useful tool for fast NBTI monitoring of wafer level reliability in production measurements. It could reduce device relaxation in NBTI measurement without special ultra-fast test equipment. In this work NBTI characterization from a parametric tester using polysilicon heater test structures for 1.2V PMOS devices placed in the scribe line of a 65 nm BCD technology was performed with real-time feedback temperature control methodology without changing the chuck temperature to realize NBTI reliability assessment with a short test time.	PDF Xplore

Session 7: MEMs and Sensors

7.1	Application of Greek cross structures for process development of electrochemical sensors M. Zhang, S. Zhang, C. Dunare, J. R. K. Marland, J. G. Terry, S. Smith School of Engineering, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS55420.2023.10094096 ABSTRACT: Using a test structure chip designed to assist in process development for reference electrode fabrication for integrated electrochemical sensors, this paper reports measurements of Greek cross test structures and compares them to measurements of bridge resistor structures on the same chip. The correct application of these structures requires careful consideration of the measurement parameters to provide accurate results and different force current values have been investigated. Results from platinum structures suggest there is measureable variation in the feature size when Greek cross results are used to extract electrical critical dimension from the bridge resistor measurements. Similar measurements of silver structures were less conclusive. While the bridge structures show a significant effect of oxidation of silver which has been exposed to air since fabrication, the Greek cross results are highly variable and may not be reliable.	PDF Xplore
7.2	Test Structures for Studying Coplanar Reverse- Electrowetting for Vibration Sensing and Energy Harvesting A. Moyo, M. W. Shahzad, J. G. Terry¹, S. Smith¹, Y. Mita², Y. Li Department of Mechanical and Construction Engineering, Faculty of Engineering and Environment, Northumbria University, Newcastle upon Tyne, UK ¹School of Engineering,Institute for Integrated Micro and Nano Systems,The University of Edinburgh, Edinburgh, UK ²Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS55420.2023.10094057 ABSTRACT: Reverse electrowetting on dielectric (REWOD) has emerged to be a promising energy harvesting technology from low frequency vibrations. This study aims to use test structures to characterize a unique form of REWOD using a coplanar electrode configuration. This configuration allows for better versatility in system integration, device packaging and applications.	PDF Xplore
7.3	Damage Assessment Structure of Thermal-Annealing Post-Processing on CMOS LSIs Y. Okamoto, N. Makimoto, K. Misumi¹, T. Kobayashi, Y. Mita¹, M. Ichiki Sensing System Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan ¹School of Electrical Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS55420.2023.10094159 ABSTRACT: We assessed the degradation of MOSFET and CMOS LSI circuit characteristics induced by the high temperature annealing, especially for the PZT deposition process. The test structure consists of ring oscillators having different numbers of stages and single PMOSFETs and NMOEFETs designed with $0.6 \mu \mathrm{m}$ CMOS technology. We observed the ring oscillator (RO) oscillating frequencies and the $I_{\mathrm{d}}-V_{\mathrm{g}}$ characteristics of the MOSFETs before and after the annealing post-process. The result indicated that such an annealing process involving high temperatures of around 575°C is possible unless the wiring on the CMOS components is mechanically broken. In addition, annealing temperature affected the MOSFET characteristics more than annealing times. Therefore, the effects of the CMOSMEMS monolithic integration using PZT thin films be optimized using the proposed test structures.	PDF Xplore
7.4	Improving Performance of FBARs by Advanced Low-Temperature High-Pressure Technology Y. -F. Tu, T. -C. Chang¹, K. -J. Zhou¹, W. -C. Hung¹, T. -T. Kuo², C. -H. Lien Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan ¹Department of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan ²Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS55420.2023.10094148 ABSTRACT: In this study, a unique supercritical fluid (SCF) treatment is utilized to improve the resonance properties of thin film bulk acoustic resonators (FBARs) composed of a piezoelectric material of AlN. In an etching process of the sacrificial oxide, FBARs suffered from severe surface tension of etching acid solvent, resulting in structural bonding and residues generation. These impact on FABR’s structural integrity would influence its resonance properties. Therefore, a SCF treatment with low surface tension and high penetrability can effectively carry out residues from the release gap in a FBAR, observed from SEM images. The results show that the reflection coefficient, the quality factor, and the effective coupling coefficient are all improved in FABRs.	PDF Xplore
7.5	Solderable Multisided Metal Patterns Enables 3D Integrable Direct Laser Written Polymer MEMS L. Ivy, A. Lal The SonicMEMS Laboratory, School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA DOI: 10.1109/ICMTS55420.2023.10094101 ABSTRACT: Advancing highly integrated micro sensors and actuators calls for the ability to scale down three-dimensional structures while ensuring efficient electrical interconnectivity. This necessitates addressing a pressing need to develop novel techniques for shrinking components and facilitating seamless interconnectivity to the miniature structures. Here, we demonstrate a three-step fabrication method to produce 3D prints fabricated by direct laser writing (DLW) via two-photon polymerization (TPP), with multisided evaporated metal patterns. The three steps consist of printing the core structure and shadow mask shell (SMS) on sacrificial Dextran 70, evaporating metal onto the desired side(s), and then releasing the core and SMS in water. To showcase this process’ capabilities, we produced a simple characterization structure featuring two electrical vias, an out-of-plane serpentine resistor, and four solderable electrodes. With this test structure, three firsts were achieved for the TPP community: (1) The deposition of metal patterns onto opposing sides of a DLW structure; (2) the flip-chip soldering of said structure to a PCB; and (3) the verification of electrical continuity through its two microvias.	PDF Xplore

Session 8: Modeling

8.1	Accurate Gate Charge Modeling of HV LDMOS Transistors for Power Circuit Applications X. Jie, R. v. Langevelde, K. Xia¹, L. Chao, C. C. McAndrew, Q. Zhang, M. Bacchi², W. Li NXP Semiconductors, Front End Innovation ¹TSMC, Special Technology Product Engineering ²NXP Semiconductors, Business Line Advanced Analog DOI: 10.1109/ICMTS55420.2023.10094091 ABSTRACT: Accurate modeling of the gate-drain capacitance Cgd for HV LDMOS transistors is important but is challenging because of its strong bias dependence. We present an improved Cgd model, based on the physics that the drift region under the poly-gate is fully depleted at high Vdg, and validate our model against gate charge measurements for both n-and p-type 90V LDMOS transistors.	PDF Xplore
8.2	Introducing Transfer Learning Framework on Device Modeling by Machine Learning K. Niiyama, H. Awano, T. Sato Graduate School of Informatics, Kyoto University Yoshida-hommachi, Kyoto, Sakyo, Japan DOI: 10.1109/ICMTS55420.2023.10094067 ABSTRACT: In this study, we propose a novel transistor modeling method using machine learning techniques, with a focus on extrapolation performance. Our method leverages knowledge from a base model that is related to the target model, instead of relying solely on device-specific information. The results show that our approach outperforms other transistor modeling methods based on machine learning, particularly in modeling similar but different transistors that belong to the same device family. Our method was able to reduce the root mean squared error (RMSE) by up to 80.0% compared to other methods.	PDF Xplore
8.3	Technology-Dependent Modeling of MOSFET Parasitic Capacitances for Circuit Simulation D. Navarro, C. Tanaka, K. Adachi¹, T. Naito, K. Tada, A. Hokazono Memory Division, KIOXIA Corporation, Yokohama, Japan ¹KIOXIA Corporation, Institute of Memory Technology Research and Development, Yokohama, Japan DOI: 10.1109/ICMTS55420.2023.10094071 ABSTRACT: Models for parasitic capacitances in the MOSFET overlap region are developed for circuit simulation. In particular, the overlap capacitance ($C_{\mathrm{o}\mathrm{v}}$) model considers the modulation of the overlap length due to the dynamic depletion of channel/LDDjunction, which is the physical origin of the $C_{\mathrm{o}\mathrm{v}}$ bias-dependence. The models are implemented in Verilog-A, and incorporated in a MOSFET model for circuit simulation. Reproduction of device simulation results and RF-CMOS gatedrain capacitance measurements are verified.	PDF Xplore

Session 9: Novel Materials

9.1	Bridging Large-Signal and Small-Signal Responses of Hafnium-Based Ferroelectric Tunnel Junctions M. Massarotto, M. Segatto, F. Driussi, A. Affanni, S. Lancaster¹, S. Slesazeck¹, T. Mikolajick¹, D. Esseni DPIA, University of Udine Udine, Italy ¹NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS55420.2023.10094178 ABSTRACT: Ferroelectric Tunnel Junctions (FTJs) operating as memristors are promising electron devices to realize artificial synapses for neuromorphic computing. But the understanding of their operation requires an in-depth electrical characterization. In this work, an inhouse experimental setup is employed along with novel experimental methodologies to investigate the largesignal (LS) and small-signal (AC) responses of FTJs. For the first time, our experiments and physics-based simulations help to explain the discrepancies between LS and AC experiments reported in previous literature.	PDF Xplore
9.2	Demonstration of frequency doubler application using ZnO-DNTT anti-ambipolar switch device Y. Lee, H. J. Hwang, B. H. Lee Department of Electrical Engineering, Center for Semiconductor Technology Convergence, Pohang University of Science and Technology, Pohang, Gyeongbuk, Republic of Korea DOI: 10.1109/ICMTS55420.2023.10094079 ABSTRACT: This paper presents the demonstration of an antiambipolar switch (AAS) using a ZnO-dinaphtho[2,3-$b: 2^{\prime}, 3^{\prime}$ ' $f]$ thieno $[3,2-b]$ thiophene (DNTT) heterojunction structure. The proper combination of n-and p-type thin-film semiconductors achieved a high peak-to-valley ratio of $\sim 10^{5}$ at a low process temperature compatible with the back-end-of-line process. Using the electrical characteristic of positive-to-negative transconductance switching at the peak current point, a frequency doubler was implemented with only one device. The excellent electrical performance of the ZnO-DNTT AAS device resulted in a high conversion gain of $-5 \mathrm{~dB}$ and an output frequency purity of 97 %.	PDF Xplore
9.3	Identifying nano-Schottky diode currents in silicon diodes with 2D interfacial layers T. Knežević, L. K. Nanver¹ Ruđer Bošković Institute, Zagreb, Croatia ¹MESA+ Institute of Nanotechnology, University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS55420.2023.10094164 ABSTRACT: In silicon technology, Schottky diodes mainly exhibit high current levels, and attempts are regularly made to reduce these by introducing 2D layers between the metal contact and the silicon. Defects in such interfacial layers, from weakly bonded structures to actual pinholes, can lead to high, localized metal-semiconductor Schottky currents. Using the example of diodes with an interfacial layer of pure boron (PureB) between an aluminum metallization layer and the Si, a signature for such ‘‘nano-Schottky’s’’ is determined by evaluating the results of several different test-structure arrays and measurement techniques. An adapted bipolar-type measurement is introduced as an additional method to determine whether any high current characteristics originate from a low Schottky barrier height over the entire diode surface or from a localized nano-Schottky structure.	PDF Xplore

By First Author

4.2	A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact Y. -L. Chen, S. -H. Lai, J. -H. Lin, B. -Y. Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS55420.2023.10094097 HOVER FOR ABSTRACT	PDF Xplore
6.4	Wafer Level Reliability Monitoring of NBTI Using Polysilicon Heater Structures for Production Measurements Y. -H. Cheng Central Engineering, onsemi, East Greenwich, 1900 South County Trail, USA DOI: 10.1109/ICMTS55420.2023.10094064 HOVER FOR ABSTRACT	PDF Xplore
2.1	Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure O. Gauthier, S. Haendler, R. Beucher, P. Scheer, Q. Rafhay¹, C. Theodorou¹ STMicroelectronics, Crolles, France ¹Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP, IMEP-LAHC, Grenoble, France DOI: 10.1109/ICMTS55420.2023.10094087 HOVER FOR ABSTRACT	PDF Xplore
1.2	Test Methodology Development for Investigating CeRAM at Elevated Temperatures A. A. Gruszecki, R. Prasad, S. V. Suryavanshi¹, G. Yeric¹, C. D. Young Electrical and Computer Engineering Department, The University of Texas at Dallas, Richardson, Texas, USA ¹Cerfe Labs, Austin, Texas, USA DOI: 10.1109/ICMTS55420.2023.10094065 HOVER FOR ABSTRACT	PDF Xplore
3.3	New Extraction Method for Intrinsic Qrr of Power MOSFETs T. Hara, S. Nakajima, T. Ohguro, K. Miyashita Advanced Semiconductor Device Development Center, Toshiba Electronic Devices & Storage Corporation DOI: 10.1109/ICMTS55420.2023.10094069 HOVER FOR ABSTRACT	PDF Xplore
6.1	Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications H. -C. Hong, L. -Y. Lin, B. -C. Chen¹ Institute of Electrical and Computer Engineering ¹Institute of Electrical and Control Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS55420.2023.10094078 HOVER FOR ABSTRACT	PDF Xplore
7.5	Solderable Multisided Metal Patterns Enables 3D Integrable Direct Laser Written Polymer MEMS L. Ivy, A. Lal The SonicMEMS Laboratory, School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA DOI: 10.1109/ICMTS55420.2023.10094101 HOVER FOR ABSTRACT	PDF Xplore
5.1	Measurement of Temperature Effect on Comparator Offset Voltage Variation Y. Iwata, T. Kitamura, M. Islam Department of Electrical Engineering, Graduate School of Engineering, Kyoto University Kyoto Daigaku Katsura, Nishikyo-ku, Kyoto, JAPAN DOI: 10.1109/ICMTS55420.2023.10094194 HOVER FOR ABSTRACT	PDF Xplore
8.1	Accurate Gate Charge Modeling of HV LDMOS Transistors for Power Circuit Applications X. Jie, R. v. Langevelde, K. Xia¹, L. Chao, C. C. McAndrew, Q. Zhang, M. Bacchi², W. Li NXP Semiconductors, Front End Innovation ¹TSMC, Special Technology Product Engineering ²NXP Semiconductors, Business Line Advanced Analog DOI: 10.1109/ICMTS55420.2023.10094091 HOVER FOR ABSTRACT	PDF Xplore
9.3	Identifying nano-Schottky diode currents in silicon diodes with 2D interfacial layers T. Knežević, L. K. Nanver¹ Ruđer Bošković Institute, Zagreb, Croatia ¹MESA+ Institute of Nanotechnology, University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS55420.2023.10094164 HOVER FOR ABSTRACT	PDF Xplore
2.2	An Extended Method to Analyze Boron Diffusion Defects in 16 nm Node High-Voltage FinFETs T. -T. Kuo, Y. -C. Chen, T. -C. Chang¹, F. -M. Ciou², C. -H. Yeh³, P. -H. Chen⁴, S. M. Sze⁵ Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan ¹Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, Taiwan ²Department of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan ³Department of Photonics, National Sun Yat-sen University, Kaohsiung, Taiwan. ⁴Department of Applied Science, R. O. C. Naval Academy, Kaohsiung, Taiwan ⁵National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS55420.2023.10094125 HOVER FOR ABSTRACT	PDF Xplore
1.1	Discrete current limiting circuit for emerging memory programming L. Laborie, P. Trotti, K. Veyret, C. Cagli¹ Univ. Grenoble Alpes,CEA, Leti, Grenoble, France ¹STMicroelectronics, Grenoble, France DOI: 10.1109/ICMTS55420.2023.10094099 HOVER FOR ABSTRACT	PDF Xplore
9.2	Demonstration of frequency doubler application using ZnO-DNTT anti-ambipolar switch device Y. Lee, H. J. Hwang, B. H. Lee Department of Electrical Engineering, Center for Semiconductor Technology Convergence, Pohang University of Science and Technology, Pohang, Gyeongbuk, Republic of Korea DOI: 10.1109/ICMTS55420.2023.10094079 HOVER FOR ABSTRACT	PDF Xplore
1.5	Analysis of Critical Schottky Distance Effect and Distributed Set Voltage in HfO2-based 1T-1R Device S. -K. Lin, T. -C. Chang¹, W. -C. Huang¹, Y. -F. Tan², C. -H. Lien Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan ¹Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan ²Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS55420.2023.10094175 HOVER FOR ABSTRACT	PDF Xplore
2.3	VSS-Bias-Based Measurement of Random Telegraph Noise in Hybrid SRAM PUF after Hot Carrier Injection Burn-in K. Liu, Y. Tang, S. Xu, H. Shinohara Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan DOI: 10.1109/ICMTS55420.2023.10094138 HOVER FOR ABSTRACT	PDF Xplore
9.1	Bridging Large-Signal and Small-Signal Responses of Hafnium-Based Ferroelectric Tunnel Junctions M. Massarotto, M. Segatto, F. Driussi, A. Affanni, S. Lancaster¹, S. Slesazeck¹, T. Mikolajick¹, D. Esseni DPIA, University of Udine Udine, Italy ¹NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS55420.2023.10094178 HOVER FOR ABSTRACT	PDF Xplore
1	How to Make a Better Abstract Y. Mita The University of Tokyo, Tokyo, Japan HOVER FOR ABSTRACT
7.2	Test Structures for Studying Coplanar Reverse- Electrowetting for Vibration Sensing and Energy Harvesting A. Moyo, M. W. Shahzad, J. G. Terry¹, S. Smith¹, Y. Mita², Y. Li Department of Mechanical and Construction Engineering, Faculty of Engineering and Environment, Northumbria University, Newcastle upon Tyne, UK ¹School of Engineering,Institute for Integrated Micro and Nano Systems,The University of Edinburgh, Edinburgh, UK ²Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS55420.2023.10094057 HOVER FOR ABSTRACT	PDF Xplore
8.3	Technology-Dependent Modeling of MOSFET Parasitic Capacitances for Circuit Simulation D. Navarro, C. Tanaka, K. Adachi¹, T. Naito, K. Tada, A. Hokazono Memory Division, KIOXIA Corporation, Yokohama, Japan ¹KIOXIA Corporation, Institute of Memory Technology Research and Development, Yokohama, Japan DOI: 10.1109/ICMTS55420.2023.10094071 HOVER FOR ABSTRACT	PDF Xplore
8.2	Introducing Transfer Learning Framework on Device Modeling by Machine Learning K. Niiyama, H. Awano, T. Sato Graduate School of Informatics, Kyoto University Yoshida-hommachi, Kyoto, Sakyo, Japan DOI: 10.1109/ICMTS55420.2023.10094067 HOVER FOR ABSTRACT	PDF Xplore
3.4	On-Resistance Measurements of Low Voltage MOSFET at wafer level K. Oasa, T. Nishiwaki, T. Ohguro¹, Y. Saito, Y. Kawaguchi¹ Toshiba Electronic Devices & Storage Corporation, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan ¹Toshiba Electronic Devices & Storage Corporation, Iwauchi-Machi, Nomi, Ishikawa, 1-1, Japan DOI: 10.1109/ICMTS55420.2023.10094127 HOVER FOR ABSTRACT	PDF Xplore
3.2	Measuring of parasitic resistance of stacked chip of Si power device T. Ohguro, H. Kojima, T. Hara, T. Nishiwaki¹, K. Kobayashi Toshiba Electronic Devices & Storage Corporation, 1-1, Iwauchi-Machi, Nomi, Ishikawa, Japan ¹Toshiba Electronic Devices & Storage Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan DOI: 10.1109/ICMTS55420.2023.10094137 HOVER FOR ABSTRACT	PDF Xplore
7.3	Damage Assessment Structure of Thermal-Annealing Post-Processing on CMOS LSIs Y. Okamoto, N. Makimoto, K. Misumi¹, T. Kobayashi, Y. Mita¹, M. Ichiki Sensing System Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan ¹School of Electrical Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS55420.2023.10094159 HOVER FOR ABSTRACT	PDF Xplore
1.4	Automated RRAM measurements using a semi-automated probe station and ArC ONE interface A. G. Panca, A. Serb, S. Stathopoulos, S. K. Garlapati¹, T. Prodromakis Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh, UK ¹Materials Science And Metallurgical Engineering, Indian Institute of Technology Hyderabad, Telangana, India DOI: 10.1109/ICMTS55420.2023.10094156 HOVER FOR ABSTRACT	PDF Xplore
2	Making Good Presentations B. Smith NXP Semiconductors HOVER FOR ABSTRACT
4.3	Test Structure for Evaluation of Pad Size for Wafer Probing B. Smith, D. Hall, G. Tranquillo¹ NXP Semiconductors, Austin, TX, USA ¹Celadon Systems, Inc., Burnsville, MN, USA DOI: 10.1109/ICMTS55420.2023.10094145 HOVER FOR ABSTRACT	PDF Xplore
5.3	Variability Evaluation of MOS-gated PNPN Diode for Hardware Spiking Neural Network T. Takada, T. Mori, J. Ida Division of Electrical Engineering, Kanazawa Institute of Technology, Ishikawa, Japan DOI: 10.1109/ICMTS55420.2023.10094054 HOVER FOR ABSTRACT	PDF Xplore
5.2	Variability of MOSFET Series Resistance Extracted from Individual Devices: Is Direct Variability Measurement Possible? K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS55420.2023.10094106 HOVER FOR ABSTRACT	PDF Xplore
3.1	Distributed field plate effects in split-gate trench MOSFETs R. Tambone, A. Ferrara, F. Magrini¹, A. Hoffmann¹, A. Wood, G. Noebauer, E. Gondro¹, R. J. E. Hueting² Infineon Technologies Austria AG, Siemenstrasse 2, Villach, Austria ¹Infineon Technologies AG, Am Campeon 1, Neubiberg, Germany ²University of Twente, Drienerlolaan 5, NB Enschede, The Netherlands DOI: 10.1109/ICMTS55420.2023.10094167 HOVER FOR ABSTRACT	PDF Xplore
4.4	Test Bench for Biopotential Instrumentation Amplifier using Single-Ended to Differential Amplifiers S. Thanapitak, P. Sedtheetorn, P. Chanyagorn, T. Chulajata, S. Bhatranand, P. Phattanasri Department of Electrical Engineering, Faculty of Engineering, Mahidol University, Nakhon Pathom, Thailand DOI: 10.1109/ICMTS55420.2023.10094130 HOVER FOR ABSTRACT	PDF Xplore
7.4	Improving Performance of FBARs by Advanced Low-Temperature High-Pressure Technology Y. -F. Tu, T. -C. Chang¹, K. -J. Zhou¹, W. -C. Hung¹, T. -T. Kuo², C. -H. Lien Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan ¹Department of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan ²Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS55420.2023.10094148 HOVER FOR ABSTRACT	PDF Xplore
4.1	The Pressing Probe Needle Technique for Characterizing Mechanical Stress Sensitivity of Semiconductor Devices H. Tuinhout, O. Dieball NXP Semiconductors, Eindhoven, The Netherlands DOI: 10.1109/ICMTS55420.2023.10094063 HOVER FOR ABSTRACT	PDF Xplore
6.2	Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation V. Vidya, N. Zamdmer, T. Mechler, K. Onishi, D. Chidambarrao, B. W. Jeong¹, Y. G. Ko¹, C. H. Lee, J. Sim, M. Angyal, E. Crabbe IBM Systems, IBM Corp, 2070 Route 52, B300-A, Hopewell Junction, NY, USA ¹Samsung Electronics Co. Ltd, San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, Republic of Korea DOI: 10.1109/ICMTS55420.2023.10094206 HOVER FOR ABSTRACT	PDF Xplore
3.5	Comparative study on characteristics of GaN-based MIS-HEMTs with Al2O3 and Si3N4 gate insulators under Hot Carrier Degradation P. -Y. Wu, X. -Y. Tsai¹, T. -C. Chang², T. -M. Tsai, S. M. Sze¹ Pei-Yu Wu and Tsung-Ming Tsai are with the Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung, Taiwan ¹Xin-Ying Tsai and Simon M. Sze are with the Department of Electronics Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan. ²Ting-Chang Chang is with Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS55420.2023.10094072 HOVER FOR ABSTRACT	PDF Xplore
5.4	Effect of Quadruple Size Transistor on SRAM Physically Unclonable Function Stabilized by Hot Carrier Injection S. Xu, K. Liu¹, Y. Tang, R. Zhang, H. Shinohara¹ Information, Production and Systems Research Center, Waseda University, Kitakyushu, Japan ¹Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan DOI: 10.1109/ICMTS55420.2023.10094187 HOVER FOR ABSTRACT	PDF Xplore
1.3	Real-time electrical measurements during laser attack on STT-MRAM N. Yazigy, J. Postel-Pellerin, V. D. Marca, R. C. Sousa¹, A. -L. Ribotta², G. D. Pendina¹, P. Canet IM2NP, CNRS, UMR 7334, 5 rue Enrico Fermi, Aix-Marseille Université, Marseille, France ¹CNRS, CEA, SPINTEC, SPINTEC, University Grenoble Alpes, Grenoble, France ²Mines Saint-Etienne, CEA, Leti, Centre CMP, Gardanne, France DOI: 10.1109/ICMTS55420.2023.10094166 HOVER FOR ABSTRACT	PDF Xplore
7.1	Application of Greek cross structures for process development of electrochemical sensors M. Zhang, S. Zhang, C. Dunare, J. R. K. Marland, J. G. Terry, S. Smith School of Engineering, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS55420.2023.10094096 HOVER FOR ABSTRACT	PDF Xplore
6.3	An Electrical Inline-Testable Structure to Monitor Gate-Source/Drain Short Defect Caused by Imperfect Fin-Cut Patterning in FinFET Technology H. Zhu, K. Onishi, S. Wu, A. Yang, B. -W. Jeong¹, S. -J. Lim¹, N. Jing, C. -H. Lee, D. Conrady, D. Chidambarrao IBM Infrastructure, IBM Corp, 2070 Rt 52, B300A, Hopewell Junction, NY, USA ¹Samsung Electronics Co. Ltd., San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, Republic of Korea DOI: 10.1109/ICMTS55420.2023.10094149 HOVER FOR ABSTRACT	PDF Xplore