IEEE International Conference on Microelectronic Test Structures

ICMTS 2019 Program

2019 Program Booklet

By Session

1	High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Field-Effect Transistors [Invited] Y. Koide Research Network and Facility Services Division, National Institute for Materials Science (NIMS), Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2019.8730974 ABSTRACT: Thanks to its excellent intrinsic properties, diamond is promising for applications of high-power electronic devices, ultraviolet detectors, biosensors, high-temperature tolerant gas sensors, etc. Here, an overview of high-k oxides on hydrogenated-diamond (H-diamond) for metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) is demonstrated. Fabrication routines for the H-diamond MOS capacitors and MOSFETs, band configurations of oxide/H-diamond heterointerfaces, and electrical properties of the MOS and MOSFETs are summarized and discussed. High-k oxide insulators are deposited using atomic layer deposition (ALD) and sputtering deposition (SD) techniques. Electrical properties of the H-diamond MOS capacitors with high-k oxides of ALD-Al2O3, ALD-HfO2,ALD-HfO2/ALD-Al2O3 multilayer, SD-HfO2/ALD-HfO2 bilayer, SD-TiO2/ALD-Al2O3 bilayer, and ALD TiO2/ALD-Al2O3 bilayer are discussed. Analyses for capacitance-voltage characteristics of them show that there are low fixed and trapped charge densities for the ALD-Al2O3/H -diamond and SD-HfO2/ALD-HfO2/H- diamond MOS capacitors. The k value of 27.2 for the ALD-TiO2/ALD-Al2O3 bilayer is larger than those of the other oxide insulators. Drain-source current versus voltage curves show distinct pitch-off and p-type channel characteristics for the ALD-Al2O3/H -diamond, SD- EfO2/ALD-HfO2/H-diamond, and ALD-TiO2/ALD- Al2O3/H-diamond MOSFETs. Understanding of fabrication routines and electrical properties for the high-k oxide/H-diamond MOS electronic devices is meaningful for the fabrication of high-performance H-diamond MOS capacitor and MOSFETs.	PDF Xplore
2	Taming Emerging Devices' Variation and Reliability Challenges with Architectural and System Solutions [Invited] Y. Wang, L. Shao, M. A. Lastras-Montaä±o¹, K. -T. Cheng² Department of Electrical and Computer Engineering, University of California, Santa Barbara, U.S.A. ¹FC, Universidad Autónoma de San Luis Potosä, México ²School of Engineering, Hong Kong University of Science and Technology, Hong Kong DOI: 10.1109/ICMTS.2019.8730924 ABSTRACT: Emerging devices are promising alternatives to traditional CMOS technologies as proposed in various solutions for future computation and communication systems. However, such devices often suffer from significant variations and relatively poor reliability. To address such limitations for their broader adoption, novel techniques at circuit, architecture, and system levels could help alleviate the device variation and reliability challenges. In this paper, we illustrate the effectiveness of such techniques in three distinct application domains, namely nonvolatile memories, flexible electronics, and silicon photonics-enabled optical interconnects.	PDF Xplore

Session 1: Photonic Test Structures

1.1	A Micro Racetrack Optical Resonator Test Structure to Optimize Pattern Approximation in Direct Lithography Technologies A. Higo, T. Sawamura, M. Fujiwara, E. Ota, A. Mizushima, E. Lebrasseur, T. Arakawa¹, Y. Mita² VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan ¹Faculty of Eng., Yokohama National University, Kanagawa, Japan ²Dept. of EEIS, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2019.8730981 ABSTRACT: High-throughput electron beam (EB) lithography technologies such as variable shape beam (VSB) and character projection (CP) are drawing much interests to the industries due to the wafer scale exposure capability and reduced exposure time in the order of magnitude. However, the tradeoff relationship of the exposure quality according to the EB exposure pattern approximation methods has not yet been comprehensively studied. The study is essential for photonics because target patterns include curved shapes. We propose a test structure of silicon racetrack resonator to quantify the quality dependence. Three approximation techniques were tried such as octagon shape CP, tilted square CPs, and thin variable shape rectangles. Optical measurement clearly revealed quality differences between methods, which were impossible to be identified by classical metrological methods including Surface Probe Microscopy (SPM).	PDF Xplore
1.2	PbS Quantum Dot / ZnO Nanowires Hybrid Test Structures for Infrared Photodetector H. Wang, A. Higo¹, Y. Mita², T. Kubo, H. Segawa Research Center for Advanced Science and Technology, The University. of Tokyo, Tokyo, Japan ¹VLSI Design and Education Research Center, The University of Tokyo, Tokyo, Japan ²Graduate School of Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2019.8730956 ABSTRACT: Aiming at developing infrared optoelectronic devices compatible with silicon-based large scale integration, we investigated performance of PbS colloidal quantum dot-silicon photodetectors using several different test structures. Silicon-based IR photo detector structures composed of PbS quantum dot/ZnO nanowire were investigated.	PDF Xplore
1.3	In search of a hole inversion layer in $\mathrm{Pd}/\mathrm{MoO}_{x}/\mathrm{Si}$ diodes through I- V characterization using dedicated ring-shaped test structures G. Gupta, S. D. Thammaiah, R. J. E. Hueting, L. K. Nanver MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS.2019.8730920 ABSTRACT: Palladium (Pd) capped molybdenum-oxide (MoOx) thin films deposited bye-beam evaporation on p- and n-type silicon (Si) substrates were investigated employing dedicated ring-shaped test structures. The results show diode characteristics on n-type Si with a high rectification of ~ 108 and a low leakage current of ~ 10-11 A and an ohmic contact on p-type Si, as expected from the reported high workfunction of MoOx. Reports in the literature that an inversion layer of holes should be present at the MoOx/n -Si interface were investigated via various DC electrical measurements on lateral test structures, but no indication of any significant inversion was found.	PDF Xplore
1.4	Wafer-Level Test Solution Development for a Quad-Channel Linear Driver Die in a 400G Silicon Photonics Transceiver Module Y. Wang, H. Ding, B. Blakely, A. Yan Department of Silicon Photonics Test Development, GLOBALFOUNDRIES, Essex Junction, VT, USA DOI: 10.1109/ICMTS.2019.8730947 ABSTRACT: In this paper, we demonstrate a wafer-level sorting test solution developed for quad-channel linear driver to be used in a 400G silicon photonics transceiver module. In-house built tester-on-a-board (TOB) system was used to provide power and control signals to the device-under-test (DUT), as well as conduct parametric tests. RF switch matrix was implemented to support multi-channel RF tests up to 50GHz. This wafer sorting test solution covers contact tests, power consumption tests, single-ended and true-mode differential full S-parameter tests, output signal swing and total harmonic tests. This work enables wafer-level driver die sorting capability for next-generation 400G silicon photonics coherent transceiver module.	PDF Xplore

Session 2: Yield and Reliability

2.1	Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive ring Oscillators R. Kishida, T. Asuke¹, J. Furuta¹, K. Kobayashil¹ Department of Electrical Engineering, Tokyo University of Science, Noda, Chiba, Japan ¹Department of Electronics, Kyoto Institute of Technology, Japan DOI: 10.1109/ICMTS.2019.8730967 ABSTRACT: Measuring bias temperature instability (BTI) by ring oscillators (ROs) is frequently used. However, the performance of a semiconductor chip is fluctuated dynamically due to bias, temperature and etc. BTI-sensitive and -insensitive ROs are implemented in order to extract BTI-induced degradation without temporal fluctuation factors. A test chip including those ROs was fabricated in a 65 nm process. BTI-induced degradation without temporal fluctuation was successfully measured by subtracting results of BTI-insensitive ROs from those of BTI-sensitive ones. Performance degradation of NMOS and PMOS transistors mainly due to BTI increases along logarithmic and exponential functions, respectively.	PDF Xplore
2.2	Extremely Low Voltage Operatable On-Chip- Monitor-Test Circuit for Plasma Induced Damage using High sensitivity Ring-VCO(Voltage Controlled Oscillator) M. Tomita, S. Mori, Y. Fukuzaki, K. Ogawa, S. Miyake, H. Ohnuma Sony Semiconductor Solutions Corporation, Kanagawa, Japan DOI: 10.1109/ICMTS.2019.8730985 ABSTRACT: We developed an on-chip-monitor-test circuit that measures Vth fluctuation caused by plasma induced damage (PID) during wafer process with using a novel ring voltage controlled oscillator (Ring- VCO) at low Vdd operation condition. The circuit can be easily implemented to conventional design and applied to product test. We have demonstrated that the circuit fabricated by 28nm process can monitor Vth fluctuation due to PID with operating voltage at 0.5V, which can be used for low power IoT products by 28nm CMOS technology and beyond.	PDF Xplore
2.3	Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions M. Jaoul, D. Ney¹, D. Céli¹, C. Maneux, T. Zimmer IMS, Université Bordeaux I, Talence, France ¹ST Microelectronics, Crolles, France DOI: 10.1109/ICMTS.2019.8730951 ABSTRACT: This paper presents an investigation of hot carrier degradation in advanced SiGe HBTs. This failure mechanism is observed under mixed mode stress conditions. Its physical location is examined through DC measurements from 2D transistors with different emitter width WE. TCAD simulations were performed to confirm its physical origin and location. The methodology permits to identify the origin of the degradation mechanism located at the emitter-base spacer interface. It is based on the scalable analysis of the DC characteristics measured after stressing the devices during 10 000s under mixed mode (MM) stress conditions. This study confirms the mechanism responsible of the MM degradation for SiGe HBTs.	PDF Xplore
5.2	Modeling and Test Structures for Accurate Current Sensing in Vertical Power FETs M. Chu, T. Harjono, K. Joardar, V. Krishnamurthy Advanced Technology Development, Texas Instruments, Dallas, TX DOI: 10.1109/ICMTS.2019.8730949 ABSTRACT: A new approach using a combination of analytical models, Spice simulations, and test structures is reported that allows for a comprehensive treatment of 3-dimensional (3D) distributed effects in vertical power FETs. This method leads to higher accuracy in current sensing as well as more cost effective design cycles.	PDF Xplore

Session 3: Novel Process Characterization

3.1	Electrical characterization of hot-wire assisted atomic layer deposited Tungsten films K. van der Zouw, A. A. I. Aarnink, J. Schmitz, A. Y. Kovalgin MESA+, University of Twente, Enschede, AE, The Netherlands DOI: 10.1109/ICMTS.2019.8730954 ABSTRACT: In this work, we applied conventional Van der Pauw and circular transmission line method (CTLM) test structures to determine the sheet and contact resistance of ultra-thin (1-10 nm) tungsten films grown by Hot-Wire assisted Atomic Layer Deposition, as well as their temperature coefficient of resistance (TCR). We finally explored the field effect (FE) in these layers. From fundamental point of view, it is important to explore the impact of film thickness on film's electrical behavior, whereas practically this knowledge is crucial for the existing and foreseen applications.	PDF Xplore
3.2	Continuity assessment for supercritical-fluids-deposited (SCFD) Cu film as electroplating seed layer N. Usami, E. Ota¹, A. Higo¹, T. Momose², Y. Mita¹ Tokyo Daigaku, Bunkyo-ku, Tokyo, JP ¹VLSI Design and Education Center (VDEC), The University of Tokyo ²Department of Material Engineering, The University of Tokyo DOI: 10.1109/ICMTS.2019.8730945 ABSTRACT: We evaluated supercritical fluid deposition (SCFD) copper thin films compatibility as a seed layer of electroplating processes. SCFD is an attractive technology for conformal metal coating on walls of high-aspect-ratio micro/nano structures (HARMS/HARNS), including trenches and holes. Therefore, it has a great potential for an electroplating seed layer. To utilize SCFD films as seed layers, we assessed the electrical and topological continuity of the SCFD films. The electrical measurements efficiently identified the suitability of various SCFD films for the electroplating process, which could not be achieved by microscope observation. The results have been cross-validated by atomic force microscopy.	PDF Xplore
3.3	Test Structures for Characterising the Silver Chlorination Process During Integrated Ag/AgCl Reference Electrode Fabrication C. Dunare, J. R. K. Marland, E. O. Blair¹, A. Tsiamis, F. Moorel, J. G. Terry, A. J. Walton, S. Smith School of Engineering, The University of Edinburgh, Edinburgh, UK ¹Department of Biomedical Engineering, University of Strathclyde, Glasgow, UK DOI: 10.1109/ICMTS.2019.8730966 ABSTRACT: Robust and repeatable processes are required to fabricate reference electrodes for micro-scale integrated electrochemical sensors. One method for this is to produce a “silver/silver chloride” (Ag/Agel) electrode through chemical chlorination of a thin film silver layer. This paper presents test structures, which can electrically characterise the process to aid process development and in-line control of the chlorination process.	PDF Xplore
3.4	Test structure to assess the useful extent of regular dummy devices around high-precision metal fringe capacitor arrays H. Tuinhout, I. Brunets, A. Z. -v. Duijnhoven NXP Semiconductors, Eindhoven, AE, The Netherlands DOI: 10.1109/ICMTS.2019.8730988 ABSTRACT: This paper discusses metal fringe capacitor matching test structures to characterize the impact of layer density disturbances at the edges of capacitor arrays. It is demonstrated that a seemingly minor pattern density disturbance can significantly affect the systematic mismatch in capacitor arrays up to well over 5 μm away from the array edges.	PDF Xplore

Session 4: Resistive Materials

4.1	Resistance Measurement Platform for Statistical Analysis of Next Generation Memory Materials T. Maeda, Y. Omura¹, A. Teramoto², R. Kuroda, T. Suwa², S. Sugawa² Graduate School of Engineering, Tohoku University, Sendai, Japan ¹School of Engineering, Tohoku University, Sendai, Japan ²New Industry Creation Hatchery Center, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS.2019.8730955 ABSTRACT: A newly developed resistance measurement platform is presented in this paper. The measurement platform consists of an array test circuit fabricated by a conventional 0.18 μm 1-Poly-Si 5-Metal layers CMOS technology, and a measurement target material formed on top of the 5M layer of the platform by an additional process. Using this platform, we can measure the resistance of various materials only by forming the measurement target layer and the top metal layer on the platform additionally. The resistance measurement operation was verified by measuring 234 poly-Si test resistor pre-formed by the poly-Si gate electrode layer in the array test circuit. Furthermore, 200 nm thick amorphous-Si layer was formed as a measurement target material on the platform and 490,700 cells were measured. The resistance measurement of 490,700 cells was conducted within 0.5 s with the resistance range of 500 Ω- 10 MΩ. We observed random telegraph noise (RTN) in some amorphous-Si cells. The developed platform is very useful for research and development of new memory materials, as well as for developing process, process equipment, and device structure to improve the reliability and performance of next generation memories.	PDF Xplore
4.2	Optimization of 3ω Method for Phase-Change Materials Thermal Conductivity Measurement at High Temperature A. L. Serra, G. Bourgeois, M. C. Cyrille, J. Cluzel, J. Garrione, G. Navarro, E. Nowak CEA, Univ. Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS.2019.8730993 ABSTRACT: Thermal conductivity (kth) of Ge-rich Ge-Sb-Te phase-change material (GGST) is here investigated at temperatures up to 400 °C through “3ω method”. We present the engineering of the test vehicle, with the optimization of the metal-based heater to achieve a reliable measurement even at high temperature. Finally, we compare the results from four different approaches, showing which method is more accurate for the kth evaluation in phase-change materials.	PDF Xplore
4.3	Evaluation of Truly Passive Crossbar Memory Arrays on Short Flow Characterization Vehicle Test Chips C. Hess, T. Brozek, H. Schneider, Y. Yu, M. Lunenborg, K. H. Ng, D. Ciplickas, R. Vallishayee, C. Dolainsky, L. H. Weiland PDF Solutions Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS.2019.8730984 ABSTRACT: More and more non volatile memory bit cell candidates are emerging which can be implemented between two metal layers in the BEOL process. Thus, short flow Characterization Vehicle® (CV®) Test Chips become beneficial for fast yield and endurance learning cycles. However, providing high observability of tail bits with ppm resolution requires access to more than just one bit cell per pad to be economically viable. Since, there are no FEOL switches available to address the bit cells we are evaluating truly Passive Crossbar Memory Arrays (PCMA) to significantly improve the bit per area ratio. Experimental results confirm successful memory operation based on fast parallel pulse testing. Design guidelines are presented to balance array size, signal to noise ratio, and test time.	PDF Xplore
4.4	Proposed one-dimensional passive array test circuit for parallel kelvin measurement with efficient area use M. Rerecich, C. D. Young¹ Samsung Austin Semiconductor, LLC, Austin, TX, USA ¹Materials Science and Engineering Department, University of Texas at Dallas, Dallas, TX, USA DOI: 10.1109/ICMTS.2019.8730948 ABSTRACT: A test structure and measurement method are proposed that permits measurement of several resistors in parallel using a kelvin method with only two independent pads per device. This technique allows rapid measurement of several different resistors with efficient area usage and a simple and adaptable circuit architecture.	PDF Xplore

Session 5: Power Devices

5.1	Vertical Bipolar Transistor Test Structure for Measuring Minority Carrier Lifetime in IGBTs K. Takeuchi, M. Fukui, T. Saraya, K. Itou, T. Takakura, S. Suzuki, Y. Numasawa¹, K. Kakushima², T. Hoshii², K. Furukawa², M. Watanabe², N. Shigyo², H. Wakabayashi², M. Tsukuda, A. Ogura¹, K. Tsutsui², H. Iwai², S. Nishizawa, I. Omura, H. Ohashi², T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan ¹Meiji University, Kawasaki, Japan ²Tokyo Institute of Technology, Yokohama, Japan DOI: 10.1109/ICMTS.2019.8730922 ABSTRACT: Vertical PNP bipolar transistor test structures were fabricated, which can be integrated on the same wafer with functional IGBTs. Common-base current gain was measured by applying zero voltage to the leaky back side junction, from which minority carrier lifetime in the base region was extracted. The structure makes it possible to measure the lifetime after a real IGBT fabrication process flow, and to correlate it with the characteristics of IGBTs on the same wafer.	PDF Xplore
5.3	A study on statistical parameter modeling of power MOSFET model by principal component analysis H. Tsukamoto, M. Shintani¹, T. Sato² Faculty of Engineering, Kyoto University, Kyoto, Japan ¹Graduate School of Science and Technology, Nara Institute of Science and Technology, Nara, Japan ²Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2019.8730946 ABSTRACT: In this paper, a set of dominant model parameters, which largely contributes characteristic variation of power MOSFETs, has been studied on the basis of statistical parameter extraction. Through the numerical analysis upon measured drain currents of a SiC power MOSFET, we demonstrate that the fluctuation of the current characteristics can be represented by a few random variables. In our example, threshold voltage and current scaling factor are identified particularly important to approximate the fluctuation of the current characteristics.	PDF Xplore

Session 6: Matching and Variability

6.1	Two-transistor Voltage-Measurement-Based Test Structure for Fast Extraction of MOS Mismatch Design Parameters J. P. M. Brito, S. Bampi¹ CEITEC S.A. Semiconductors, Porto Alegre, Brazil ¹Graduate Program on Microelectronics - PGMICRO, Federal University of of Rio Grande do Sul - UFRGS DOI: 10.1109/ICMTS.2019.8730918 ABSTRACT: This paper proposes a new test structure and a measurement method for measuring MOS transistors mismatches. The structure is based on the combination of two stacked MOS transistors and the measurement methodology relies on two single DC voltage measurements. The method allows to extract separately σ(ΔVTH) and σ(Δβ/β) and enables fast extraction of design MOS mismatch parameters such as AVTH and Aβ with less than 2% error. The simple data post-processing algorithm results in an increase of \pmb30x in the measurement speed with data correlation coefficient not less than 0.94 (R<sup>2</sup> ≥\pmb0.94). Rapid address decoding and bias configuration have been used in order to select each device in a two-dimensional (2D) DUT matrix of FETs. The experimental data presented herein for analysis is taken from measurements in a prototype fabricated in 65nm CMOS bulk process.	PDF Xplore
6.2	On-Chip Threshold Voltage Variability Detector Targeting Supply of Ring Oscillator for Characterizing Local Device Mismatch P. Jain, B. P. Das Department of ECE, Indian Institute of Technology, Roorkee, India DOI: 10.1109/ICMTS.2019.8730952 ABSTRACT: In this work, an all-digital on-chip threshold voltage variability detector is proposed to detect the local random threshold voltage variation from an array of device under test (DUTs). The use of single ring oscillator (RO) results in the compact structure of the proposed design. Any mismatch in the DUT is reflected as the change in the voltage of the sense node which is connected to the supply voltage of the RO. The difference of RO periods due to change in voltage level from VDD to (VDD-VTH) at the sense node actually represents the impact of threshold voltage of a DUT. The mismatch in threshold voltage of the DUTs can be modeled exponentially from the RO period difference. The difference nature of estimation technique enables to mitigate the impact of local supply voltage variation and error due to systematic variations in the path of the RO. The potency of the proposed technique is demonstrated using measurement results from a fabricated test chip designed in a 0.13μm process technology node. Measurement results from a test chip indicate that the test structure can estimate local random threshold voltage variations and is also useful in improving the yield as well as in process optimization.	PDF Xplore
6.3	Comparison of MOSFET Threshold Voltage Extraction Methods with Temperature Variation Y. -H. Cheng ON Semiconductor, Corporate Research and Development, East Greenwich, RI, USA DOI: 10.1109/ICMTS.2019.8730978 ABSTRACT: Threshold voltage is a fundamental parameter for MOSFET device and technology characterization. Multiple threshold voltage extraction methods are compared in this paper with experimental data over a wide temperature range from -40°C to 150°C for 5V and 1.8V NMOS devices in a 180 nm BCD process. Consistent results are found among two linear extrapolation methods from the drain current versus gate voltage transfer characteristics and transition method for MOSFETs biased in the linear region. The difference in temperature coefficients of extracted threshold voltages from different methods are compared and the different trends of scaled drain currents at extracted threshold voltages over temperature are analyzed to reveal the underestimation of threshold voltage temperature coefficients in gm/Id methods.	PDF Xplore
6.4	Analysis of Test Structure Design Induced Variation in on Si On-wafer TRL Calibration in sub-THz C. Yadav, S. Fregonese, M. Deng, M. Cabbia, M. De Matos, M. Jaoul, T. Zimmer IMS Laboratory, University of Bordeaux, Talence cedex, France DOI: 10.1109/ICMTS.2019.8730962 ABSTRACT: In this paper, we present on-wafer S-parameter measurement of test structures designed and fabricated on silicon substrate for transistor de-embedding upto 220 GHz. Using two different types of reflects (open circuit and short circuit) in on-wafer thru-reflect-line (TRL) calibration, we show that in the on-wafer TRL, some of the error terms could be sensitive to the use of the reflect type and may not contain always exactly the same value with change in reflect type. Further, impact of reflect induced variations in error terms is demonstrated on the on-wafer TRL calibrated S-parameters of de-embedding structures. On basis of the on-wafer TRL calibrated S-parameters of de-embedding structures, we conclude that one type of reflect could suit more in the on-wafer TRL calibration for a de-embedding structure than another type.	PDF Xplore

Session 7: Measurement Technique

7.1	A Study of Power Supply Stability in Ring Oscillator Structures B. Smith, D. Hall, B. Verzi¹, D. Pechonis NXP Semiconductors, Austin, Texas, USA ¹Keysight Technologies, Austin, Texas, USA DOI: 10.1109/ICMTS.2019.8730980 ABSTRACT: The stability of the supply rails while testing wafer-level ring oscillator structures has been studied. The power and ground supplies were observed to be disturbed by a switching output signal, a result of the tester hardware being unable to respond fast enough to maintain stable voltages. It was shown that using stronger test hardware to provide 0 V improved the stability of the ground voltage. It was further shown that the addition of discrete capacitors between the power supplies improved the stability of the supply voltage. The areas under curves in the supply voltage waveforms were used as quality metrics to quantify the charge involved in the disruption and to evaluate different solutions. Samples from six technologies built in three factories all showed the same issues and responded to the hardware changes, demonstrating that the issue was not sensitive to Si technology.	PDF Xplore
7.2	Fast Tera-Ohm Measurement Approach Using V93k AVI64 DC Scale Card J. Stolle, R. Poirier¹, M. Froehle², H. Weindl², M. Naiman, V. Kriegerstein² Advantest Europe GmbH, Boeblingen, Germany ¹Innova-test, Bordeaux, France ²GLOBALFOUNDRIES, Dresden, Germany DOI: 10.1109/ICMTS.2019.8730977 ABSTRACT: This paper describes a measurement approach for massive parallel testing enabling characterization of Mega-Ohm resistor and Giga-Ohm isolation structures for process characterization using low power test conditions with Advantest V93000 AVI64 equipment. Moreover, it exhibits the technique how to accomplish resistance readings up to single digit Tera-Ohms. Compared to a parametric benchmark tool, we are approx. 5x faster with sufficient accuracy and high repeatability. The new measurement methodology was applied for interconnect process characterization of an advanced CMOS technology.	PDF Xplore
7.4	Characterization and Modeling of Zener Diode Breakdown Voltage Mismatch M. Yang, C. C. McAndrew¹, L. Chao, K. Xia NXP Semiconductors, Beijing, PRC ¹NXP Semiconductors, Chandler, AZ DOI: 10.1109/ICMTS.2019.8730968 ABSTRACT: In this paper, we present test structures and procedures to characterize and model mismatch of the breakdown voltage of Zener diodes. Direct force-current/measure-voltage for breakdown is not sufficiently accurate for mismatch characterization, so we use an I(V) sweep followed by cubic interpolation; the accuracy of this approach is verified using the Tuinhout DUT-1-2-1-2 methodology. To demonstrate our approach, we present measured and modeled breakdown voltage mismatch for 5 V Zener diodes in a 90 nm power BCD process.	PDF Xplore
7.5	Physical, small-signal and pulsed thermal impedance characterization of multi-finger SiGe HBTs close to the SOA edges M. Couret, G. Fischer¹, S. Frégonése, T. Zimmer, C. Maneux IMS Laboratory, University of Bordeaux, Talence, France ¹IHP - Leibniz-Insitut for innovative Mikroelektronik, Frankfurt (Oder), Germany DOI: 10.1109/ICMTS.2019.8730964 ABSTRACT: A thermal impedance model of single-finger and multi-finger SiGe heterojunction bipolar transistors (HBTs) is presented. The heat flow analysis through the device has to be considered in two diffusion parts: the front-end-of-line (FEOL) diffusion and the back-end-of-line (BEOL) diffusion. Therefore, this new thermal impedance model features multi-poles network which has been incorporated in HiCuM L2 compact model. The HiCuM compact model simulation results are compared with on-wafer low-frequency S-parameters measurements at room temperature highlighting the device frequency dependence of self-heating mechanism. The simulation results are also compared to pulse measurements to improve reliability analysis.	PDF Xplore
7.7	A Study of Test Throughput Analysis on Capacitance Measurement of Parallel Test Structures Using LCR and Direct Charge based Instruments V. Katragadda, N. Deshmukh, A. Gasasira, C. -M. Lee¹, A. Cusick PDYE Test & Char, GlobalFoundries, Malta, NY, USA ¹Semiconductor Test, Keysight Technologies, USA DOI: 10.1109/ICMTS.2019.8730979 ABSTRACT: Advancement in technology scaling has enabled further integration of additional structures per area. While the direct benefits of improved performance in smaller packaging is achieved, the test content per structure has increased for quicker and better yield learning, ultimately driving up test time and cost. Parallel testing where multiple devices can be measured synchronously or asynchronously has shown results in addressing such high test demand [1] [2]. In this paper, we discuss capacitance measurement using traditional LCR meter and direct charge measurement (DCM) hardware [3] on advanced technology nodes. The LCR meter is a shared resource, whereas DCM is a per-pin based architecture of capacitance measurement, enabled for higher throughput. Recent studies [3] [4] [7] comparing DCM based hardware to LCR meters can fall short when devices show higher leakage especially during the initial phase of technology development. We present how an improved DCM hardware [6] helps in better overall correlation to LCR while maintaining throughput. Also, the structures designed for parallel test (DFPT), contribute to higher throughput when tested using DCM.	PDF Xplore

Session 8: Noise

8.1	Experimental Extraction of Body Bias Dependence of Low Frequency Noise in sub-micron MOSFETs from Subthreshold to Moderate Inversion Regime C. Tanaka, K. Adachi¹, A. Nakayama, Y. Iguchi, S. Yoshitomi Design Technology Innovation Division ¹Device Technology Research & Development Center, Toshiba Memory Corporation DOI: 10.1109/ICMTS.2019.8730953 ABSTRACT: In this study, we investigate low frequency noise under the reverse body bias conditions from subthreshold to moderate inversion regime with 1/f noise measurement for small-area conventional nMOSFETs. The reverse body bias is not influenced on coulomb scattering process, even though the depletion capacitance was influenced by body bias. Furthermore, gate-to-bulk coupling was reduced flat-band fluctuations. These results suggest that reverse body bias is applicable to the low power and high signal-to-noise ratio for low current operation.	PDF Xplore
8.2	Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation A. K. M. M. Islam, R. Shimizu¹, H. Onodera¹ Graduate School of Engineering, Kyoto University, Kyoto, JAPAN ¹Graduate School of Informatics, Kyoto University, Kyoto, JAPAN DOI: 10.1109/ICMTS.2019.8730976 ABSTRACT: We present measurement results of the effect of switching speed and logic depth on random telegraph noise (RTN) induced delay fluctuation using a test chip fabricated in a 65-nm Silicon-On- Thin-Buried-Oxide process. Measurement results reveal that the expected value of delay fluctuation decreases rapidly with the increase of logic depth. However, the delay fluctuation above 99th percentile is not strongly affected by logic depth. RTN-induced delay fluctuations are found to be not affected by the switching speed of logic gates. The measurement results provide useful insights into developing a statistical static timing analysis (SSTA) framework to asses the worst-case delay under the presence of RTN.	PDF Xplore
8.3	A Method to Determine the Electret Charge Potential of MEMS Vibrational Energy Harvester using Pure White Noise H. Mitsuya, H. Ashizawa, H. Homma¹, G. Hashiguchi², H. Toshiyoshi¹ Saginomiya Seisakusho, Inc., Saitama, Japan ¹Institute of Industrial Science, The university of Tokyo, Tokyo, Japan ²Shizuoka University, Shizuoka, Japan DOI: 10.1109/ICMTS.2019.8730995 ABSTRACT: A high-throughput measurement method is developed to determine the electrical potential of electret embedded in a MEMS vibrational energy harvester. When a electret device is electrically excited with white noise voltage, the mechanical resonance disappears from the real-time FFT analysis when the superposed dc bias voltage compensates the electret potential, by which the magnitude of the electret potential is known.	PDF Xplore

Session 9: Packaging

9.1	Probing impact on pad moisture tightness: A challenge for pad size reduction M. Vidal-Dho, Q. Hubert¹, P. Gonon, P. Delorme¹, J. Jacquot¹, M. Marchetti¹, L. Beauvisage¹, J. -M. Moragues¹, P. Potard², P. Fornara¹, J. -P. Escales¹, P. Sallagoity¹, O. Pizzuto¹, D. Maury¹, J. -M. Mirabel¹ LTM CNRS, Grenoble, France ¹STMicroclcctronics Rousset, Rousset, France ²STMicroelectronics, Crolles, FR DOI: 10.1109/ICMTS.2019.8730990 ABSTRACT: This paper underlines the damages induced by probing on narrow pads reliability of specifically designed test structures placed on dicing streets and indicates that probing during electrical test steps provokes detrimental cracks diving from the passivation through the BEOL layers providing a path for moisture ingress.	PDF Xplore
9.2	Characterization of Micro-Bumps for 3DIC Wafer Acceptance Tests C. B. Sia FormFactor Inc., Singapore DOI: 10.1109/ICMTS.2019.8730921 ABSTRACT: The strong market needs to embed multiple functionalities from different semiconductor processing technologies into a single system continue to drive demands for more advanced 3DIC packaging technologies. Dimensions of copper pillar micro-bumps are consistently reduced in every new technology node to facilitate the 3D stacking of multiple dies so that overall system performance can be improved. Semiconductor packaging companies must perform wafer acceptance tests to qualify their copper pillar micro-bumping process. Probecards and single DC probes are unable to address the measurement challenges and flexibilities needed for micro-bump wafer acceptance tests, which measure the micro-bump resistance and the wafer surface leakage currents in a single setup. In this paper, consistent and repeatable test results are obtained in a fully automatic manner using custom DC positioners with theta-X planarizing capability and true Kelvin probes for micro-bump resistance measurements as well as standard DC probes for wafer surface leakage measurements.	PDF Xplore
9.3	Damage Assessment Structure of Test-Pad Post-Processing on CMOS LSIs Y. Okamoto, A. Mizushima¹, N. Usami, J. Kinoshita², A. Higo¹, Y. Mita School of Electrical Engineering, The University of Tokyo, Tokyo, Japan ¹VLSI Design & Education Center (VDEC), The University of Tokyo, Tokyo, Japan ²NEXTY Electronics Corporation, Tokyo, Japan DOI: 10.1109/ICMTS.2019.8730991 ABSTRACT: We assessed potential degradation of MOSFET characteristics induced by post-processing of extra bond pads. The pads are used as stable electrical connections in repairing and test. The test structure consists of 16⨉16 arrayed PMOSFETs designed with 0.6 μm CMOS technology. An aluminum pad is deposited on the arrayed structure using a silicon shadow mask, and wire bonding is performed subsequently. The characteristics of Id-Vg were compared before and after the post-process. The result indicates that the post-processing does not affect the characteristics of MOSFETs, and therefore it can be used to place post-processed bond pads over an LSI chip.	PDF Xplore

Session 10: TFTs

10.1	Understanding the Effects of Low-Temperature Passivation and Annealing on ZnO TFTs Test Structures R. A. Rodriguez-Davila, P. Bolshakov, C. D. Young, M. Quevedo-Lopez Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX, USA DOI: 10.1109/ICMTS.2019.8730965 ABSTRACT: Back-gate ZnO TFTs - with and without top-side passivation - were fabricated and electrically characterized. Passivation layers consisting of HfO2, Al2O3, and Parylene were introduced to study their impact on the TFT performance. Annealing was done to improve the electrical characteristics of passivated devices by neutralizing the initial charge introduced as a result of the low-temperature passivation. Low-temperature annealing combined with an Al2O3 passivation layer demonstrates an I-V response comparable to ZnO TFTs without any passivation layer, indicating the viability of Al2O3 as a good candidate for passivating ZnO TFTs.	PDF Xplore
10.2	A compact model of I -V characteristic degradation for organic thin film transistors M. Saito, M. Shintani¹, K. Kuribara², Y. Ogasahara², T. Sato Graduate School of Informatics, Kyoto University, Kyoto, Japan ¹Graduate School of Science and Technology, Nara Institute of Science and Technology, Nara, Japan ²National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2019.8730987 ABSTRACT: The lifetime of organic thin film transistors is known to be significantly shorter than that of silicon MOSFETs. It is hence important to predict their degradation at early design phase. This paper proposes a drain current model for simulating organic thin film transistors. The proposed model characterizes the degradation by the changes of the threshold voltage and carrier mobility. With the extracted parameters, the proposed model successfully reproduces temporal performance degradation of the fabricated devices. The experimental results also demonstrate that the proposed model achieves 38% better accuracy compared to the existing model.	PDF Xplore

By First Author

6.1	Two-transistor Voltage-Measurement-Based Test Structure for Fast Extraction of MOS Mismatch Design Parameters J. P. M. Brito, S. Bampi¹ CEITEC S.A. Semiconductors, Porto Alegre, Brazil ¹Graduate Program on Microelectronics - PGMICRO, Federal University of of Rio Grande do Sul - UFRGS DOI: 10.1109/ICMTS.2019.8730918 HOVER FOR ABSTRACT	PDF Xplore
6.3	Comparison of MOSFET Threshold Voltage Extraction Methods with Temperature Variation Y. -H. Cheng ON Semiconductor, Corporate Research and Development, East Greenwich, RI, USA DOI: 10.1109/ICMTS.2019.8730978 HOVER FOR ABSTRACT	PDF Xplore
5.2	Modeling and Test Structures for Accurate Current Sensing in Vertical Power FETs M. Chu, T. Harjono, K. Joardar, V. Krishnamurthy Advanced Technology Development, Texas Instruments, Dallas, TX DOI: 10.1109/ICMTS.2019.8730949 HOVER FOR ABSTRACT	PDF Xplore
7.5	Physical, small-signal and pulsed thermal impedance characterization of multi-finger SiGe HBTs close to the SOA edges M. Couret, G. Fischer¹, S. Frégonése, T. Zimmer, C. Maneux IMS Laboratory, University of Bordeaux, Talence, France ¹IHP - Leibniz-Insitut for innovative Mikroelektronik, Frankfurt (Oder), Germany DOI: 10.1109/ICMTS.2019.8730964 HOVER FOR ABSTRACT	PDF Xplore
3.3	Test Structures for Characterising the Silver Chlorination Process During Integrated Ag/AgCl Reference Electrode Fabrication C. Dunare, J. R. K. Marland, E. O. Blair¹, A. Tsiamis, F. Moorel, J. G. Terry, A. J. Walton, S. Smith School of Engineering, The University of Edinburgh, Edinburgh, UK ¹Department of Biomedical Engineering, University of Strathclyde, Glasgow, UK DOI: 10.1109/ICMTS.2019.8730966 HOVER FOR ABSTRACT	PDF Xplore
1.3	In search of a hole inversion layer in $\mathrm{Pd}/\mathrm{MoO}_{x}/\mathrm{Si}$ diodes through I- V characterization using dedicated ring-shaped test structures G. Gupta, S. D. Thammaiah, R. J. E. Hueting, L. K. Nanver MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS.2019.8730920 HOVER FOR ABSTRACT	PDF Xplore
4.3	Evaluation of Truly Passive Crossbar Memory Arrays on Short Flow Characterization Vehicle Test Chips C. Hess, T. Brozek, H. Schneider, Y. Yu, M. Lunenborg, K. H. Ng, D. Ciplickas, R. Vallishayee, C. Dolainsky, L. H. Weiland PDF Solutions Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS.2019.8730984 HOVER FOR ABSTRACT	PDF Xplore
1.1	A Micro Racetrack Optical Resonator Test Structure to Optimize Pattern Approximation in Direct Lithography Technologies A. Higo, T. Sawamura, M. Fujiwara, E. Ota, A. Mizushima, E. Lebrasseur, T. Arakawa¹, Y. Mita² VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan ¹Faculty of Eng., Yokohama National University, Kanagawa, Japan ²Dept. of EEIS, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2019.8730981 HOVER FOR ABSTRACT	PDF Xplore
8.2	Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation A. K. M. M. Islam, R. Shimizu¹, H. Onodera¹ Graduate School of Engineering, Kyoto University, Kyoto, JAPAN ¹Graduate School of Informatics, Kyoto University, Kyoto, JAPAN DOI: 10.1109/ICMTS.2019.8730976 HOVER FOR ABSTRACT	PDF Xplore
6.2	On-Chip Threshold Voltage Variability Detector Targeting Supply of Ring Oscillator for Characterizing Local Device Mismatch P. Jain, B. P. Das Department of ECE, Indian Institute of Technology, Roorkee, India DOI: 10.1109/ICMTS.2019.8730952 HOVER FOR ABSTRACT	PDF Xplore
2.3	Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions M. Jaoul, D. Ney¹, D. Céli¹, C. Maneux, T. Zimmer IMS, Université Bordeaux I, Talence, France ¹ST Microelectronics, Crolles, France DOI: 10.1109/ICMTS.2019.8730951 HOVER FOR ABSTRACT	PDF Xplore
7.7	A Study of Test Throughput Analysis on Capacitance Measurement of Parallel Test Structures Using LCR and Direct Charge based Instruments V. Katragadda, N. Deshmukh, A. Gasasira, C. -M. Lee¹, A. Cusick PDYE Test & Char, GlobalFoundries, Malta, NY, USA ¹Semiconductor Test, Keysight Technologies, USA DOI: 10.1109/ICMTS.2019.8730979 HOVER FOR ABSTRACT	PDF Xplore
2.1	Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive ring Oscillators R. Kishida, T. Asuke¹, J. Furuta¹, K. Kobayashil¹ Department of Electrical Engineering, Tokyo University of Science, Noda, Chiba, Japan ¹Department of Electronics, Kyoto Institute of Technology, Japan DOI: 10.1109/ICMTS.2019.8730967 HOVER FOR ABSTRACT	PDF Xplore
1	High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Field-Effect Transistors [Invited] Y. Koide Research Network and Facility Services Division, National Institute for Materials Science (NIMS), Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2019.8730974 HOVER FOR ABSTRACT	PDF Xplore
4.1	Resistance Measurement Platform for Statistical Analysis of Next Generation Memory Materials T. Maeda, Y. Omura¹, A. Teramoto², R. Kuroda, T. Suwa², S. Sugawa² Graduate School of Engineering, Tohoku University, Sendai, Japan ¹School of Engineering, Tohoku University, Sendai, Japan ²New Industry Creation Hatchery Center, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS.2019.8730955 HOVER FOR ABSTRACT	PDF Xplore
8.3	A Method to Determine the Electret Charge Potential of MEMS Vibrational Energy Harvester using Pure White Noise H. Mitsuya, H. Ashizawa, H. Homma¹, G. Hashiguchi², H. Toshiyoshi¹ Saginomiya Seisakusho, Inc., Saitama, Japan ¹Institute of Industrial Science, The university of Tokyo, Tokyo, Japan ²Shizuoka University, Shizuoka, Japan DOI: 10.1109/ICMTS.2019.8730995 HOVER FOR ABSTRACT	PDF Xplore
9.3	Damage Assessment Structure of Test-Pad Post-Processing on CMOS LSIs Y. Okamoto, A. Mizushima¹, N. Usami, J. Kinoshita², A. Higo¹, Y. Mita School of Electrical Engineering, The University of Tokyo, Tokyo, Japan ¹VLSI Design & Education Center (VDEC), The University of Tokyo, Tokyo, Japan ²NEXTY Electronics Corporation, Tokyo, Japan DOI: 10.1109/ICMTS.2019.8730991 HOVER FOR ABSTRACT	PDF Xplore
4.4	Proposed one-dimensional passive array test circuit for parallel kelvin measurement with efficient area use M. Rerecich, C. D. Young¹ Samsung Austin Semiconductor, LLC, Austin, TX, USA ¹Materials Science and Engineering Department, University of Texas at Dallas, Dallas, TX, USA DOI: 10.1109/ICMTS.2019.8730948 HOVER FOR ABSTRACT	PDF Xplore
10.1	Understanding the Effects of Low-Temperature Passivation and Annealing on ZnO TFTs Test Structures R. A. Rodriguez-Davila, P. Bolshakov, C. D. Young, M. Quevedo-Lopez Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX, USA DOI: 10.1109/ICMTS.2019.8730965 HOVER FOR ABSTRACT	PDF Xplore
10.2	A compact model of I -V characteristic degradation for organic thin film transistors M. Saito, M. Shintani¹, K. Kuribara², Y. Ogasahara², T. Sato Graduate School of Informatics, Kyoto University, Kyoto, Japan ¹Graduate School of Science and Technology, Nara Institute of Science and Technology, Nara, Japan ²National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2019.8730987 HOVER FOR ABSTRACT	PDF Xplore
4.2	Optimization of 3ω Method for Phase-Change Materials Thermal Conductivity Measurement at High Temperature A. L. Serra, G. Bourgeois, M. C. Cyrille, J. Cluzel, J. Garrione, G. Navarro, E. Nowak CEA, Univ. Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS.2019.8730993 HOVER FOR ABSTRACT	PDF Xplore
9.2	Characterization of Micro-Bumps for 3DIC Wafer Acceptance Tests C. B. Sia FormFactor Inc., Singapore DOI: 10.1109/ICMTS.2019.8730921 HOVER FOR ABSTRACT	PDF Xplore
7.1	A Study of Power Supply Stability in Ring Oscillator Structures B. Smith, D. Hall, B. Verzi¹, D. Pechonis NXP Semiconductors, Austin, Texas, USA ¹Keysight Technologies, Austin, Texas, USA DOI: 10.1109/ICMTS.2019.8730980 HOVER FOR ABSTRACT	PDF Xplore
7.2	Fast Tera-Ohm Measurement Approach Using V93k AVI64 DC Scale Card J. Stolle, R. Poirier¹, M. Froehle², H. Weindl², M. Naiman, V. Kriegerstein² Advantest Europe GmbH, Boeblingen, Germany ¹Innova-test, Bordeaux, France ²GLOBALFOUNDRIES, Dresden, Germany DOI: 10.1109/ICMTS.2019.8730977 HOVER FOR ABSTRACT	PDF Xplore
5.1	Vertical Bipolar Transistor Test Structure for Measuring Minority Carrier Lifetime in IGBTs K. Takeuchi, M. Fukui, T. Saraya, K. Itou, T. Takakura, S. Suzuki, Y. Numasawa¹, K. Kakushima², T. Hoshii², K. Furukawa², M. Watanabe², N. Shigyo², H. Wakabayashi², M. Tsukuda, A. Ogura¹, K. Tsutsui², H. Iwai², S. Nishizawa, I. Omura, H. Ohashi², T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan ¹Meiji University, Kawasaki, Japan ²Tokyo Institute of Technology, Yokohama, Japan DOI: 10.1109/ICMTS.2019.8730922 HOVER FOR ABSTRACT	PDF Xplore
8.1	Experimental Extraction of Body Bias Dependence of Low Frequency Noise in sub-micron MOSFETs from Subthreshold to Moderate Inversion Regime C. Tanaka, K. Adachi¹, A. Nakayama, Y. Iguchi, S. Yoshitomi Design Technology Innovation Division ¹Device Technology Research & Development Center, Toshiba Memory Corporation DOI: 10.1109/ICMTS.2019.8730953 HOVER FOR ABSTRACT	PDF Xplore
2.2	Extremely Low Voltage Operatable On-Chip- Monitor-Test Circuit for Plasma Induced Damage using High sensitivity Ring-VCO(Voltage Controlled Oscillator) M. Tomita, S. Mori, Y. Fukuzaki, K. Ogawa, S. Miyake, H. Ohnuma Sony Semiconductor Solutions Corporation, Kanagawa, Japan DOI: 10.1109/ICMTS.2019.8730985 HOVER FOR ABSTRACT	PDF Xplore
5.3	A study on statistical parameter modeling of power MOSFET model by principal component analysis H. Tsukamoto, M. Shintani¹, T. Sato² Faculty of Engineering, Kyoto University, Kyoto, Japan ¹Graduate School of Science and Technology, Nara Institute of Science and Technology, Nara, Japan ²Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2019.8730946 HOVER FOR ABSTRACT	PDF Xplore
3.4	Test structure to assess the useful extent of regular dummy devices around high-precision metal fringe capacitor arrays H. Tuinhout, I. Brunets, A. Z. -v. Duijnhoven NXP Semiconductors, Eindhoven, AE, The Netherlands DOI: 10.1109/ICMTS.2019.8730988 HOVER FOR ABSTRACT	PDF Xplore
3.2	Continuity assessment for supercritical-fluids-deposited (SCFD) Cu film as electroplating seed layer N. Usami, E. Ota¹, A. Higo¹, T. Momose², Y. Mita¹ Tokyo Daigaku, Bunkyo-ku, Tokyo, JP ¹VLSI Design and Education Center (VDEC), The University of Tokyo ²Department of Material Engineering, The University of Tokyo DOI: 10.1109/ICMTS.2019.8730945 HOVER FOR ABSTRACT	PDF Xplore
9.1	Probing impact on pad moisture tightness: A challenge for pad size reduction M. Vidal-Dho, Q. Hubert¹, P. Gonon, P. Delorme¹, J. Jacquot¹, M. Marchetti¹, L. Beauvisage¹, J. -M. Moragues¹, P. Potard², P. Fornara¹, J. -P. Escales¹, P. Sallagoity¹, O. Pizzuto¹, D. Maury¹, J. -M. Mirabel¹ LTM CNRS, Grenoble, France ¹STMicroclcctronics Rousset, Rousset, France ²STMicroelectronics, Crolles, FR DOI: 10.1109/ICMTS.2019.8730990 HOVER FOR ABSTRACT	PDF Xplore
2	Taming Emerging Devices' Variation and Reliability Challenges with Architectural and System Solutions [Invited] Y. Wang, L. Shao, M. A. Lastras-Montaä±o¹, K. -T. Cheng² Department of Electrical and Computer Engineering, University of California, Santa Barbara, U.S.A. ¹FC, Universidad Autónoma de San Luis Potosä, México ²School of Engineering, Hong Kong University of Science and Technology, Hong Kong DOI: 10.1109/ICMTS.2019.8730924 HOVER FOR ABSTRACT	PDF Xplore
1.2	PbS Quantum Dot / ZnO Nanowires Hybrid Test Structures for Infrared Photodetector H. Wang, A. Higo¹, Y. Mita², T. Kubo, H. Segawa Research Center for Advanced Science and Technology, The University. of Tokyo, Tokyo, Japan ¹VLSI Design and Education Research Center, The University of Tokyo, Tokyo, Japan ²Graduate School of Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2019.8730956 HOVER FOR ABSTRACT	PDF Xplore
1.4	Wafer-Level Test Solution Development for a Quad-Channel Linear Driver Die in a 400G Silicon Photonics Transceiver Module Y. Wang, H. Ding, B. Blakely, A. Yan Department of Silicon Photonics Test Development, GLOBALFOUNDRIES, Essex Junction, VT, USA DOI: 10.1109/ICMTS.2019.8730947 HOVER FOR ABSTRACT	PDF Xplore
6.4	Analysis of Test Structure Design Induced Variation in on Si On-wafer TRL Calibration in sub-THz C. Yadav, S. Fregonese, M. Deng, M. Cabbia, M. De Matos, M. Jaoul, T. Zimmer IMS Laboratory, University of Bordeaux, Talence cedex, France DOI: 10.1109/ICMTS.2019.8730962 HOVER FOR ABSTRACT	PDF Xplore
7.4	Characterization and Modeling of Zener Diode Breakdown Voltage Mismatch M. Yang, C. C. McAndrew¹, L. Chao, K. Xia NXP Semiconductors, Beijing, PRC ¹NXP Semiconductors, Chandler, AZ DOI: 10.1109/ICMTS.2019.8730968 HOVER FOR ABSTRACT	PDF Xplore
3.1	Electrical characterization of hot-wire assisted atomic layer deposited Tungsten films K. van der Zouw, A. A. I. Aarnink, J. Schmitz, A. Y. Kovalgin MESA+, University of Twente, Enschede, AE, The Netherlands DOI: 10.1109/ICMTS.2019.8730954 HOVER FOR ABSTRACT	PDF Xplore