ICMTS 2017 Program

2017 Program Booklet

By Session

Session 1: Novel Test Structures

1.1	Characterization and monitoring structures for robustness against cyclic thermomechanical stress: Design and influence of Ti-Al(Cu) layer scheme A. Mann, H. Lohmeyer, Y. Joseph1 Robert Bosch GmbH Automotive Electronics, Reutlingen, Germany 1Technische Universität Bergakademie Freiberg, Institute of Electronic and Sensor Materials, Freiberg, Germany DOI: 10.1109/ICMTS.2017.7954255 ABSTRACT: A wafer-level test approach based on dedicated test structures sensitive to repetitive-power-pulsing stress is described. The approach is suitable for the qualification of different IC backend stack options with respect to thermomechanical robustness in an early phase of technology development and for process control purposes. In this work, we investigate low-cycle robustness by end-of-life tests for different smart-power technologies with AlCu backend stack. Compared to reference trials a strong dependence of the mean lifetime on lower metal finger configuration and on the used Ti-Al(Cu) layer scheme is found.	PDF Xplore
1.2	Test structures for studying flexible interconnect supported by carbon nanotube scaffolds D. Jiang, S. Sun, M. Edwards, K. Jeppson Department of Microtechnology and Nanoscience, Electronics Materials and Systems Laboratory, Gothenburg, Sweden DOI: 10.1109/ICMTS.2017.7954256 ABSTRACT: Due to their flexibility and compatibility with silicon devices, the use of carbon nanotubes as scaffolds for metal interconnect in flexible and wearable electronics has been proposed. This paper examines the performance of dual-height carbon nanotubes as flexible scaffolds for horizontal and vertical interconnects. For this purpose, a number of test structures have been designed and fabricated and their electrical and mechanical performance been investigated.	PDF Xplore
1.3	Dealing with leakage current in TLM and CTLM structures with vertical junction isolation S. N. Bystrova, S. M. Smits, J. H. Klootwijk1, R. A. M. Wolters, A. Y. Kovalgin, L. K. Nanver2, J. Schmitz MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands 1Philips Research, Enschede, The Netherlands 2Aalborg University, Aalborg, Denmark DOI: 10.1109/ICMTS.2017.7954257 ABSTRACT: Transmission line method (TLM) structures are often employed to extract contact resistivity between a metal and a doped semiconductor region. In this article we treat the situation where the doped region is junction-isolated from the substrate. The junction isolation may be leaky resulting in erroneous parameter extraction. The effect of junction leakage is treated both theoretically and through exemplary wafer-level CTLM measurement results on photovoltaic cells (solar cells) and epi-wafer samples. This paper describes how reliable contact resistivity values can be obtained using the transmission line method on junction isolated structures.	PDF Xplore
1.4	Electrical test structures for verifying continuity of ultra-thin insulating and conducting films S. Banerjee, R. van der Velde, M. Yang, J. Schmitz, A. Y. Kovalgin1 MESA+ Institute for Nanotechnology, University of Twente, Enschede, AE, The Netherlands 1Universiteit Twente, Enschede, Overijssel, NL DOI: 10.1109/ICMTS.2017.7954258 ABSTRACT: In this work, electrical characterization on insulating aluminium nitride (AlN) and conducting tungsten (W) films was performed using dedicated test structures, in order to determine the thickness at which the films reached continuity. A discontinuous-to-continuous transformation of the AlN layer (occurring around 11 nm) resulted in a transition from ohmic to non-ohmic current conduction, in addition to drastically reduced current density levels. For similar transformation of the W layer (occurring between 2-3 nm) the reverse transition was observed, which was accompanied by a rapid convergence of the film resistivity to the bulk value. The electrical analysis of film continuity was complemented optically by in-situ monitoring of the film growth and its closure, with the spectroscopic ellipsometry (SE) technique.	PDF Xplore

Session 2: Novel Materials Characterization

2.1	Detailed characterization and critical discussion of series resistance in graphene-metal contacts S. Venica, F. Driussi1, A. Gahoi, V. Passi, P. Palestri1, M. C. Lemme, L. Selmi1 University of Siegen, School of Science and Technology, Siegen, Germany 1Universitä¡ degli Studi di Udine, Dipartimento Politecnico di Ingegneria e Architettura (DPIA), Udine, Italy DOI: 10.1109/ICMTS.2017.7954259 ABSTRACT: We apply the contact-end resistance method to TLM structures in order to characterize the graphene-metal contact resistance. A critical analysis of the experimental results shows that the commonly used transmission line model fails to accurately describe the graphene-metal contact under specific biasing conditions. The experiments suggest the presence of an additional resistance contribution associated to the p-p+ junction induced in the graphene in the proximity of the contact. This voltage dependent resistance limits the range of applicability of the extraction technique. However, for carefully chosen bias conditions that reduce this additional resistance to small values, the technique provides reliable results, useful to investigate the graphene-metal contact properties and their technology dependence.	PDF Xplore
2.2	The outstanding properties of graphene-insulator-semiconductor (GIS) test structures for photoelectric determination of semiconductor devices band diagram K. Piskorski, V. Passi1, J. Ruhkopf1, M. C. Lemme1, H. M. Przewlocki Institute of Electron Technology, Warsaw, Poland 1University of Siegen, Siegen, Germany DOI: 10.1109/ICMTS.2017.7954260 ABSTRACT: The energy band diagram is a primary feature of any semiconductor device and determines its physical parameters and practical applicability. The most effective technique of band diagram characterization is the photoelectric measurement based on internal photoemission phenomena in the layered structures. In the technologically important metal-insulator-semiconductor (MIS) structures, the most important parameters of the band diagram are barrier heights on both sides of the insulator layer. In this article, we consider graphene-insulator-semiconductor (GIS) structures in which the graphene replaces metal as the gate material. Using graphene layer as the gate of the structure facilitates direct measurements of the photocurrent due to hole emission from the substrate into the insulator, allowing determination of the barrier height for holes. Having also measured the barrier height for electrons emitted from the substrate into the insulator the direct determination of the insulator band gap is possible.	PDF Xplore
2.3	Electromechanical testing of ZnO thin films under high uniaxial strain R. Tuyaerts, J. -P. Raskin1, J. Proost Universite catholique de Louvain, Louvain-la-Neuve, BE 1Institute of Information and Communication Technologies, Universit catholique de Louvain, Louvain-la-Neuve, Belgium DOI: 10.1109/ICMTS.2017.7954261 ABSTRACT: Thanks to an innovative design, stress-strain curves of released thin films can be obtained, from zero stress up to the tensile fracture stress of the material, using internal stress present in a second material. This second material acts as an actuator that pulls on the sample when released from the substrate, allowing to apply a stress on the tested material. This technique has also been used to make electrical resistivity measurements under deformation to extract piezoresistive coefficients and can be extended to perform Hall measurements to measure charge carriers density and mobility as well as the resistivity.	PDF Xplore
2.4	Test structures for understanding the impact of ultra-high vacuum metal deposition on top-gate MoS2 field-effect-transistors P. Bolshakov, P. Zhao, C. M. Smyth, A. Azcatl, R. M. Wallace, C. D. Young, P. K. Hurley1 Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX, USA 1Tyndall National Institute, University College Cork, Dyke Parade, Cork, Ireland DOI: 10.1109/ICMTS.2017.7954262 ABSTRACT: Greek crosses and TLM test structures were fabricated and characterized along with top-gate field effect transistors. We also show the usefulness and adaptation of a single TLM structure into multiple bottom-gate FETs that allow for extraction of contact resistance and typical device parameters for direct correlation on the same TMD flake enabling very little variability that can occur “flake to flake”. Sheet resistance and contact resistance were successfully extracted and improvement in device performance was demonstrated with C-V and I-V measurements.	PDF Xplore

Session 3: Variability Characterization

3.1	Statistical characterization and modeling of drain current local and global variability in 14 nm bulk FinFETs T. Karatsori, C. Theodorou, R. Lavieville, T. Chiarella1, J. Mitard1, N. Horiguchi1, C. A. Dimitriadis2, G. Ghibaudo IMEP-LAHC, Univ. Grenoble Alpes, Minatec, Grenoble, France 1IMEC, Leuven, Belgium 2Department of Physics, Aristotle University of Thessaloniki, Greece DOI: 10.1109/ICMTS.2017.7954263 ABSTRACT: A detailed statistical characterization and modeling of drain current local and global variability in 14nm Si bulk FinFET devices is performed. To this end, an analytical mismatch model covering weak to strong inversion region is used to extract the main matching parameters. Our results show that, despite their very aggressive dimensions in terms of Fin width and height, such devices exhibit excellent local and global variability performance. Moreover, a Lambert-W function-based MOSFET compact model is used for MC simulation of local variability.	PDF Xplore
3.2	Measurement of mismatch factor and noise of SRAM PUF using small bias voltage Ziyang Cui, Baikun Zheng, Yanhao Piao, Shiyu Liu, Ronghao Xie, H. Shinohara Graduate School of Information, Production and Systems, Waseda University, Fukuoka, Japan DOI: 10.1109/ICMTS.2017.7954264 ABSTRACT: Mismatch factor of SRAM bit cell and noise factor that affects its power up state are measured using 256 bit SRAM PUF test structure with bias voltage inputs. Probability of power up state is used to extract a mismatch factor normalized by σn (sigma noise voltage). By combining shifted bias voltages and repeat evaluation, whole 256 bit mismatch factors from real SRAM with small modification are obtained. According to the measurement data, it is confirmed that both noise factor and mismatch factor follow Gaussian distribution within a range of ±3.5σ and ± 2.9σ, respectively.	PDF Xplore
3.3	Vth-shiftable SRAM cell TEGs for direct measurement for the immunity of the threshold voltage variability S. Yamaguchi, H. Imi, S. Tokumaru, T. Kondo, H. Yamamoto, K. Nakamura Center for Microelectronic Systems, Kyushu Institute of Technology, Fukuoka, Japan DOI: 10.1109/ICMTS.2017.7954265 ABSTRACT: We developed VTSTs for 6T-SRAM and RL-SRAM and evaluated them to investigate the influences of SRAM operation by Vth fluctuation using measured FCMs and CΔVths. As a result, we successfully confirmed the superior immunity of Vth fluctuation of the RL-SRAM than the 6T-SRAM.	PDF Xplore
3.4	Ring-oscillator test-structures for sub-0.1% accuracy wafer-level characterization of active- and standby current consumption, variability, and fast aging of oscillation frequencies M. Vertregt, H. Tuinhout, N. Wils, A. Zegers, J. Croon NXP Semiconductors High Tech Campus, The Netherlands DOI: 10.1109/ICMTS.2017.7954266 ABSTRACT: This paper describes a set of ring oscillator test structures, with individually measurable static and dynamic supply currents, Nwell/Pwell leakage currents, and frequency. Purpose is to characterize frequency, leakage and aging and their variabilities, serving the stringent low-energy consumption requirements for IoT products. To obtain a comprehensive technology performance overview, these ring oscillator modules are realized in both GO1 (core oxide, four threshold flavors) and GO2 (I/O oxide, one threshold), either from inverters (mostly) or dual-input NAND/NOR cells, and with channel lengths varying from module to module.	PDF Xplore

Session 4: Device Modeling

4.1	Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI K. Pradeep, G. Gouget1, T. Poiroux2, P. Scheer3, A. Juge3, G. Ghibaudo IMEP-LAHC, MINATEC Campus, Grenoble, Cedex 1, France 1STMicroelectronics, Crolles, FR 2CEA-Leti, MINATEC Campus, Grenoble Cedex 9, France 3STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2017.7954267 ABSTRACT: In this work, robust methodologies for parameter extraction using split C-V measurements in FD-SOI structures are developed. These methods enable an automated and robust extraction procedure which is very important from an industrial perspective. The accuracy and robustness of the improved methods are verified using statistical measurements carried out on 28 nm FD-SOI devices and comparison with physical characterization.	PDF Xplore
4.2	True Kelvin CMOS Test Structure to achieve accurate and repeatable DC wafer-level measurements for device modelling applications C. B. Sia Cascade Microtech Inc. (A FormFactor Company), Singapore DOI: 10.1109/ICMTS.2017.7954268 ABSTRACT: A 6-pad True Kelvin Test Structure for advanced CMOS devices is proposed in this work. It allows test engineers to make very accurate and repeatable wafer-level measurements required for SPICE modelling applications. This design helps to overcome parasitic resistance of the probe holder and probe which is found to be dependent on test temperatures. It also mitigates increase in probe contact resistance due to oxidation of exposed underlying copper on aluminum capped test pads as a result of repeated probing at elevated temperatures. Most important of all, it enables accurate device measurements with minimal probe scrub, essential for 30 micrometers or less test pads, without the need for frequent probe tip cleaning.	PDF Xplore
4.3	Impact of access resistance on New-Y function methodology for MOSFET parameter extraction in advanced FD-SOI technology J. -B. Henry, A. Cros, J. Rosa, Q. Rafhay1, G. Ghibaudo1 STMicroelectronics, TR&D/STD/TPS/SiRel, Crolles, France 1IMEP-LAHC, MINATEC Campus, Grenoble, France DOI: 10.1109/ICMTS.2017.7954269 ABSTRACT: In this work, an upgraded version of the so called New Y function MOSFET parameter extraction methodology is proposed, taking the impact of access resistance into account. This new approach emphasizes the importance of considering access resistance variation with gate bias when extracting MOSFET parameters.	PDF Xplore
4.4	Input capacitance determination of power MOSFETs from switching trajectories K. Oishi, M. Shintani, M. Hiromoto, T. Sato Graduate School of Informatics, Kyoto University, Sakyo, Kyoto, Japan DOI: 10.1109/ICMTS.2017.7954270 ABSTRACT: A novel method for determining input capacitance of power MOSFETs is proposed. Through measurements of gate charge transfer trajectories during switching, gate-source capacitance and drain-gate capacitance are determined. The capacitance models obtained by the proposed method simulate switching waveforms accurately and reduce timing errors by more than 16 times when compared to the conventional model characterized through the small-signal measurements.	PDF Xplore

Session 5: RF and HV Device Characterization

5.1	A 130 to 170 GHz integrated noise source based on avalanche silicon Schottky diode in BiCMOS 55 nm for in-situ noise characterization J. C. A. Goncalves, T. Quemerais1, D. Gloria2, G. Avenier2, S. Lepilliet, G. Ducournau3, C. Gaquière, F. Danneville Liemn, UMR CNRS 8520, Villeneuve-d'Ascq, France 1STMicroelectronics, Grenoble, France 2STMicroelectronics, Crolles, France 3Institut d'Electronique de Microelectronique et de Nanotechnologie, Villeneuve-d'Ascq, Hauts-de-France, FR DOI: 10.1109/ICMTS.2017.7954271 ABSTRACT: In this paper, an integrated noise source realized with silicon Schottky diodes is presented. To this aim, dedicated test structures have been designed and characterized; the corresponding Schottky diodes feature an avalanche breakdown voltage close to −6 V. When biased around this breakdown voltage (their anode is grounded), an adjustable Excess Noise Ratio, ranging between 4 dB to 20 dB, was achieved in D-band. Hence, because of its ability to be integrated within a Si process, one can strongly expect the use of this solid state noise source for high frequency in-situ noise characterization of advanced Si CMOS or BiCMOS technologies, with the aim to target millimeter-wave applications.	PDF Xplore
5.2	Design of a Broadband CMOS RF Power Amplifier to establish device-circuit aging correlations E. Barajas, D. Mateo, X. Aragones, A. Crespo-Yepes1, R. Rodriguez1, J. Martin-Martinez1, M. Nafria1 Dept. Enginyeria Electrònica, Universitat Politècnica de Catalunya (UPC), Barcelona, Spain 1Dept. Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB), Barcelona, Spain DOI: 10.1109/ICMTS.2017.7954272 ABSTRACT: This paper presents the design of a Broadband CMOS RF Power Amplifier, suitable to be stressed at circuit level but with the possibility to be measured both at circuit and at device level. It allows establishing a relation between the degradation of circuit's RF performances and those of its individual devices parameters. The test structure, measurement set-up and procedure are described in detail.	PDF Xplore
5.3	DC and RF characterization of RF MOSFET embedding structure A. Takeshige, K. Katayama, S. Amakawa, K. Takano, T. Yoshida, M. Fujishima Graduate School of Advanced Sciences of Matter, Hiroshima University, Hiroshima, Japan DOI: 10.1109/ICMTS.2017.7954273 ABSTRACT: It is not so easy to correlate DC Kelvin measurement data of an RF transistor and its non-Kelvin RF measurement data, because the actual bias voltages in the latter are not known precisely. Knowing the bias voltages requires accurate characterization of its embedding structure. This paper reports on an attempt at correlating DC and RF measurements of parasitic resistances associated with a MOSFET test structure, including a transmission line, on a CMOS chip.	PDF Xplore
5.4	High voltage MOSFETs integration on advanced CMOS technology: Characterization of thick gate oxides incorporating high k metal gate stack from logic core process D. Morillon, F. Julien1, J. Coignus2, A. Toffoli2, L. Welter1, C. Jahan2, J. -P. Reynard1, E. Richard1, P. Masson3 EpOC/Nice Sophia-Antipolis University, Biot, France 1STMicroelectronics, France 2CEA LETI, Grenoble, France 3Universite de Nice Sophia Antipolis, Nice, Provence-Alpes-Cote d'Azu, FR DOI: 10.1109/ICMTS.2017.7954274 ABSTRACT: This paper presents the performance and reliability evaluation of high voltage MOS gate stacks integrated in an advanced CMOS technology platform. The aim of this study is to evaluate the compatibility of a thick silicon dioxide with a high-k metal gate stack which replaces the standard polysilicon gate. Using capacitors, physical, electrical, and reliability characterizations are carried out and TiN metal gate is found to be a potential issue as it induces a high density of interfacial traps. Despite these traps, oxide lifetime could still meet demanding requirements. Thus, using the high-k metal gate stack on top of a thick SiO2 gate oxide could be a potential solution for high voltage transistors integration on advanced CMOS platforms with embedded non-volatile memories.	PDF Xplore

Session 6: Array Testing and Mapping

6.1	An arrayed test structure for transistor damage assessment induced by circuit analysis and repairing processes with back-side-accessing Focused Ion Beam N. Usami, J. Kinoshita1, R. Ikeno2, Y. Okamoto, M. Tanno1, K. Asada2, Y. Mita3 Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan 1Van Partners, Toyota Tsusho Electronics Corporation, Tokyo, Japan 2VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan 3Dept. of Spacecraft Engineering, Institute of Space and Astronautical Science, Japan DOI: 10.1109/ICMTS.2017.7954275 ABSTRACT: We propose an arrayed test structure to assess the damages of metal-oxide-semiconductor field-effect transistors (MOSFETs) exposed under back-side LSI processes, such as by Focused Ion Beam (FIB). Back-side process with FIB is becoming essential to analyze and repair modern LSI chips, to avoid processing through many metal layers with dense wiring and dummy patterns. To access transistors from back-side, however, FET active region must be cropped out and that may cause damage to transistor characteristics. Our test structure consists of 2-D-arrayed MOSFETs. The impact by the back-side process on various conditions can be visualized as I-V characteristics change. The test structure was used with several FIB back-side processes and visualized the damages as threshold shift. The measurement indicated the importance of mixture of fast-and-isotropic etching and slow-and-anistoropic etching to miminimize electrical damage.	PDF Xplore
6.2	A new test vehicle for RRAM array characterization C. Nguyen, C. Cagli, L. Kadura, J. -F. Nodin, S. Bernasconi, G. Reimbold CEA-Leti, Grenoble, FRANCE DOI: 10.1109/ICMTS.2017.7954276 ABSTRACT: In this paper we present a new test vehicle designed for Resistive Random Access Memories (RRAM) arrays (from single bit to 1Mbits) characterization. The arrays structure, the decoders, and the selectors are explained as well as the electrical setup that drives the array decoders and performs the electrical characterization. Eventually, we discuss some electrical results concerning the switching voltage variability and show the performance of the test vehicle.	PDF Xplore
6.3	Development of an Advanced System for Automated 200 mm Wafer Mapping of Stress Using Test Structures S. Lokhandwala, J. Murray, S. Smith, A. R. Mount1, J. G. Terry, A. J. Walton Scottish Microelectronics Centre, The university of Edinburgh, Edinburgh, UK 1Joseph Black Building, The university of Edinburgh, UK DOI: 10.1109/ICMTS.2017.7954277 ABSTRACT: Controlling and understanding the stress in materials is of major importance in the successful fabrication of MEMS devices. Failure to properly account for stress related effects can lead to the substrate warping and layer delamination, both of which are detrimental to the performance and reliability of components. Hence, it is desirable to have reliable and automated technology to spatially monitor both stress and strain on silicon wafers. This paper reports in detail an integrated measurement system that has been specifically designed to semiautomatically wafer map stress, strain and Young's modulus. The measurement system is designed to determine the rotation of a test structure automatically and then calculate the strain. Young's modulus is then determined using a nanoindenter running customised software and the combination of the two measurements from the same location is used to calculate and map the spatial stress in the film.	PDF Xplore

Session 7: Sensor Test Structures

7.1	A test structure to characterize transparent electrode array platform with TFTs for bio-chemical applications A. Tixier-Mita, S. Ihida, G. Cathcart1, F. A. Shaik1, H. Fujita, Y. Mita2, H. Toshiyoshi3 Institute of Industrial Sciences, The university of Tokyo, Tokyo, Japan 1Research Center for Advanced Research Science and Technology, The University of Tokyo, Tokyo, Japan 2Department of Electrical Engineering and Information Systems, The university of Tokyo, Tokyo, Japan 3Tokyo Daigaku, Bunkyo-ku, Tokyo, JP DOI: 10.1109/ICMTS.2017.7954278 ABSTRACT: Test structures are proposed to characterize Thin-Film-Transistors in array that control a transparent electrode array platform, used for bio-chemical applications. The structures are post-processed electrodes that connect the source terminals of multiple TFTs. This characterization is essential to determine the limits, in terms of sensitivity and operation frequency in the case of impedance measurements on biological cells, as well to investigate other possible biological applications.	PDF Xplore
7.2	Test structures for the characterisation of sensor packaging technology E. O. Blair, A. Buchoux, A. Tsiamis1, C. Dunare, J. R. K. Marland1, J. G. Terry, S. Smith1, A. J. Walton Institute for Integrated Micro and Nano Systems 1Institute for Bioengineering School of Engineering, The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2017.7954279 ABSTRACT: This paper presents three test structures targeted at characterising sensor packaging materials for liquid environments. The test structures enable the evaluation of: 1) the successful removal of packaging material on sensing areas, 2) the permeability of the packaging material to its environment, 3) electrical continuity through the packaging process, and 4) the ingress of the liquid environment between the packaging material and the chip surface. The paper presents an example of the evaluation of a UV curable resin as packaging process for a biomedical sensor.	PDF Xplore
7.3	Test structures for optimizing polymer electrolyte performance in a microfabricated electrochemical oxygen sensor J. R. K. Marland, C. Dunare, A. Tsiamis, E. Gonzä¡lez-Fernä¡ndez1, E. O. Blair, S. Smith, J. G. Terry, A. F. Murray, A. J. Walton Schocl of Engineering, University of Edinburgh, Edinburgh, EH9 3FF, UK 1School of Chemistry, University of Edinburgh, Edinburgh, EH9 3FJ, UK DOI: 10.1109/ICMTS.2017.7954280 ABSTRACT: Test structures were produced for optimizing the design and fabrication of a patterned solid polymer electrolyte in an electrochemical oxygen sensor. Measurements showed that choice of photoresist developer and the underlying insulator material affected durability of the polymer structures. Test electrodes covered by the polymer were effective at supporting electrochemical oxygen detection.	PDF Xplore
7.4	Test structures for stepwise deformation sensing on super-flexible strain sensors C. Wang, B. B. Xu, J. G. Terry1, S. Smith1, A. J. Walton1, Y. Li Faculty of Engineering and Environment, Northumbria University, UK 1SMC, The university of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2017.7954281 ABSTRACT: Developing MEMS sensors with a high strain sensing range (up to 0.6) and a stepwise sensing mechanism could enable widespread downstream applications, by allowing intimate, mechanically conformable integration with soft biological tissues. Most approaches to date focus on challenges to associate the sensing mechanism with high peak strains under large deformation. By designing and characterizing test structures with multi-switching electrodes on super-flexible substrates, this research has established a strategy for stepwise strain-sensing mechanism based on elastic instabilities. The growing and co-existence of wrinkles and creases on multiple electrodes with different dimensions are observed under lateral strains ranging between 0.3 and 0.6. Initial electrical measurements of the multi-switching mechanism has been demonstrated with a two stage resistance value change observed under changing compressive strain. Further investigation will focus on the device optimization and mechano-electrical signal processing.	PDF Xplore

Session 8: Low Frequency Noise Characterization

8.1	A statistical modeling methodology of RTN gate size dependency based on skewed ring oscillators A. K. M. M. Islam, T. Nakai1, H. Onodera1 Institute of Industrial Science, The University of Tokyo, Tokyo, JAPAN 1Graduate School of Informatics, Kyoto University, Kyoto, JAPAN DOI: 10.1109/ICMTS.2017.7954282 ABSTRACT: This paper proposes a statistical modeling methodology of RTN (Random Telegraph Noise) gate size dependency utilizing skewed ring oscillator (RO) structures. An iterative characterization flow is developed to estimate RTN induced threshold distribution of each gate sizes of pMOSFET and nMOSFET independently. The skewed RO based test structure was fabricated in a 65 nm SOTB (Silicon On Thin Body) process. It is observed that Lognormal distribution represents RTN induced delay distribution well. RTN model of gate size dependency is then developed and validated using the measured data. Model based delay distribution estimation and measurement match well. The proposed extraction methodology is thus suitable for estimating RTN of transistors with arbitrary gate size. The model helps reliability and worst case analysis of digital circuits where transistors of various gate sizes are used.	PDF Xplore
8.2	A variability-based analysis technique revealing physical mechanisms of MOSFET low-frequency noise T. H. Both, J. A. Croon, M. B. da Silva1, H. P. Tuinhout, A. Z. -v. Duijnhoven, A. J. Scholten, G. I. Wirth1 NXP Semiconductors, Eindhoven, The Netherlands 1Universidade Federal do Rio Grande do Sul, Programa de Pós-Graduaä§ä£o em Microeletrônica (PGMicro), Porto Alegre, Brazil DOI: 10.1109/ICMTS.2017.7954283 ABSTRACT: This paper presents a technique for statistical analysis of MOSFET low-frequency noise (LFN) based on the autocorrelation coefficient of numerous LFN power spectral density (PSD) spectra. This correlation analysis reveals information about physical mechanisms behind 1/Æ’ noise that is difficult to obtain otherwise. The methodology also enables quantification and validation of old and new statistical LFN models. Numerous PSD spectra from contemporary mixed-signal CMOS technologies were analysed; the results reinforce the idea that the 1/Æ’ noise in MOSFETs has a trapping-related origin.	PDF Xplore
8.3	Statistical low-frequency noise characterization in sub-15 nm Si/SiGe nanowire Trigate pMOSFETs C. G. Theodorou, R. Lavieville, T. A. Karatsori, S. Barraud1, C. A. Dimitriadis2, G. Ghibaudo IMEP-LAHC, Univ. Grenoble Alpes, Grenoble, France 1CEA-LETI, Univ. Grenoble Alpes, Grenoble, France 2Department of Physics, Aristotle university of Thessaloniki, Greece DOI: 10.1109/ICMTS.2017.7954284 ABSTRACT: A detailed statistical characterization of the drain current low-frequency noise (LFN) in sub-15 nm Si/SiGe Trigate NW pMOSFETs is presented. The slow oxide trap density and distribution, as well as the correlated mobility fluctuations effect are probed for several channel geometries. The LFN variability scaling is also presented and compared to established nano-scale planar CMOS technologies. Our results indicate that such devices demonstrate relatively good gate oxide interface quality and LFN variability levels, despite their very aggressive dimensions and not yet optimized fabrication process.	PDF Xplore
8.4	Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs M. Bucher, A. Nikolaou, N. Mavredakis, N. Makris, M. Coustans1, J. Lolivier2, P. Habas2, A. Acovic2, R. Meyer2 School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece 1Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland 2EM Microelectronic-Marin SA, Marin-Epagnier, Switzerland DOI: 10.1109/ICMTS.2017.7954285 ABSTRACT: Variability of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) is an important concern for many analog CMOS integrated circuits. In this paper, transistors with enclosed gate layout are examined and compared with standard layout transistors, with particular emphasis on weak inversion region. Enclosed gate transistors show an improved gate voltage mismatch in weak inversion. A compact MOSFET model for LFN and its variability, based on number fluctuation theory, is shown to cover well the behavior of either type of transistors. Lower levels of noise as well as lower variability of noise are observed in enclosed gate transistors.	PDF Xplore

Session 9: Novel Device Architecture Characterization

9.1	A microsecond time resolved current collapse test setup dedicated to GaN-based Schottky diode characterization T. Lorin, W. Van Den Daele, C. Gillot, M. Charles, J. Biscarrat, M. Plissonnier, G. Ghibaudo1, G. Reimbold CEA, MINATEC Campus, Grenoble, France 1IMEP-LAHC, Universitä© Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS.2017.7954286 ABSTRACT: This paper presents a test setup to characterize current collapse effects in power diodes such as GaN-based Schottky junctions. The setup principle and its main parts are described. Current/voltage transients can be recorded very shortly (2 microseconds on wafer prober) after reverse to forward switching. The related trapping effects are analyzed through temperature dependent measurements.	PDF Xplore
9.2	Novel C-V measurements based method for the extraction of GaN buffer layer residual doping level in HEMT I. Nifa, C. Leroux, A. Torres, M. Charles, G. Reimbold, G. Ghibaudo1, E. Bano1 Univ. Grenoble Alpes 1IMEP-LAHC, MINATEC/INPG, Grenoble, France DOI: 10.1109/ICMTS.2017.7954287 ABSTRACT: This paper presents a new methodology to characterize the GaN buffer doping level which is a critical parameter for epitaxial fabrication of GaN wafers. As demonstrated in this study, its characterization is challenging due to parasitic effects. Capacitance-Voltage (C-V) measurements are carried out on a Metal Insulator Semiconductor (MIS) structure with a gate on Al2O3 dielectric using a novel configuration. The experimental study is validated with a self-consistent Poisson-Schrodinger (PS) simulation. Finally, our methodology is applied to a new generation of GaN buffer through a fully and partially (without any contacts) processed wafer, with a Hg-probe C-V measurement performed on the partially processed one.	PDF Xplore
9.3	Test structure configurations for analysis of field effect influenced self-heating and thermal coupling in High Voltage SiGe HBTs B. Ó. hAnnaidh, E. Coyne, B. Lane Process Development, Raheen Industrial Estate, Limerick, Ireland DOI: 10.1109/ICMTS.2017.7954288 ABSTRACT: This paper presents several test structure configurations that facilitate a comprehensive assessment of self-heating and thermal coupling effects in High Voltage SiGe HBTs in a DTI on SOI process. Several layout test structures are investigated including variations in device separations, multi-device arrays and the influence of the substrate contact in the regions outside the trench isolation, and indeed the potential for trench field effects themselves, the latter two both due to the high voltages involved. The findings are reported with a view to focus on a Compact Modelling solution implementable in a commercial CAD tool.	PDF Xplore
9.4	Test structures for nano-gap fabrication process development for nano-electromechanical systems S. Smith, Y. Takeshiro1, Y. Okamoto1, J. G. Terry2, A. J. Walton2, R. Ikeno3, K. Asada3, Y. Mita1 Institute for Bioengineering, The University of Edinburgh, UK 1Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan 2Institute for Integrated Micro and Nano Systems, The University of Edinburgh, UK 3VLSI Design and Education Centre, The University of Tokyo, Japan DOI: 10.1109/ICMTS.2017.7954289 ABSTRACT: Nanometre scale pores, gaps or trenches are of significant interest for a number of applications in nano and microsystems, including biosensors, nanofluidic devices and mechanical resonators. This paper presents the design of two test structure chips for the development of a process capable of the fabrication of controllable nanoscale trenches or gaps. This process uses uses standard microfabrication technologies, without the need for nano-scale lithography. Initial results from the first test chip have suggested design rules for pattern density and feature size for the process, which relies on chemical mechanical planarisation of polysilicon. These results have been used to inform the design of a second test chip which includes mechanical and electrical test structures. Initial results show that HF etch rate of a nanoscale silicon oxide used as a sacrificial layer can be very high, even for the very high aspect ratio features in this process.	PDF Xplore

By First Author

1.4	Electrical test structures for verifying continuity of ultra-thin insulating and conducting films S. Banerjee, R. van der Velde, M. Yang, J. Schmitz, A. Y. Kovalgin1 MESA+ Institute for Nanotechnology, University of Twente, Enschede, AE, The Netherlands 1Universiteit Twente, Enschede, Overijssel, NL DOI: 10.1109/ICMTS.2017.7954258 HOVER FOR ABSTRACT	PDF Xplore
5.2	Design of a Broadband CMOS RF Power Amplifier to establish device-circuit aging correlations E. Barajas, D. Mateo, X. Aragones, A. Crespo-Yepes1, R. Rodriguez1, J. Martin-Martinez1, M. Nafria1 Dept. Enginyeria Electrònica, Universitat Politècnica de Catalunya (UPC), Barcelona, Spain 1Dept. Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB), Barcelona, Spain DOI: 10.1109/ICMTS.2017.7954272 HOVER FOR ABSTRACT	PDF Xplore
7.2	Test structures for the characterisation of sensor packaging technology E. O. Blair, A. Buchoux, A. Tsiamis1, C. Dunare, J. R. K. Marland1, J. G. Terry, S. Smith1, A. J. Walton Institute for Integrated Micro and Nano Systems 1Institute for Bioengineering School of Engineering, The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2017.7954279 HOVER FOR ABSTRACT	PDF Xplore
2.4	Test structures for understanding the impact of ultra-high vacuum metal deposition on top-gate MoS2 field-effect-transistors P. Bolshakov, P. Zhao, C. M. Smyth, A. Azcatl, R. M. Wallace, C. D. Young, P. K. Hurley1 Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX, USA 1Tyndall National Institute, University College Cork, Dyke Parade, Cork, Ireland DOI: 10.1109/ICMTS.2017.7954262 HOVER FOR ABSTRACT	PDF Xplore
8.2	A variability-based analysis technique revealing physical mechanisms of MOSFET low-frequency noise T. H. Both, J. A. Croon, M. B. da Silva1, H. P. Tuinhout, A. Z. -v. Duijnhoven, A. J. Scholten, G. I. Wirth1 NXP Semiconductors, Eindhoven, The Netherlands 1Universidade Federal do Rio Grande do Sul, Programa de Pós-Graduaä§ä£o em Microeletrônica (PGMicro), Porto Alegre, Brazil DOI: 10.1109/ICMTS.2017.7954283 HOVER FOR ABSTRACT	PDF Xplore
8.4	Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs M. Bucher, A. Nikolaou, N. Mavredakis, N. Makris, M. Coustans1, J. Lolivier2, P. Habas2, A. Acovic2, R. Meyer2 School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece 1Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland 2EM Microelectronic-Marin SA, Marin-Epagnier, Switzerland DOI: 10.1109/ICMTS.2017.7954285 HOVER FOR ABSTRACT	PDF Xplore
1.3	Dealing with leakage current in TLM and CTLM structures with vertical junction isolation S. N. Bystrova, S. M. Smits, J. H. Klootwijk1, R. A. M. Wolters, A. Y. Kovalgin, L. K. Nanver2, J. Schmitz MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands 1Philips Research, Enschede, The Netherlands 2Aalborg University, Aalborg, Denmark DOI: 10.1109/ICMTS.2017.7954257 HOVER FOR ABSTRACT	PDF Xplore
3.2	Measurement of mismatch factor and noise of SRAM PUF using small bias voltage Ziyang Cui, Baikun Zheng, Yanhao Piao, Shiyu Liu, Ronghao Xie, H. Shinohara Graduate School of Information, Production and Systems, Waseda University, Fukuoka, Japan DOI: 10.1109/ICMTS.2017.7954264 HOVER FOR ABSTRACT	PDF Xplore
5.1	A 130 to 170 GHz integrated noise source based on avalanche silicon Schottky diode in BiCMOS 55 nm for in-situ noise characterization J. C. A. Goncalves, T. Quemerais1, D. Gloria2, G. Avenier2, S. Lepilliet, G. Ducournau3, C. Gaquière, F. Danneville Liemn, UMR CNRS 8520, Villeneuve-d'Ascq, France 1STMicroelectronics, Grenoble, France 2STMicroelectronics, Crolles, France 3Institut d'Electronique de Microelectronique et de Nanotechnologie, Villeneuve-d'Ascq, Hauts-de-France, FR DOI: 10.1109/ICMTS.2017.7954271 HOVER FOR ABSTRACT	PDF Xplore
4.3	Impact of access resistance on New-Y function methodology for MOSFET parameter extraction in advanced FD-SOI technology J. -B. Henry, A. Cros, J. Rosa, Q. Rafhay1, G. Ghibaudo1 STMicroelectronics, TR&D/STD/TPS/SiRel, Crolles, France 1IMEP-LAHC, MINATEC Campus, Grenoble, France DOI: 10.1109/ICMTS.2017.7954269 HOVER FOR ABSTRACT	PDF Xplore
8.1	A statistical modeling methodology of RTN gate size dependency based on skewed ring oscillators A. K. M. M. Islam, T. Nakai1, H. Onodera1 Institute of Industrial Science, The University of Tokyo, Tokyo, JAPAN 1Graduate School of Informatics, Kyoto University, Kyoto, JAPAN DOI: 10.1109/ICMTS.2017.7954282 HOVER FOR ABSTRACT	PDF Xplore
1.2	Test structures for studying flexible interconnect supported by carbon nanotube scaffolds D. Jiang, S. Sun, M. Edwards, K. Jeppson Department of Microtechnology and Nanoscience, Electronics Materials and Systems Laboratory, Gothenburg, Sweden DOI: 10.1109/ICMTS.2017.7954256 HOVER FOR ABSTRACT	PDF Xplore
3.1	Statistical characterization and modeling of drain current local and global variability in 14 nm bulk FinFETs T. Karatsori, C. Theodorou, R. Lavieville, T. Chiarella1, J. Mitard1, N. Horiguchi1, C. A. Dimitriadis2, G. Ghibaudo IMEP-LAHC, Univ. Grenoble Alpes, Minatec, Grenoble, France 1IMEC, Leuven, Belgium 2Department of Physics, Aristotle University of Thessaloniki, Greece DOI: 10.1109/ICMTS.2017.7954263 HOVER FOR ABSTRACT	PDF Xplore
6.3	Development of an Advanced System for Automated 200 mm Wafer Mapping of Stress Using Test Structures S. Lokhandwala, J. Murray, S. Smith, A. R. Mount1, J. G. Terry, A. J. Walton Scottish Microelectronics Centre, The university of Edinburgh, Edinburgh, UK 1Joseph Black Building, The university of Edinburgh, UK DOI: 10.1109/ICMTS.2017.7954277 HOVER FOR ABSTRACT	PDF Xplore
9.1	A microsecond time resolved current collapse test setup dedicated to GaN-based Schottky diode characterization T. Lorin, W. Van Den Daele, C. Gillot, M. Charles, J. Biscarrat, M. Plissonnier, G. Ghibaudo1, G. Reimbold CEA, MINATEC Campus, Grenoble, France 1IMEP-LAHC, Universitä© Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS.2017.7954286 HOVER FOR ABSTRACT	PDF Xplore
1.1	Characterization and monitoring structures for robustness against cyclic thermomechanical stress: Design and influence of Ti-Al(Cu) layer scheme A. Mann, H. Lohmeyer, Y. Joseph1 Robert Bosch GmbH Automotive Electronics, Reutlingen, Germany 1Technische Universität Bergakademie Freiberg, Institute of Electronic and Sensor Materials, Freiberg, Germany DOI: 10.1109/ICMTS.2017.7954255 HOVER FOR ABSTRACT	PDF Xplore
7.3	Test structures for optimizing polymer electrolyte performance in a microfabricated electrochemical oxygen sensor J. R. K. Marland, C. Dunare, A. Tsiamis, E. Gonzä¡lez-Fernä¡ndez1, E. O. Blair, S. Smith, J. G. Terry, A. F. Murray, A. J. Walton Schocl of Engineering, University of Edinburgh, Edinburgh, EH9 3FF, UK 1School of Chemistry, University of Edinburgh, Edinburgh, EH9 3FJ, UK DOI: 10.1109/ICMTS.2017.7954280 HOVER FOR ABSTRACT	PDF Xplore
5.4	High voltage MOSFETs integration on advanced CMOS technology: Characterization of thick gate oxides incorporating high k metal gate stack from logic core process D. Morillon, F. Julien1, J. Coignus2, A. Toffoli2, L. Welter1, C. Jahan2, J. -P. Reynard1, E. Richard1, P. Masson3 EpOC/Nice Sophia-Antipolis University, Biot, France 1STMicroelectronics, France 2CEA LETI, Grenoble, France 3Universite de Nice Sophia Antipolis, Nice, Provence-Alpes-Cote d'Azu, FR DOI: 10.1109/ICMTS.2017.7954274 HOVER FOR ABSTRACT	PDF Xplore
6.2	A new test vehicle for RRAM array characterization C. Nguyen, C. Cagli, L. Kadura, J. -F. Nodin, S. Bernasconi, G. Reimbold CEA-Leti, Grenoble, FRANCE DOI: 10.1109/ICMTS.2017.7954276 HOVER FOR ABSTRACT	PDF Xplore
9.2	Novel C-V measurements based method for the extraction of GaN buffer layer residual doping level in HEMT I. Nifa, C. Leroux, A. Torres, M. Charles, G. Reimbold, G. Ghibaudo1, E. Bano1 Univ. Grenoble Alpes 1IMEP-LAHC, MINATEC/INPG, Grenoble, France DOI: 10.1109/ICMTS.2017.7954287 HOVER FOR ABSTRACT	PDF Xplore
4.4	Input capacitance determination of power MOSFETs from switching trajectories K. Oishi, M. Shintani, M. Hiromoto, T. Sato Graduate School of Informatics, Kyoto University, Sakyo, Kyoto, Japan DOI: 10.1109/ICMTS.2017.7954270 HOVER FOR ABSTRACT	PDF Xplore
2.2	The outstanding properties of graphene-insulator-semiconductor (GIS) test structures for photoelectric determination of semiconductor devices band diagram K. Piskorski, V. Passi1, J. Ruhkopf1, M. C. Lemme1, H. M. Przewlocki Institute of Electron Technology, Warsaw, Poland 1University of Siegen, Siegen, Germany DOI: 10.1109/ICMTS.2017.7954260 HOVER FOR ABSTRACT	PDF Xplore
4.1	Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI K. Pradeep, G. Gouget1, T. Poiroux2, P. Scheer3, A. Juge3, G. Ghibaudo IMEP-LAHC, MINATEC Campus, Grenoble, Cedex 1, France 1STMicroelectronics, Crolles, FR 2CEA-Leti, MINATEC Campus, Grenoble Cedex 9, France 3STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2017.7954267 HOVER FOR ABSTRACT	PDF Xplore
4.2	True Kelvin CMOS Test Structure to achieve accurate and repeatable DC wafer-level measurements for device modelling applications C. B. Sia Cascade Microtech Inc. (A FormFactor Company), Singapore DOI: 10.1109/ICMTS.2017.7954268 HOVER FOR ABSTRACT	PDF Xplore
9.4	Test structures for nano-gap fabrication process development for nano-electromechanical systems S. Smith, Y. Takeshiro1, Y. Okamoto1, J. G. Terry2, A. J. Walton2, R. Ikeno3, K. Asada3, Y. Mita1 Institute for Bioengineering, The University of Edinburgh, UK 1Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan 2Institute for Integrated Micro and Nano Systems, The University of Edinburgh, UK 3VLSI Design and Education Centre, The University of Tokyo, Japan DOI: 10.1109/ICMTS.2017.7954289 HOVER FOR ABSTRACT	PDF Xplore
5.3	DC and RF characterization of RF MOSFET embedding structure A. Takeshige, K. Katayama, S. Amakawa, K. Takano, T. Yoshida, M. Fujishima Graduate School of Advanced Sciences of Matter, Hiroshima University, Hiroshima, Japan DOI: 10.1109/ICMTS.2017.7954273 HOVER FOR ABSTRACT	PDF Xplore
8.3	Statistical low-frequency noise characterization in sub-15 nm Si/SiGe nanowire Trigate pMOSFETs C. G. Theodorou, R. Lavieville, T. A. Karatsori, S. Barraud1, C. A. Dimitriadis2, G. Ghibaudo IMEP-LAHC, Univ. Grenoble Alpes, Grenoble, France 1CEA-LETI, Univ. Grenoble Alpes, Grenoble, France 2Department of Physics, Aristotle university of Thessaloniki, Greece DOI: 10.1109/ICMTS.2017.7954284 HOVER FOR ABSTRACT	PDF Xplore
7.1	A test structure to characterize transparent electrode array platform with TFTs for bio-chemical applications A. Tixier-Mita, S. Ihida, G. Cathcart1, F. A. Shaik1, H. Fujita, Y. Mita2, H. Toshiyoshi3 Institute of Industrial Sciences, The university of Tokyo, Tokyo, Japan 1Research Center for Advanced Research Science and Technology, The University of Tokyo, Tokyo, Japan 2Department of Electrical Engineering and Information Systems, The university of Tokyo, Tokyo, Japan 3Tokyo Daigaku, Bunkyo-ku, Tokyo, JP DOI: 10.1109/ICMTS.2017.7954278 HOVER FOR ABSTRACT	PDF Xplore
2.3	Electromechanical testing of ZnO thin films under high uniaxial strain R. Tuyaerts, J. -P. Raskin1, J. Proost Universite catholique de Louvain, Louvain-la-Neuve, BE 1Institute of Information and Communication Technologies, Universit catholique de Louvain, Louvain-la-Neuve, Belgium DOI: 10.1109/ICMTS.2017.7954261 HOVER FOR ABSTRACT	PDF Xplore
6.1	An arrayed test structure for transistor damage assessment induced by circuit analysis and repairing processes with back-side-accessing Focused Ion Beam N. Usami, J. Kinoshita1, R. Ikeno2, Y. Okamoto, M. Tanno1, K. Asada2, Y. Mita3 Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan 1Van Partners, Toyota Tsusho Electronics Corporation, Tokyo, Japan 2VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan 3Dept. of Spacecraft Engineering, Institute of Space and Astronautical Science, Japan DOI: 10.1109/ICMTS.2017.7954275 HOVER FOR ABSTRACT	PDF Xplore
2.1	Detailed characterization and critical discussion of series resistance in graphene-metal contacts S. Venica, F. Driussi1, A. Gahoi, V. Passi, P. Palestri1, M. C. Lemme, L. Selmi1 University of Siegen, School of Science and Technology, Siegen, Germany 1Universitä¡ degli Studi di Udine, Dipartimento Politecnico di Ingegneria e Architettura (DPIA), Udine, Italy DOI: 10.1109/ICMTS.2017.7954259 HOVER FOR ABSTRACT	PDF Xplore
3.4	Ring-oscillator test-structures for sub-0.1% accuracy wafer-level characterization of active- and standby current consumption, variability, and fast aging of oscillation frequencies M. Vertregt, H. Tuinhout, N. Wils, A. Zegers, J. Croon NXP Semiconductors High Tech Campus, The Netherlands DOI: 10.1109/ICMTS.2017.7954266 HOVER FOR ABSTRACT	PDF Xplore
7.4	Test structures for stepwise deformation sensing on super-flexible strain sensors C. Wang, B. B. Xu, J. G. Terry1, S. Smith1, A. J. Walton1, Y. Li Faculty of Engineering and Environment, Northumbria University, UK 1SMC, The university of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2017.7954281 HOVER FOR ABSTRACT	PDF Xplore
3.3	Vth-shiftable SRAM cell TEGs for direct measurement for the immunity of the threshold voltage variability S. Yamaguchi, H. Imi, S. Tokumaru, T. Kondo, H. Yamamoto, K. Nakamura Center for Microelectronic Systems, Kyushu Institute of Technology, Fukuoka, Japan DOI: 10.1109/ICMTS.2017.7954265 HOVER FOR ABSTRACT	PDF Xplore
9.3	Test structure configurations for analysis of field effect influenced self-heating and thermal coupling in High Voltage SiGe HBTs B. Ó. hAnnaidh, E. Coyne, B. Lane Process Development, Raheen Industrial Estate, Limerick, Ireland DOI: 10.1109/ICMTS.2017.7954288 HOVER FOR ABSTRACT	PDF Xplore