IEEE International Conference on Microelectronic Test Structures

ICMTS 2016 Program

2016 Program Booklet

By Session

1.1	An efficient method to evaluate 4 million micro-bump interconnection resistances for 3D stacked 16-mpixel image sensor Y. Takemoto, H. Kato, T. Kondo, N. Takazawa, M. Tsukimura, H. Saito, K. Kobayashi, J. Aoki, S. Suzuki, Y. Gomi, S. Matsuda, Y. Tadaki Imager and Analog LSI technology Department, Olympus Corporation, Hachioji-shi, Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476162 ABSTRACT: We developed an efficient method for evaluating the 4 million micro-bump interconnection resistances of the 3D stacked 16-Mpixel CMOS image sensor by including vertical scanning and readout circuits and extra circuits in both of two substrates for a resistance testing mode, which enables us not only to find failed bumps but also to evaluate the resistances by scanning all micro bumps. We measured the resistances of the interconnections ranging from 50 to 500 kΩ with a resolution of 50kΩ.	PDF Xplore
1.2	An end-point visualization test structure for all plasma dry release of Deep-RIE MEMS Y. Okamoto, E. Lebrasseur, I. Mori, Y. Mita Department of Electrical Engineering The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476163 ABSTRACT: We propose a test structure for an easy visual check of the progress of a MEMS dry release process. The release process of MEMS on a silicon-on-insulator (SOI) wafer is done by plasma etching of the silicon substrate (SOI handle). The Si MEMS movable structure is protected from etching by the underneath buried oxide (BOX) layer and by a Teflon layer on the walls. Improper etching conditions, however, damage the Teflon layer and harm MEMS structure. Therefore, a check method of the progress of process is essential to release MEMS structure successfully. The test structure has two purposes. First, it enables the detection of the completion of the release process. Second, it helps determining the undercut speed according to the opening sizes and plasma conditions.	PDF Xplore
1.3	Spring-constant measurement methods for RF-MEMS capacitive switches J. Wang, J. Bielen¹, C. Salm, J. Schmitz The MESA+ Institute for Nanotechnology, University of Twente, Netherlands ¹EPCOS Netherlands, Netherlands DOI: 10.1109/ICMTS.2016.7476164 ABSTRACT: In this article we compare three approaches to measure the spring constant in RF MEMS capacitive switches. We use the lowest vibration mode, as obtained from vibrometry; the pull-in voltage; and the low-field capacitance-voltage curve of the device to extract the spring constant. Experimental results are presented for each approach, and FEM model predictions are used to further verify and interpret the findings. Pros and cons of each method are discussed.	PDF Xplore
1.4	Microfabricated test structures for thermal gas sensor M. Denoual, M. Pouliquen, D. Robbes, O. de Sagazan¹, J. Grand¹, H. Awala¹, S. Mintova², S. Inoue³, A. Mita-Tixier³, Y. Mita³ GREYC-CNRS, ENSICAEN, France ¹LCS-CNRS, University of Caen, France ²IETR, University of Rennes, France ³Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476165 ABSTRACT: Microfabricated test structures are presented for the proof validation of a new chemical sensor concept. The proposed detection principle is based on time constant shift of a thermal device covered with zeolites when target species are adsorbed.	PDF Xplore

Session 2: Thermal Issues

2.1	A test structure for analysis of metal wire effect on temperature distribution in stacked IC T. Matsuda, H. Demachi, H. Iwata, T. Hatakeyama, T. Ohzone¹ Toyama Prefectural University, Toyama, Japan ¹Dawn Enterprise, Nagoya, Japan DOI: 10.1109/ICMTS.2016.7476167 ABSTRACT: A test structure for analysis of temperature distributions and effects of metal wires on thermal properties in stacked IC is presented. The effects on the temperature distributions and transient phenomena in the single die and the stacked ICs were analyzed. The heat transfer in the metal wires affects the temperature distributions, which are consistent with the thermal simulation results. The test structure can provide an effective way for analysis of thermal properties in various LSIs.	PDF Xplore
2.2	Dedicated test-structures for investigation of the thermal impact of the BEOL in advanced SiGe HBTs in time and frequency domain R. D'Esposito, S. Fregonese, T. Zimmer, A. Chakravorty¹ CNRS-UMR 5218, Université de Bordeaux ¹Department of Electrical Engineering, IIT Madras, Chennai, India DOI: 10.1109/ICMTS.2016.7476168 ABSTRACT: This paper presents a study on the thermal impact of the back-end-of-line (BEOL) in a state-of-the-art SiGe HBT technology for high power applications. A recursive RC network is proposed to model the thermal behavior of the BEOL and is validated with measurements on dedicated test-structures in the time and frequency domain.	PDF Xplore
2.3	Hotspot test structures for evaluating carbon nanotube microfin coolers and graphene-like heat spreaders K. Jeppson, J. Bao¹, S. Huang¹, Y. Zhang, S. Sun, Y. Fu², J. Liu Chalmers University of Technology, Gothenburg, Sweden ¹Chalmers University of Technology, SHT Smart High Tech, Gothenburg, Sweden ²Shanghai University SMIT Center, Jiading Campus, Shanghai, China DOI: 10.1109/ICMTS.2016.7476169 ABSTRACT: The design, fabrication, and use of a hotspot-producing and temperature-sensing test structure for evaluating the thermal properties of carbon nanotubes, graphene and boron nitride for cooling of electronic devices in applications like 3D integrated chip-stacks, power amplifiers and light-emitting diodes is described. The test structure is a simple meander-shaped metal resistor serving both as the hotspot and the temperature thermo-meter. By use of this test structure, the influence of emerging materials like those mentioned above on the temperature of the hotspot has been evaluated with good accuracy (±0.5°C).	PDF Xplore
2.4	Transistor self-heating correction and thermal conductance extraction using only DC data C. C. McAndrew, A. Lorenzo-Cassagnes, O. L. Hartin¹ NXP Semiconductors, Tempe, AZ ¹Arizona State University, Tempe, AZ DOI: 10.1109/ICMTS.2016.7476170 ABSTRACT: This paper presents a simple technique to correct measured transistor output characteristics for the effect of self-heating. The advantage of the proposed technique is that, unlike previous methods, it does not require special test structures, but can be applied to DC data measured from standard transistor DC measurement test structures. The technique also quantifies the thermal conductance gth. The accuracy of the technique is verified by comparison with TCAD simulations, both including and excluding self-heating, and with measured data.	PDF Xplore

Session 3: Arrayed Test Structures

3.1	Random telegraph noise measurement and analysis based on arrayed test circuit toward high S/N CMOS image sensors R. Kuroda, A. Teramoto¹, S. Sugawa¹ Graduate School of Engineering, Tohoku University, Sendai, Japan ¹New Industry Creation Hatchery Center, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS.2016.7476172 ABSTRACT: Using the developed array test circuit, both static and temporal electrical characteristics of over million transistors/shot were measured with the accuracy of 60 μVrms to analyze and reduce random telegraph noise (RTN) toward high S/N CMOS image sensors. Statistical evaluation results of RTN parameters such as time constants and amplitude and their behaviors toward transistor device structures and operation conditions are summarized. Application to high S/N CMOS image sensor is also described.	PDF Xplore
3.2	Proposal of a new array structure to enable the detection of soft failure and the aging test with overcurrent of resistive element S. Sato, Y. Omura Faculty of Engineering Science, Kansai University, Osaka, Japan DOI: 10.1109/ICMTS.2016.7476173 ABSTRACT: A new array structure to detect the soft failure of resistive elements is reported. By adding terminals to sense local potentials and high pass filtering a bit map image, it becomes possible to detect soft failure. Thanks to a simplified peripheral circuit, the layout area is drastically reduced and an aging test with overcurrent becomes possible.	PDF Xplore
3.3	Advanced ioff measureable MOSFET array with eliminating leakage current of peripheral circuits T. Suzuki, S. Mori, H. Oishi, M. Bairo, M. Tomita, K. Ogawa, Y. Fukuzaki, H. Ohnuma Sony Corporation, Atsugi-shi, Kanagawa, Japan DOI: 10.1109/ICMTS.2016.7476174 ABSTRACT: A Novel Ioff measurable MOSFET array has been developed. Body bias of peripheral circuit is controlled in order to eliminate the unwanted leakage current in peripheral circuit. SPICE simulation results indicate 10-14A or less of Ioff can be measured, and it is demonstrated that around 10-12A of Ioff can be measured directly without any additional correction measurement. Since it can be fit into scribe line, Ion and Ioff can be measured with high accuracy for plenty of MOSFETs during mass production. In addition, MOSFET characteristics depending on various types of layout parameters will be able to extract efficiently.	PDF Xplore
3.4	Design and use of an array-based test structure to characterize mechanical stress effects caused by WLCSP solder bumps H. Tuinhout, R. van Dalen¹ NXP Semiconductors - Technology & Operations, FEI - Modeling, Netherlands ¹Now with Ampleon, Netherlands DOI: 10.1109/ICMTS.2016.7476175 ABSTRACT: This paper discusses a 2100-DUT-array based test structure approach for high-resolution characterization of spatial mechanical stress distributions that are attributable to wafer level chip scale package solder bumps. DUT cell layout requirements, array implementation, measurement approach, and some data analysis challenges are reviewed in detail. Several examples of solder bump induced mobility variation illustrate the value of these test structures.	PDF Xplore

Session 4: Parameter Extraction

4.1	New access resistance extraction methodology for 14nm FD-SOI technology J. -B. Henry, A. Cros, J. Rosa, Q. Rafhay¹, G. Ghibaudo¹ STMicroelectronics, Crolles Site, TR&D/STD/TPS/SiRel, Crolles, France ¹IMEP-LAHC, MINATEC Campus, Grenoble, France DOI: 10.1109/ICMTS.2016.7476177 ABSTRACT: In this work, an improved methodology of access resistance extraction is proposed and applied on dedicated Kelvin test structures from a FD-SOI 14 nm technology. The use of this new approach and these test structures allow to confirm that the parasitic resistance of advanced MOSFET is highly dependent of the gate voltage. This explains the impossibility to decorrelate intrinsic and access components using Y function method for very small gate length transistors. A simple phenomenological model for MOSFETs access resistance is proposed and validated at the drain current level.	PDF Xplore
4.2	Test structures for CMOS RF reliability assessment L. Heiß, A. Lachmann¹, R. Schwab¹, G. Panagopoulos¹, P. Baumgartner¹, M. Y. Virupakshappaa¹, D. Schmitt-Landsiedel² Technische Universitat Munchen, Munchen, Bayern, DE ¹Intel Deutschland GmbH, Neubiberg, Germany ²Technical University of Munich (TUM), Munich, Germany DOI: 10.1109/ICMTS.2016.7476178 ABSTRACT: This work presents an improved methodology for CMOS RF reliability assessment with on-chip AC stress circuits. Compared to previous work high frequency stress signals are not only generated on-chip, but are also monitored by an on-chip oscilloscope (OCO). Experimental data from a HKMG technology highlight that without the OCO, existing test structures often lead to misinterpreted results under AC and RF stress.	PDF Xplore
4.3	Statistical analysis and modeling of Random Telegraph Noise based on gate delay variation measurement A. K. M. Mahfuzul Islam, T. Nakai¹, H. Onodera² Institute of Industrial Science, The University of Tokyo ¹Graduate School of Informatics, Kyoto University ²JST, CREST DOI: 10.1109/ICMTS.2016.7476179 ABSTRACT: We propose a characterization and modeling methodology for Random Telegraph Noise (RTN) induced ΔVth variation based on gate delay variation measurement. We characterize the total amount of ΔVth and model its scaling effect. A topology-reconfigurable ring oscillator (RO) is used to obtain gate delay variations between inverter stages. The devices under test are operated at near- or sub-threshold region to characterize RTN at low supply voltage. Measurement and characterization results from a 65 nm test chip show that lognormal distribution based modeling represents RTN-induced ΔVth variability precisely. We extract the model parameters and evaluate the gate size dependency of these parameters. It is found that μl of the lognormal distribution, lnN(μl, σl2), does not have specific gate size dependency. Whereas, σ shows a W−a dependency to gate size rather than the commonly assumed W−1 dependency, where a is evaluated to be less than 0.5. The proposed comprehensive statistical model and its parameter dependency is suitable for performance analysis of circuits where transistors of different gate sizes are used.	PDF Xplore

Session 5: RF and Power Devices

5.1	A high power curve tracer for characterizing full operational range of SiC power transistors Y. Nakamura, M. Shintani¹, T. Sato¹, T. Hikihara Graduate School of Engineering, Kyoto University, Kyoto, Japan ¹Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2016.7476181 ABSTRACT: A curve tracer is proposed for measuring static characteristics of power devices at high voltage and large current range. Using a SiC-MOSFET as a switch for pulse-based measurement, high voltage tolerance and fast switching are simultaneously achieved. The proposed curve tracer facilitates current-voltage measurements for full I-V regions found in practical device operations. The measurement results provided by the proposed method contribute to build device models that can be used to design efficient power converters.	PDF Xplore
5.2	A test structure set for on-wafer 3D-TRL calibration M. Potéreau, A. Curutchet, R. D'Esposito, M. De Matos, S. Fregonese, T. Zimmer IMS-Lab University of Bordeaux, Talence, France DOI: 10.1109/ICMTS.2016.7476182 ABSTRACT: This paper presents a new test structure set for on-wafer 3D-TRL calibration. It permits to define the reference plane below the Back-End-of-Line on Metal 1 level. Only one additional test structure is necessary to account for the coupling between input and output ports. Measurement accuracy below 1fF has been achieved.	PDF Xplore
5.3	Test structures of LASCR device for RF ESD protection in nanoscale CMOS process C. -Y. Lin, R. -K. Chang Department of Electrical Engineering, National Taiwan Normal University, Taiwan DOI: 10.1109/ICMTS.2016.7476183 ABSTRACT: The test structures of inductor-assisted silicon-controlled rectifier (LASCR) are investigated in this work to protect the radio-frequency (RF) integrated circuits from electrostatic discharge (ESD) damages. Verified in silicon chip, the LASCR with the assistance of inductor can provide both good ESD robustness and RF performances. With the better performances, the LASCR is very suitable for gigahertz RF applications.	PDF Xplore

Session 6: Capacitances

6.1	Highly effective and versatile test structure for evaluating dielectric properties using flexible pulse generator on chip S. Mori, K. Sawada, M. Tomita, K. Ogawa, T. Suzuki, H. Oishi, M. Bairo, Y. Fukuzaki, H. Ohnuma Sony Corporation, Atsugi-shi, Japan DOI: 10.1109/ICMTS.2016.7476185 ABSTRACT: A highly effective and versatile test structure with a flexible pulse generating circuit is proposed. Several significant features of the key components are demonstrated, that is, the tunable ring oscillator, the start-stop pulse controller, the Charge Injection induced Error Free Charge Based Capacitance Measurement (CIEF-CBCM) using Self-Aligned pulses and the modified Charge Pumping (CP) technique. This circuit system enables efficiently to collect data of multiple dielectric properties.	PDF Xplore
6.2	Extraction of floating-gate capacitive parameters in split-gate flash memory cells Y. Tkachev Silicon Storage Technology Inc., Microchip Technology, Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2016.7476186 ABSTRACT: A new fast and simple method for extraction of capacitive coupling coefficients in a split-gate flash memory cell is described. The method is based on the modulation of cell's erase characteristics by the bias applied to the gates during read and erase operations. The absolute values of the capacitance between the floating gate and other nodes are also extracted using the effect of modulation of cell conductance caused by the transfer of individual electrons to/from the floating gate.	PDF Xplore
6.3	Demonstration of MOS capacitor measurement for wafer manufacturing using a Direct Charge Measurement K. Takano, M. Goto, E. Shiling¹, A. Gasasira², J. -H. Liao² Keysight Technologies International Japan, Hachioji-shi, Tokyo, Japan ¹Keysight Technologies, Santa Rosa, CA, USA ²GLOBALFOUNDRIES, NY, USA DOI: 10.1109/ICMTS.2016.7476187 ABSTRACT: Direct Charge Measurement (DCM) has a capability to improve the capacitance measurement time in parametric test. Through an actual wafer measurement, we have successfully verified that DCM can measure MOS capacitor much faster than an LCR meter while keeping good correlations for wafer manufacturing.	PDF Xplore

Session 7: Memories

7.1	Test circuits to characterize setup/hold/access times, minimum voltage and maximum frequency of operation for memory compilers N. Dhamija, G. Lalani, M. Nelson¹, J. Brown¹, H. Spruth¹, P. Sharma Freescale Semiconductor, NOIDA, INDIA ¹Freescale Semiconductor, Austin, TX, USA DOI: 10.1109/ICMTS.2016.7476189 ABSTRACT: This paper will explain the design methodology to accurately measure the setup/hold/access time/Vmin & Fmax of memories on silicon. This architecture scheme implements the high resolution fine-tune delays of a few pico-seconds along with the coarse step sizes of ten's to hundreds of pico-seconds depending on technology, along with BIST for memory Vmin & Fmax characterization. This architecture has been implemented on one of our test-chip and silicon measurements show that measured parameters results are within 10% range of the simulated values. Implemented design scheme also ensures the serial as well as parallel measurement of these parameters of the memory instances in order to save the expensive tester time.	PDF Xplore
7.2	A new write stability metric using extended write butterfly curve for yield estimation in SRAM cells at low supply voltage H. Qiu, K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476190 ABSTRACT: A new extended write butterfly curve (BC) is proposed and evaluated through our device-matrix-array test-element-group (DMA-TEG) fabricated by Silicon-on-Thin-BOX (SOTB) technology. A good normality at low supply voltage (VDD), as well as good correlation with word-line method, demonstrates the extended write BC as a good candidate for yield estimation at low VDD. The comparison with conventional write BC is also discussed.	PDF Xplore
7.3	Measurement of SRAM power-up state for PUF applications using an addressable SRAM cell array test structure K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto, H. Shinohara¹ Institute of Industrial Science, University of Tokyo, Tokyo, Japan ¹Graduate School of Information, Production and Systems Waseda University, Fukuoka, Japan DOI: 10.1109/ICMTS.2016.7476191 ABSTRACT: SRAM data just after power-up were measured using an addressable SRAM cell array test structure. It was found that the results are strongly affected by the address switching noise and “memory effect”. An addressing sequence combined with word line reset pulse application is proposed for reliable power-up data stability evaluation.	PDF Xplore

Session 8: Non-Volatile Memories

8.1	New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM Y. Shuto, S. Yamamoto, S. Sugahara Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, Yokohama, Japan DOI: 10.1109/ICMTS.2016.7476193 ABSTRACT: Power-gating (PG) architectures employing nonvolatile state/data retention are expected to be a highly efficient energy reduction technique for high-performance CMOS logic systems. Recently, two types of PG architectures using nonvolatile retention have been proposed: One architecture is nonvolatile PG (NVPG) using nonvolatile bistable circuits such as nonvolatile SRAM (NV-SRAM) and nonvolatile flip-flop (NV-FF), in which nonvolatile retention is not utilized during the normal SRAM/FF operation mode and it is used only when there exist energetically meaningful shutdown periods given by break-even time (BET). In contrast, the other architecture employs nonvolatile retention during the normal SRAM/FF operation mode. In this type of architecture, an even short standby period can be replaced by a shutdown period, and thus this architecture is also called normally-off (NOF) rather than PG. In this paper, these two PG architectures for a FinFET-based high-performance NV-SRAM cell employing spintronics-based nonvolatile retention were systematically analyzed using HSPICE with a magnetoresistive-device macromodel. The NVPG architecture shows effective reduction of energy dissipation without performance degradation, whereas the NOF architecture causes severe performance degradation and the energy efficiency of the NOF architecture cannot be superior to that of the NVPG architecture.	PDF Xplore
8.2	Challenges of modeling the Split-Gate SuperFlash® Memory Cell with 1.1V Select Transistor M. Tadayoni, S. Martinie¹, O. Rozeau¹, S. Hariharan, C. Raynaud¹, N. Do Silicon Storage Technology, Inc., A subsidiary of Microchip Technology Inc., San Jose, CA, USA ¹CEA-LETI, Grenoble, France DOI: 10.1109/ICMTS.2016.7476194 ABSTRACT: In this paper we discuss key challenges related to application of an accurate 2T cell model for robust array design in 40nm CMOS technology and how an improved model behavior is used to overcome the challenges. The main challenge is the extraction of model parameters for word line (WL) and floating gate (FG) transistors in the absence of access to the FG. A global optimization scheme with an improved data collection strategy enabled the extraction of a comprehensive set of model parameters. This makes the separation of mobility parameters of WL and FG transistors possible.	PDF Xplore
8.3	Ultra-small and ultra-reliable innovative fuses scalable from 0.35um to 28nm S. Chung, W. -K. Fang, Y. Hsu, J. Hsiao, L. Lin, W. -H. Yu Attopsemi Technology Co.,LTD, Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS.2016.7476195 ABSTRACT: I-fuse is a fuse-based technology having (a) 1R1D cell, (b) limited programming below a critical current, and (c) small cell to improve program efficiency to pass qualification at 300°C for 4,290 hours. Test structures consist of single 1R1D structure and mini-arrays are used to characterize (a) critical current, (b) diode characteristics, and (c) cell current distribution.	PDF Xplore
8.4	Impact of a laser pulse on HfO2-based RRAM cells reliability and integrity A. Krakovinsky, M. Bocquet, R. Wacquez¹, J. Coignus¹, D. Deleruyelle, C. Djaou, G. Reimbold¹, J. -M. Portal CEA - DRT/DPACA, Laboratoire SAS, Centre de Microelectronique de Provence ¹IM2NP - UMR CNRS 7334, Aix-Marseille Université, France DOI: 10.1109/ICMTS.2016.7476196 ABSTRACT: Several NVM technologies have emerged during the last 10 years. These technologies offer solutions for the replacement of the Flash technology, which is facing downsizing limits [1]. Moreover these solutions propose lower switching energy and faster operations compared to the state of the art for Flash, and thus, are seen as an opportunity for the rise of the IoT market. But one of the main concerns regarding IoT is the protection of the data. Contrary to Flash, security of the data in emerging NVM is yet to be evaluated. In order to verify capability of the technology in terms of data integrity, we propose to investigate reliability and integrity of HfO2-based Resistive RAM (OxRRAM). This paper details the experimental protocol defined for laser-based attacks, shows that a laser pulse can affect the information stored in a single OxRRAM bit. The occurring phenomenon is then explained by mean of thermal and electrical simulations.	PDF Xplore

Session 9: Process and Device Characterization

9.1	Test structures to support the development and process verification of microelectrodes for high temperature operation in molten salts E. O. Blair, D. K. Corrigan¹, I. Schmueser, J. G. Terry, S. Smith, A. R. Mount¹, A. J. Walton SMC, The University of Edinburgh, Edinburgh, UK ¹EASTCHEM, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS.2016.7476198 ABSTRACT: This paper reports the design and application of test structures used for the development and characterisation of microelectrodes for operation in the harsh, caustic environment of molten salts operating at 450°C. These structures have been employed to evaluate the effect of electrode area and the dielectric integrity of insulating layers in the molten salt. This has been useful in identifying failures mechanisms, which has facilitated the optimisation of both the design and fabrication of the microelectrodes while at the same time also providing valuable information for process verification.	PDF Xplore
9.2	Interface trap density estimation in FinFETs from the subthreshold current J. Schmitz, B. Kaleli¹, P. Kuipers, N. van den Berg², S. M. Smits, R. J. E. Hueting MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands ¹ASML, Veldhoven, The Netherlands ²Micronit Microftuidics, Enschede, The Netherlands DOI: 10.1109/ICMTS.2016.7476199 ABSTRACT: In this work we present a measurement approach to determine the interface trap density in FinFETs as a function of their energy. It is based on the precise determination of the gate voltage dependent ideality factor of the subthreshold current in this device. The required measurement accuracy for temperature, drain current and transconductance is derived, and we propose an implementation for wafer-level device measurement on contemporary test set-ups. Exemplary interface trap distributions are shown as obtained from two FinFET device technologies, featuring the commonly observed bathtub shape.	PDF Xplore
9.3	Novel test structure for evaluating dynamic dopant activation after ion implantation J. -R. Tsai, R. -D. Chang¹, C. -H. Chou¹, H. -C. Liao¹, S. -K. Huang¹, S. -H. Lin¹, J. -C. Lin¹ Department of Photonics and Communication Engineering, Asia University 500, Taiwan, R. O. C. ¹Department of Electronic Engineering, Chang Gung University, Taiwan, R. O. C. DOI: 10.1109/ICMTS.2016.7476200 ABSTRACT: This work focuses on the development of a novel test structure to evaluate the dynamic behavior of electrical characteristics in the boron-implanted germanium samples during the solid phase epitaxial regrowth (SPER) at low temperature annealing of 360 and 400 °C with various annealing times ranging from 30 to 300 min. In the early stage of SPER annealing, the sheet carrier concentration is increased with annealing time. And then, it will saturate to a level after about 2 hr annealing which implies the completion of SPER process.	PDF Xplore
9.4	Top-gated MoS2 capacitors and transistors with high-k dielectrics for interface study P. Zhao, A. Azcatl, P. Bolshakov-Barrett, R. M. Wallace, C. D. Young, P. K. Hurley¹ Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX, USA ¹University of College Cork, Tyndall National Institute, Cork, Ireland DOI: 10.1109/ICMTS.2016.7476201 ABSTRACT: Top-gated MOS capacitors on bulk MoS2 and transistors of few-layer MoS2 were designed and fabricated. They can be potentially utilized on various TMD and high-k materials for fast and robust electrical characterization. The 3-terminal transistor test structure shows advantages of significant reduction of parasitic effects. C-V and I-V measurements were successfully conducted to characterize few-layer MoS2 transistors with sub-10 nm HfO2 dielectric.	PDF Xplore

Session 10: Materials Characterization

10.1	Chip level characterisation studies of Ni and NiFe electrochemical deposition using test structures J. Murray, R. Perry, J. G. Terry, S. Smith, A. R. Mount, A. J. Walton The University of Edinburgh, Edinburgh, Edinburgh, GB DOI: 10.1109/ICMTS.2016.7476203 ABSTRACT: This paper describes the first use of test structure chips designed to characterise the fundamental properties of Ni and NiFe alloy films deposited using electroplating. This approach is used to perform a chip-level investigation into the effects of electrolyte bath composition on the characteristics of deposited Ni and NiFe layers. The advantage of this methodology is that each electrolyte change does not require the replacement of a 35 litre bath (which is necessary for wafer level investigations), thereby making each experiment far less time consuming, and considerably cheaper to perform.	PDF Xplore
10.2	Test structures for the characterisation of conductive carbon produced from photoresist S. Scarfì, S. Smith¹, A. Tabasnikov, I. Schmüser, E. Blair, A. S. Bunting, A. J. Walton, A. F. Murray¹, J. G. Terry Institute for Integrated Micro and Nano Systems, The University of Edinburgh, Edinburgh, EH9 3FF ¹Institute for Biomedical Engineering, The University of Edinburgh, Edinburgh, EH9 3FF DOI: 10.1109/ICMTS.2016.7476204 ABSTRACT: Conductive carbon films are highly attractive for use as electrodes in electrochemistry and biosensing applications. Patterned photoresist films can be transformed into carbon electrodes using standard photolithographic techniques followed by pyrolysation of the photoresist in a furnace under a reducing atmosphere. Previous studies have been made of the electrical properties of blanket carbon films created using this method of fabrication. However, there is a need to investigate pattern dependent effects, particularly the extent to which the dimensions of the patterned films shrink during the high temperature processing. This study applies microfabricated test structures to the process characterisation of conductive carbon produced from standard positive photoresists.	PDF Xplore
10.3	Comparing current flows in ultrashallow pn-/Schottky-like diodes with 2-diode test method X. Liu, L. K. Nanver Semiconductor Components, University of Twente, Enschede, the Netherlands DOI: 10.1109/ICMTS.2016.7476205 ABSTRACT: A 2-diode test structure is proposed and investigated for use with simple I-V measurements, giving an easy-to-process, fast turn-around-time method of comparing process-dependent current flows when developing ultrashallow/ Schottky junction technologies. Differential diode current characteristics and collector currents obtained from lateral transistor operation of the same 2-diode test structure are used to reliably identify the diode type and variations in metal-Si interfacial properties, independent of parasitic leakage currents. The versatility of this method with respect to diode geometry and substrate doping is verified for the measurement of junction- and Schottky-like diodes formed by different chemical-vapor-deposition processes.	PDF Xplore
10.4	A reliable Schottky barrier height extraction procedure B. -Y. Tsui, T. -Y. Fu Department of Electronics Engineering & Institute of Electronics, National Chiao-Tung University ED641, Hsinchu, Taiwan, R. O. C DOI: 10.1109/ICMTS.2016.7476206 ABSTRACT: This work proposes a Schottky barrier extraction procedure which considers the thermionic field emission (TFE) model, image-force induced barrier lowering effect, and parasitic resistance. The accuracy of the Schottky barrier height extracted by the field emission (FE) model at forward bias and the TFE model at reverse bias is evaluated. The TFE model can obtain accurate SBH with low SBH (~0.3 eV) and high doping concentration (~1ä—l020 cm-3). It is thus recommended that the proposed extraction procedure could be used to study the Schottky junction precisely.	PDF Xplore

By First Author

9.1	Test structures to support the development and process verification of microelectrodes for high temperature operation in molten salts E. O. Blair, D. K. Corrigan¹, I. Schmueser, J. G. Terry, S. Smith, A. R. Mount¹, A. J. Walton SMC, The University of Edinburgh, Edinburgh, UK ¹EASTCHEM, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS.2016.7476198 HOVER FOR ABSTRACT	PDF Xplore
8.3	Ultra-small and ultra-reliable innovative fuses scalable from 0.35um to 28nm S. Chung, W. -K. Fang, Y. Hsu, J. Hsiao, L. Lin, W. -H. Yu Attopsemi Technology Co.,LTD, Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS.2016.7476195 HOVER FOR ABSTRACT	PDF Xplore
2.2	Dedicated test-structures for investigation of the thermal impact of the BEOL in advanced SiGe HBTs in time and frequency domain R. D'Esposito, S. Fregonese, T. Zimmer, A. Chakravorty¹ CNRS-UMR 5218, Université de Bordeaux ¹Department of Electrical Engineering, IIT Madras, Chennai, India DOI: 10.1109/ICMTS.2016.7476168 HOVER FOR ABSTRACT	PDF Xplore
1.4	Microfabricated test structures for thermal gas sensor M. Denoual, M. Pouliquen, D. Robbes, O. de Sagazan¹, J. Grand¹, H. Awala¹, S. Mintova², S. Inoue³, A. Mita-Tixier³, Y. Mita³ GREYC-CNRS, ENSICAEN, France ¹LCS-CNRS, University of Caen, France ²IETR, University of Rennes, France ³Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476165 HOVER FOR ABSTRACT	PDF Xplore
7.1	Test circuits to characterize setup/hold/access times, minimum voltage and maximum frequency of operation for memory compilers N. Dhamija, G. Lalani, M. Nelson¹, J. Brown¹, H. Spruth¹, P. Sharma Freescale Semiconductor, NOIDA, INDIA ¹Freescale Semiconductor, Austin, TX, USA DOI: 10.1109/ICMTS.2016.7476189 HOVER FOR ABSTRACT	PDF Xplore
4.2	Test structures for CMOS RF reliability assessment L. Heiß, A. Lachmann¹, R. Schwab¹, G. Panagopoulos¹, P. Baumgartner¹, M. Y. Virupakshappaa¹, D. Schmitt-Landsiedel² Technische Universitat Munchen, Munchen, Bayern, DE ¹Intel Deutschland GmbH, Neubiberg, Germany ²Technical University of Munich (TUM), Munich, Germany DOI: 10.1109/ICMTS.2016.7476178 HOVER FOR ABSTRACT	PDF Xplore
4.1	New access resistance extraction methodology for 14nm FD-SOI technology J. -B. Henry, A. Cros, J. Rosa, Q. Rafhay¹, G. Ghibaudo¹ STMicroelectronics, Crolles Site, TR&D/STD/TPS/SiRel, Crolles, France ¹IMEP-LAHC, MINATEC Campus, Grenoble, France DOI: 10.1109/ICMTS.2016.7476177 HOVER FOR ABSTRACT	PDF Xplore
4.3	Statistical analysis and modeling of Random Telegraph Noise based on gate delay variation measurement A. K. M. Mahfuzul Islam, T. Nakai¹, H. Onodera² Institute of Industrial Science, The University of Tokyo ¹Graduate School of Informatics, Kyoto University ²JST, CREST DOI: 10.1109/ICMTS.2016.7476179 HOVER FOR ABSTRACT	PDF Xplore
2.3	Hotspot test structures for evaluating carbon nanotube microfin coolers and graphene-like heat spreaders K. Jeppson, J. Bao¹, S. Huang¹, Y. Zhang, S. Sun, Y. Fu², J. Liu Chalmers University of Technology, Gothenburg, Sweden ¹Chalmers University of Technology, SHT Smart High Tech, Gothenburg, Sweden ²Shanghai University SMIT Center, Jiading Campus, Shanghai, China DOI: 10.1109/ICMTS.2016.7476169 HOVER FOR ABSTRACT	PDF Xplore
8.4	Impact of a laser pulse on HfO2-based RRAM cells reliability and integrity A. Krakovinsky, M. Bocquet, R. Wacquez¹, J. Coignus¹, D. Deleruyelle, C. Djaou, G. Reimbold¹, J. -M. Portal CEA - DRT/DPACA, Laboratoire SAS, Centre de Microelectronique de Provence ¹IM2NP - UMR CNRS 7334, Aix-Marseille Université, France DOI: 10.1109/ICMTS.2016.7476196 HOVER FOR ABSTRACT	PDF Xplore
3.1	Random telegraph noise measurement and analysis based on arrayed test circuit toward high S/N CMOS image sensors R. Kuroda, A. Teramoto¹, S. Sugawa¹ Graduate School of Engineering, Tohoku University, Sendai, Japan ¹New Industry Creation Hatchery Center, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS.2016.7476172 HOVER FOR ABSTRACT	PDF Xplore
5.3	Test structures of LASCR device for RF ESD protection in nanoscale CMOS process C. -Y. Lin, R. -K. Chang Department of Electrical Engineering, National Taiwan Normal University, Taiwan DOI: 10.1109/ICMTS.2016.7476183 HOVER FOR ABSTRACT	PDF Xplore
10.3	Comparing current flows in ultrashallow pn-/Schottky-like diodes with 2-diode test method X. Liu, L. K. Nanver Semiconductor Components, University of Twente, Enschede, the Netherlands DOI: 10.1109/ICMTS.2016.7476205 HOVER FOR ABSTRACT	PDF Xplore
2.1	A test structure for analysis of metal wire effect on temperature distribution in stacked IC T. Matsuda, H. Demachi, H. Iwata, T. Hatakeyama, T. Ohzone¹ Toyama Prefectural University, Toyama, Japan ¹Dawn Enterprise, Nagoya, Japan DOI: 10.1109/ICMTS.2016.7476167 HOVER FOR ABSTRACT	PDF Xplore
2.4	Transistor self-heating correction and thermal conductance extraction using only DC data C. C. McAndrew, A. Lorenzo-Cassagnes, O. L. Hartin¹ NXP Semiconductors, Tempe, AZ ¹Arizona State University, Tempe, AZ DOI: 10.1109/ICMTS.2016.7476170 HOVER FOR ABSTRACT	PDF Xplore
6.1	Highly effective and versatile test structure for evaluating dielectric properties using flexible pulse generator on chip S. Mori, K. Sawada, M. Tomita, K. Ogawa, T. Suzuki, H. Oishi, M. Bairo, Y. Fukuzaki, H. Ohnuma Sony Corporation, Atsugi-shi, Japan DOI: 10.1109/ICMTS.2016.7476185 HOVER FOR ABSTRACT	PDF Xplore
10.1	Chip level characterisation studies of Ni and NiFe electrochemical deposition using test structures J. Murray, R. Perry, J. G. Terry, S. Smith, A. R. Mount, A. J. Walton The University of Edinburgh, Edinburgh, Edinburgh, GB DOI: 10.1109/ICMTS.2016.7476203 HOVER FOR ABSTRACT	PDF Xplore
5.1	A high power curve tracer for characterizing full operational range of SiC power transistors Y. Nakamura, M. Shintani¹, T. Sato¹, T. Hikihara Graduate School of Engineering, Kyoto University, Kyoto, Japan ¹Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2016.7476181 HOVER FOR ABSTRACT	PDF Xplore
1.2	An end-point visualization test structure for all plasma dry release of Deep-RIE MEMS Y. Okamoto, E. Lebrasseur, I. Mori, Y. Mita Department of Electrical Engineering The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476163 HOVER FOR ABSTRACT	PDF Xplore
5.2	A test structure set for on-wafer 3D-TRL calibration M. Potéreau, A. Curutchet, R. D'Esposito, M. De Matos, S. Fregonese, T. Zimmer IMS-Lab University of Bordeaux, Talence, France DOI: 10.1109/ICMTS.2016.7476182 HOVER FOR ABSTRACT	PDF Xplore
7.2	A new write stability metric using extended write butterfly curve for yield estimation in SRAM cells at low supply voltage H. Qiu, K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476190 HOVER FOR ABSTRACT	PDF Xplore
3.2	Proposal of a new array structure to enable the detection of soft failure and the aging test with overcurrent of resistive element S. Sato, Y. Omura Faculty of Engineering Science, Kansai University, Osaka, Japan DOI: 10.1109/ICMTS.2016.7476173 HOVER FOR ABSTRACT	PDF Xplore
10.2	Test structures for the characterisation of conductive carbon produced from photoresist S. Scarfì, S. Smith¹, A. Tabasnikov, I. Schmüser, E. Blair, A. S. Bunting, A. J. Walton, A. F. Murray¹, J. G. Terry Institute for Integrated Micro and Nano Systems, The University of Edinburgh, Edinburgh, EH9 3FF ¹Institute for Biomedical Engineering, The University of Edinburgh, Edinburgh, EH9 3FF DOI: 10.1109/ICMTS.2016.7476204 HOVER FOR ABSTRACT	PDF Xplore
9.2	Interface trap density estimation in FinFETs from the subthreshold current J. Schmitz, B. Kaleli¹, P. Kuipers, N. van den Berg², S. M. Smits, R. J. E. Hueting MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands ¹ASML, Veldhoven, The Netherlands ²Micronit Microftuidics, Enschede, The Netherlands DOI: 10.1109/ICMTS.2016.7476199 HOVER FOR ABSTRACT	PDF Xplore
8.1	New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM Y. Shuto, S. Yamamoto, S. Sugahara Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, Yokohama, Japan DOI: 10.1109/ICMTS.2016.7476193 HOVER FOR ABSTRACT	PDF Xplore
3.3	Advanced ioff measureable MOSFET array with eliminating leakage current of peripheral circuits T. Suzuki, S. Mori, H. Oishi, M. Bairo, M. Tomita, K. Ogawa, Y. Fukuzaki, H. Ohnuma Sony Corporation, Atsugi-shi, Kanagawa, Japan DOI: 10.1109/ICMTS.2016.7476174 HOVER FOR ABSTRACT	PDF Xplore
8.2	Challenges of modeling the Split-Gate SuperFlash® Memory Cell with 1.1V Select Transistor M. Tadayoni, S. Martinie¹, O. Rozeau¹, S. Hariharan, C. Raynaud¹, N. Do Silicon Storage Technology, Inc., A subsidiary of Microchip Technology Inc., San Jose, CA, USA ¹CEA-LETI, Grenoble, France DOI: 10.1109/ICMTS.2016.7476194 HOVER FOR ABSTRACT	PDF Xplore
6.3	Demonstration of MOS capacitor measurement for wafer manufacturing using a Direct Charge Measurement K. Takano, M. Goto, E. Shiling¹, A. Gasasira², J. -H. Liao² Keysight Technologies International Japan, Hachioji-shi, Tokyo, Japan ¹Keysight Technologies, Santa Rosa, CA, USA ²GLOBALFOUNDRIES, NY, USA DOI: 10.1109/ICMTS.2016.7476187 HOVER FOR ABSTRACT	PDF Xplore
1.1	An efficient method to evaluate 4 million micro-bump interconnection resistances for 3D stacked 16-mpixel image sensor Y. Takemoto, H. Kato, T. Kondo, N. Takazawa, M. Tsukimura, H. Saito, K. Kobayashi, J. Aoki, S. Suzuki, Y. Gomi, S. Matsuda, Y. Tadaki Imager and Analog LSI technology Department, Olympus Corporation, Hachioji-shi, Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476162 HOVER FOR ABSTRACT	PDF Xplore
7.3	Measurement of SRAM power-up state for PUF applications using an addressable SRAM cell array test structure K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto, H. Shinohara¹ Institute of Industrial Science, University of Tokyo, Tokyo, Japan ¹Graduate School of Information, Production and Systems Waseda University, Fukuoka, Japan DOI: 10.1109/ICMTS.2016.7476191 HOVER FOR ABSTRACT	PDF Xplore
6.2	Extraction of floating-gate capacitive parameters in split-gate flash memory cells Y. Tkachev Silicon Storage Technology Inc., Microchip Technology, Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2016.7476186 HOVER FOR ABSTRACT	PDF Xplore
9.3	Novel test structure for evaluating dynamic dopant activation after ion implantation J. -R. Tsai, R. -D. Chang¹, C. -H. Chou¹, H. -C. Liao¹, S. -K. Huang¹, S. -H. Lin¹, J. -C. Lin¹ Department of Photonics and Communication Engineering, Asia University 500, Taiwan, R. O. C. ¹Department of Electronic Engineering, Chang Gung University, Taiwan, R. O. C. DOI: 10.1109/ICMTS.2016.7476200 HOVER FOR ABSTRACT	PDF Xplore
10.4	A reliable Schottky barrier height extraction procedure B. -Y. Tsui, T. -Y. Fu Department of Electronics Engineering & Institute of Electronics, National Chiao-Tung University ED641, Hsinchu, Taiwan, R. O. C DOI: 10.1109/ICMTS.2016.7476206 HOVER FOR ABSTRACT	PDF Xplore
3.4	Design and use of an array-based test structure to characterize mechanical stress effects caused by WLCSP solder bumps H. Tuinhout, R. van Dalen¹ NXP Semiconductors - Technology & Operations, FEI - Modeling, Netherlands ¹Now with Ampleon, Netherlands DOI: 10.1109/ICMTS.2016.7476175 HOVER FOR ABSTRACT	PDF Xplore
1.3	Spring-constant measurement methods for RF-MEMS capacitive switches J. Wang, J. Bielen¹, C. Salm, J. Schmitz The MESA+ Institute for Nanotechnology, University of Twente, Netherlands ¹EPCOS Netherlands, Netherlands DOI: 10.1109/ICMTS.2016.7476164 HOVER FOR ABSTRACT	PDF Xplore
9.4	Top-gated MoS2 capacitors and transistors with high-k dielectrics for interface study P. Zhao, A. Azcatl, P. Bolshakov-Barrett, R. M. Wallace, C. D. Young, P. K. Hurley¹ Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX, USA ¹University of College Cork, Tyndall National Institute, Cork, Ireland DOI: 10.1109/ICMTS.2016.7476201 HOVER FOR ABSTRACT	PDF Xplore