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IEEE International Conference on Microelectronic Test Structures

ICMTS 2013 Program

2013 Program Booklet


By First Author

A new measurement set-up to investigate the charge trapping phenomena in RF MEMS packaged switches
M. Barbato, V. Giliberto, G. Meneghesso
Department of Information Engineering, University of Padova, Padova, Italy
DOI: 10.1109/ICMTS.2013.6528140
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Test structure and analysis for accurate RF-characterization of tungsten through silicon via (TSV) grounding devices
V. Blaschke, H. Jebory1
TowerJazz Semiconductors Limited, Newport, CA, USA
1TowerJazz Semiconductors Limited, Newport Beach, CA, USA
DOI: 10.1109/ICMTS.2013.6528141
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Characterization and simulation of NMOS pass transistor reliability for FPGA routing circuits
C. S. Chen, J. T. Watt
Process Technology Development, Altera Corporation, San Jose, CA, USA
DOI: 10.1109/ICMTS.2013.6528175
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Process control monitors for individual single-walled carbon nanotube transistor fabrication processes
K. Chikkadi, M. Haluska, C. Hierold, C. Roman
Micro and Nanosystems, Department of Mechanical and Process Engineering, ETH Zurich, Zurich, Switzerland
DOI: 10.1109/ICMTS.2013.6528167
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On-wafer integrated system for fast characterization and parametric test of new-generation Non Volatile Memories
E. Covi, A. Cabrini, L. Vendrame1, L. Bortesi1, R. Gastaldi1, G. Torelli2
Dipartimento di Ingegneria Industriale e dellInformazione, University of Pavia, Pavia, Italy
1Micron Semiconductor Italia s.r.l., R&D - Technology Development, Agrate Brianza, Italy
2Universita degli Studi di Pavia, Pavia, Lombardia, IT
DOI: 10.1109/ICMTS.2013.6528171
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Greek cross test structure for inkjet printed thin films
E. Dä­az, E. Ramon, J. Carrabina
CAIAC, Microelectronics and Electronic Systems Department, Universitat Autònoma de Barcelona, Barcelona, Spain
DOI: 10.1109/ICMTS.2013.6528166
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Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures
C. -T. Dai, M. -D. Ker
Institute of Electronics, National Chiao-Tung University, Taiwan
DOI: 10.1109/ICMTS.2013.6528158
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A novel silicon interposer for measuring devices requiring complex two-sided contacting
J. Derakhshandeh, N. Golshani, L. A. Steenweg, W. van der Vlist, L. K. Nanver
DIMES, Delft University of Technology Engineering, Delft, Netherlands
DOI: 10.1109/ICMTS.2013.6528143
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Comparison of electrical techniques for temperature evaluation in power MOS transistors
A. Ferrara, P. G. Steeneken1, K. Reimann1, A. Heringa2, L. Yan2, B. K. Boksteen, M. Swanenberg3, G. E. J. Koops2, A. J. Scholten2, R. Surdeanu2, J. Schmitz, R. J. E. Hueting
MESA Institute for Nanotechnology, University of Twente, Enschede, Netherlands
1NXP Semiconductors, Eindhoven, Netherlands
2NXP Semiconductors, Leuven, Belgium
3NXP Semiconductors, Nijmegen, Netherlands
DOI: 10.1109/ICMTS.2013.6528156
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An integrated CMOS-MEMS probe having two-tips per cantilever for individual contact sensing and kelvin measurement with two cantilevers
K. Hosaka, S. Morishita, I. Mori, M. Kubota, Y. Mita
School of Engineering, University of Tokyo, Tokyo, Japan
DOI: 10.1109/ICMTS.2013.6528136
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A novel BJT structure for high- performance analog circuit applications
S. -M. Hwang, H. -M. Kwon, J. -H. Jang, H. -Y. Kwak, S. -K. Kwon, S. -Y. Sung, J. -K. Shin, J. -N. Yu, I. -S. Han, Y. -S. Chung, J. -H. Lee, G. -W. Lee, H. -D. Lee
Department of Electronics Engineering, Chungnam National University, Daejeon, South Korea
DOI: 10.1109/ICMTS.2013.6528154
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Three- and four-point Hamer-type MOSFET parameter extraction methods revisited
K. O. Jeppson
Department of Microtechnology and Nanoscience, Chalmers University of Technology, Gothenburg, Sweden
DOI: 10.1109/ICMTS.2013.6528161
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A new Ultra-Fast Single Pulse technique (UFSP) for channel effective mobility evaluation in MOSFETs
Z. Ji, J. Gillbert1, J. F. Zhang, W. Zhang
School of Engineering, Liverpool John Moores University, Liverpool, UK
1Keithley Instruments, Inc., UK
DOI: 10.1109/ICMTS.2013.6528147
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Benchmarking of a surface potential based organic thin-film transistor model against C10-DNTT high performance test devices
T. K. Maiti, T. Hayashi1, H. Mori2, M. J. Kang2, K. Takimiya2, M. Miura-Mattausch3, H. J. Mattausch3
HiSIM Research Center, Hiroshima University, Higashi, Hiroshima, Japan
1Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashi, Hiroshima, Japan
2Department of Applied Chemistry, Graduate School of Engineering, Hiroshima University, Higashi, Hiroshima, Japan
3HiSIM Research Center, Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashi, Hiroshima, Japan
DOI: 10.1109/ICMTS.2013.6528164
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A test structure for analysis of temperature distribution in CMOS LSI with sensing device array
T. Matsuda, H. Hanai, H. Iwata, D. Kondo, T. Hatakeyama, M. Ishizuka, T. Ohzone1
Department of Information Systems Engineering, Toyama Prefectural University, Imizu, Japan
1Dawn Enterprise Company Limited, Nagoya, Japan
DOI: 10.1109/ICMTS.2013.6528159
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Analysis of narrow gate to gate space dependence of MOS gate-source/drain capacitance by using contact-less and drawn-out source/drain test structure
Y. Naruta, S. Kumashiro1
Renesas Electronics Corporation, Kodaira, Tokyo, Japan
1Renesas Electronics Corporation, Kawasaki, Kanagawa, Japan
DOI: 10.1109/ICMTS.2013.6528160
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Investigation of devices of in-vivo energy harvesting through blood-flow-like excitation
R. O'Keeffe, N. Jackson, A. Mathewson, K. G. McCarthy1
Tyndall National Institute, University College Cork, Cork, Ireland
1Department of Electrical and Electronic Engineering, University College Cork, Cork, Ireland
DOI: 10.1109/ICMTS.2013.6528139
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Optical high frequency test structure and test bench definition for on wafer silicon integrated noise source characterization up to 110 GHz based on Germanium-on-Silicon photodiode
S. Oeuvrard, J. . -F. Lampin, G. Ducournau, L. Virot1, J. M. Fedeli2, J. M. Hartmann2, F. Danneville, Y. Morandini3, D. Gloria1
IEMN, Villeneuve d'Ascq, France
1TR&D, TPS Laboratory, STMicroelectronics, Crolles, France
2LETI, CEA, Grenoble, France
3Dolphin Integration GmbH, Meylan, France
DOI: 10.1109/ICMTS.2013.6528148
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Die-to-die and within-die variation extraction for circuit simulation with surface-potential compact model
Y. Ohnari, A. A. Khan, A. Dutta, M. Miura-Mattausch, H. J. Mattausch
Research Institute for Nanodevice and Bio Systems, Hiroshima University, Higashi, Hiroshima, Japan
DOI: 10.1109/ICMTS.2013.6528162
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Tr variance evaluation induced by probing pressure and its stress extraction methodology in 28nm High-K and Metal Gate process
T. Okagaki, T. Hasegawa, H. Takashino, M. Fujii, A. Tsuda, K. Shibutani, Y. Deguchi, M. Yokota, K. Onozawa
Renesas Electronics Corporation, Itami, Hyogo, Japan
DOI: 10.1109/ICMTS.2013.6528172
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Mosaic SRAM Cell TEGs with intentionally-added device variability for confirming the ratio-less SRAM operation
H. Okamura, T. Saito, H. Goto, M. Yamamoto, K. Nakamura
Center for Microelectronic Systems, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan
DOI: 10.1109/ICMTS.2013.6528174
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A novel test structure to implement a programmable logic array using split-gate flash memory cells
H. Om'mani, M. Tadayoni, N. Thota, Ian Yue, Nhan Do
A Subsidiary of Microchip Technology Inc., Silicon Storage Technology, San Jose, California, USA
DOI: 10.1109/ICMTS.2013.6528170
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On the length of THRU standard for TRL de-embedding on Si substrate above 110 GHz
A. Orii, M. Suizu, S. Amakawa, K. Katayama, K. Takano, M. Motoyoshi, T. Yoshida, M. Fujishima
Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashihiroshima, Japan
DOI: 10.1109/ICMTS.2013.6528150
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Measurement and investigation of thermal properties of the on-chip metallization for integrated power technologies
M. Pfost, C. Boianceanu1, I. Lascau1, D. -I. Simon1, S. Sosin1
Robert Bosch Center for Power Electronics, Reutlingen University, Reutlingen, Germany
1ATV PTP TM, Infineon Technologies Romania, Bucharest, Romania
DOI: 10.1109/ICMTS.2013.6528157
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A proper approach to characterize retention-after-cycling in 3D-Flash devices
Fengying Qiao, A. Arreghini1, P. Blomme1, G. Van den bosch1, Liyang Pan, Jun Xu, J. Van Houdt1
Institute of Microelectronics, Tsinghua University, Beijing, China
1Imec, Leuven, Belgium
DOI: 10.1109/ICMTS.2013.6528169
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New methodology for drain current local variability characterization using Y function method
L. Rahhal, A. Bajolet, C. Diouf, A. Cros, J. Rosa, N. Planes, G. Ghibaudo1
STMicroelectronics, Crolles, France
1Minatec , INPG, IMEP-LAHC, Grenoble, France
DOI: 10.1109/ICMTS.2013.6528153
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Newly developed Test-Element-Group for detecting soft failures of the low-resistance-element using doubly nesting array
S. Sato, H. Shinkawata, A. Tsuda, T. Yoshizawa, T. Ohno
Devices and Analysis Technology Div., Production and Technology Unit., Renesas Electronics Corporation, Hyogo, Japan
DOI: 10.1109/ICMTS.2013.6528152
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Characterization of capacitance mismatch using simple difference Charge-based Capacitance measurement (DCBCM) test structure
K. Sawada, G. Van der Plas1, Y. Miyamori2, T. Oishi3, C. Vladimir1, A. Mercha1, V. Diederik1, H. Ammo3
IMEC, Sony Corporation, Leuven, Belgium
1IMEC, Leuven, Belgium
2Sony Semiconductor Corporation, Kumamoto, Japan
3Sony Corporation, Atsugi, Kanagawa, Japan
DOI: 10.1109/ICMTS.2013.6528144
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Measurements of SRAM sensitivity against AC power noise with effects of device variation
T. Sawada, K. Yoshikawa, H. Takata1, K. Nii1, M. Nagata
Graduate School of System Informatics, Kobe University, Kobe, Japan
1Renesas Electronics Corporation, Tokyo, Japan
DOI: 10.1109/ICMTS.2013.6528149
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Micromechanical test structures for the characterisation of electroplated NiFe cantilevers and their viability for use in MEMS switching devices
G. Schiavone, S. Smith, J. Murray1, J. G. Terry, M. P. Y. Desmulliez2, A. J. Walton
Institute for Integrated Micro and Nano Systems, Joint Research Institute for Integrated Systems, School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK
1Institute for Integrated Micro and Nano Systems, Joint Research Institute for Integrated Systems, School of Engineering, Scottish Microelectronics Centre, School of Chemistry, Joseph Black Building, University of Edinburgh, Edinburgh, UK
2MIcroSystems Engineering Centre, Joint Research Institute for Integrated Systems, School of Engineering & Physical Sciences, Heriot-Watt University, Edinburgh, UK
DOI: 10.1109/ICMTS.2013.6528138
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Electrical and mechanical characterizations of a large-area, printed organic transistor active matrix with floating-gate-based nonuniformity compensator
T. Sekitani, T. Yokota, T. Tokuhara, T. Someya
Department of Electrical and Electronic Engineering and Department of Applied Physics, University of Tokyo, Tokyo, Japan
DOI: 10.1109/ICMTS.2013.6528165
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Efficient technique for Si validation of level shifters
P. Sharma, B. Smith1, D. Hall1, M. Nelson1, U. Lohani
Freescale Semiconductor, Inc., Noida, India
1Freescale Semiconductor, Inc., Austin, TX, USA
DOI: 10.1109/ICMTS.2013.6528173
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BSIM4 parameter extraction for tri-gate Si nanowire transistors
C. Tanaka, M. Saitoh, K. Ota, T. Numata
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama, Kanagawa, Japan
DOI: 10.1109/ICMTS.2013.6528163
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Reconsideration of the threshold voltage variability estimated with pair transistor cell array
K. Terada, N. Higuchi, K. Tsuji
Faculty of Information Sciences, Hiroshima University, Hiroshima, Japan
DOI: 10.1109/ICMTS.2013.6528155
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Effective channel length estimation using charge-based capacitance measurement
K. Tsuji, K. Terada
Faculty of Information Sciences, Hiroshima University, Hiroshima, Japan
DOI: 10.1109/ICMTS.2013.6528146
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Evaluation of 1/f noise variability in the subthreshold region of MOSFETs
H. Tuinhout, A. Z. -v. Duijnhoven
NXP Semiconductors - Design Platforms, Eindhoven, The Netherlands
DOI: 10.1109/ICMTS.2013.6528151
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Characterisation and integration of Parylene as an insulating structural layer for high aspect ratio electroplated copper coils
R. Walker, E. Sirotkin, I. Schmueser, J. G. Terry, S. Smith, J. T. M. Stevenson, A. J. Walton
Institute of Integrated Micro and Nano Systems, School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, UK
DOI: 10.1109/ICMTS.2013.6528137
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Comparison of C-V measurement methods for RF-MEMS capacitive switches
Jiahui Wang, C. Salm, J. Schmitz
MESA Institute for Nanotechnology, University of Twente, Enschede, Netherlands
DOI: 10.1109/ICMTS.2013.6528145
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Test structures for electrical evaluation of high aspect ratio TSV arrays fabricated using planarised sacrificial photoresist
R. Zhang, Y. Li, J. Murray, A. S. Bunting, S. Smith, C. C. Dunare, J. T. M. Stevenson, M. P. Desmulliez, A. J. Walton
SMC, Institute of Integrated Micro and Nano Systems, School of Engineering, Institute of Integrated Systems, University of Edinburgh, Edinburgh, UK
DOI: 10.1109/ICMTS.2013.6528142
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