IEEE International Conference on Microelectronic Test Structures
ICMTS 2008 Program
2008 Program Booklet
By First Author
| CMOS latch metastability characterization at the 65-nm-technology node M. Bhushan, M. B. Ketchen1, K. K. Das1 IBM Systems and Technology Group, Hopewell Junction, NY, USA 1IBM Research, Thomas J. Watson Research Center, Yorktown Heights, NY, USA DOI: 10.1109/ICMTS.2008.4509330 HOVER FOR ABSTRACT | PDF Xplore | |
| Spacing impact on MOSFET mismatch A. Cathignol, S. Mennillo1, S. Bordez2, L. Vendrame1, G. Ghibaudo3 STMicroelectronics, Crolles, FR 1STMicroelectronics, Advanced R&D, NVMTD-FMG, Agrate, Italy 2STMicroelectronics-Crolles 2 Alliance, Crolles, France 3IMEP, Minatec, INPG Paris Louis Néel, Grenoble, France DOI: 10.1109/ICMTS.2008.4509320 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement of the MOSFET drain current variation under high gate voltage Tetsuo Chagawa, Kazuo Terada1, Jianyu Xiang1, Katsuhiro Tsuji, Takaaki Tsunomura, Akio Nishida Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan 1MIRAI-Selete, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2008.4509319 HOVER FOR ABSTRACT | PDF Xplore | |
| Beyond van der Pauw: Sheet resistance determination from arbitrarily shaped planar four-terminal devices with extended contacts M. Cornils, O. Paul1 Albert-Ludwigs-Universitat Freiburg, Freiburg im Breisgau, Baden-Württemberg, DE 1Department of Microsystems Engineering (IMTEK), University of Freiburg, Germany DOI: 10.1109/ICMTS.2008.4509309 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement and optimisation of bond strength for anodic bonding of glass to dielectric thin films G. Cummins, H. Lin, A. J. Walton Institute of Micro and Nano Systems Institute of Integrated Systems, University of Edinburgh, UK DOI: 10.1109/ICMTS.2008.4509324 HOVER FOR ABSTRACT | PDF Xplore | |
| New method for non destructive snap-back characterization in multi-finger power MOSFETs F. Dieudonne, A. Constant, J. Rosa, B. Gautheron, J. -F. Revel ST Microelectronics, Crolles Site, Crolles, France DOI: 10.1109/ICMTS.2008.4509328 HOVER FOR ABSTRACT | PDF Xplore | |
| New Y-function-based methodology for accurate extraction of electrical parameters on nano-scaled MOSFETs D. Fleury, A. Cros, H. Brut, G. Ghibaudo1 STMicroelectronics Group, Crolles, France 1IMEP MINATEC, Grenoble, France DOI: 10.1109/ICMTS.2008.4509332 HOVER FOR ABSTRACT | PDF Xplore | |
| Highly automated test chip layout and test plan development for parametric electrical test A. Gabrys, W. Greig, A. J. West, P. Lindorfer, W. French National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2008.4509321 HOVER FOR ABSTRACT | PDF Xplore | |
| Rapid characterization of parametric distributions using a multi-meter J. Hayes, K. Agarwal, S. Nassif IBM Austin Research Laboratory, Austin, TX, USA DOI: 10.1109/ICMTS.2008.4509308 HOVER FOR ABSTRACT | PDF Xplore | |
 | High density test structure array for accurate detection and localization of soft fails C. Hess, M. Squcciarini, Shia Yu1, J. Burrows, Jianjun Cheng, R. Lindley1, A. Swimmer1, S. Winters1 PDF Solutions, Inc.orporated, San Diego, CA, USA 1PDF Solutions, Inc.orporated, San Jose, CA, USA DOI: 10.1109/ICMTS.2008.4509327 HOVER FOR ABSTRACT | PDF Xplore |
| Characterization of T-shaped terminal impedances of differential short stubs in advanced CMOS technology Chiaki Inui, Minoru Fujishima School of Frontier Science, University of Tokyo, Kashima, Chiba, Japan DOI: 10.1109/ICMTS.2008.4509336 HOVER FOR ABSTRACT | PDF Xplore | |
| Operational amplifier based test structure for transistor threshold voltage variation B. L. Ji, D. J. Pearson, I. Lauer, F. Stellari, D. J. Frank, L. Chang, M. B. Ketchen IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA DOI: 10.1109/ICMTS.2008.4509305 HOVER FOR ABSTRACT | PDF Xplore | |
| Short-flow test chip utilizing fast testing for defect density monitoring in 45nm M. Karthikeyan, W. Cote, L. Medina, E. Shiling, A. Gasasira, A. Henning, W. Ferrante, M. Craig, T. Merbeth IBM Systems and Technology Group, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.2008.4509314 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization of MOSFETs intrinsic performance using in-wafer advanced Kelvin-contact device structure for high performance CMOS LSIs Rihito Kuroda, Akinobu Teramoto1, Takanori Komuro2, Weitao Cheng, Syunichi Watabe, Ching Foa Tye, Shigetoshi Sugawa1, Tadahiro Ohmi1 Graduate School of Engineering, University of Tohoku, Sendai, Japan 1New industry Creation Hatchery Center, University of Tohoku, Japan 2Agilent Technologies International Japan Limited, Japan DOI: 10.1109/ICMTS.2008.4509331 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for characterising low voltage coplanar EWOD system Yifan Li, Mita Yoshio1, L. Haworth, W. Parkes, Masanori Kubota1, A. Walton School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK 1University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2008.4509318 HOVER FOR ABSTRACT | PDF Xplore | |
| Conduit Diffusion of Dopants in Tungsten Silicide Layers S. Liao, M. Bain, P. Baine, D. W. McNeill, B. M. Armstrong, H. S. Gamble Northern Ireland Semiconductor Research Centre, Queen's University of Belfast, Northern Ireland, UK DOI: 10.1109/ICMTS.2008.4509315 HOVER FOR ABSTRACT | PDF Xplore | |
| An evaluation of test structures for measuring the contact resistance of 3-D bonded interconnects H. Lin, S. Smith, J. T. M. Stevenson, A. M. Gundlach, C. C. Dunare, A. J. Walton Institute for Integrated Micro and Nano Systems, Part of the Institute for Integrated Systems, School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2008.4509326 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for the evaluation of 3D chip interconnection schemes A. Mathewson, J. Brun1, R. Franiatte1, A. Nowodzinski1, R. Ancient1, N. Sillon1, F. Depoutot2, B. Dubois-Bonvalot2 Tyndall National Institute, Cork, Ireland 1CEA-Leti-Minatec, Grenoble, France 2Hardware Security Research Group Gemalto, Grenoble, France DOI: 10.1109/ICMTS.2008.4509325 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure for channel length engineering of NAND gates in standard cell library T. Matsuda, Y. Sugiyama, J. Takakuwa, H. Iwata, T. Ohzone1 Department of Information Systems Engineering, Toyama Prefectural University, Japan 1Dawn Enterprise, Nagoya, Japan DOI: 10.1109/ICMTS.2008.4509317 HOVER FOR ABSTRACT | PDF Xplore | |
| A study of variation in characteristics and subthreshold humps for 65-nm SRAM using newly developed SRAM cell array test structure A. Mizumura, T. Suzuki, T. Arima1, H. Maeda1, H. Ammo Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation, Astugi, Kanagawa, Japan 1Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation, Sony LSI Design Incorporated, Astugi, Kanagawa, Japan DOI: 10.1109/ICMTS.2008.4509306 HOVER FOR ABSTRACT | PDF Xplore | |
| Test circuit for measuring pulse widths of single-event transients causing soft errors B. Narasimham, M. J. Gadlage, B. L. Bhuva, R. D. Schrimpf, L. W. Massengill, W. T. Holman, A. F. Witulski, K. F. Galloway Dept. of Electrical Engineering and Computer Science, Vanderbilt University, Nashville, TN, USA DOI: 10.1109/ICMTS.2008.4509329 HOVER FOR ABSTRACT | PDF Xplore | |
| Life condition monitoring on smart power devices using a sequence of current and charge-based capacitance measurements Zhenqiu Ning, E. de Vylder, F. Bauwens, B. Vlachakis, H. -X. Delecourt, R. Gillon, P. Van Torre1, D. Hegsted AMI Semiconductor Belgium bvba, Oudenaarde, Belgium 1Hogeschool GENT, GENT, Belgium DOI: 10.1109/ICMTS.2008.4509312 HOVER FOR ABSTRACT | PDF Xplore | |
| Advanced test structure design for dielectric characterisation of novel high-k materials J. A. O'Sullivan, Wenbin Chen1, K. G. McCarthy2, G. M. Cream2 Dept. of Electrical and Electronic Engineering, University College, Cork, Ireland 1Department of Electrical and Electronic Engineering, University College Cork, Ireland 2Tyndall National Institute, Ireland DOI: 10.1109/ICMTS.2008.4509335 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure definition for dummy metal filling strategy dedicated to advanced integrated RF inductors C. Pastore, F. Gianesello, D. Gloria, E. Serret, P. Benech1 STMicroelectronics Group, Crolles, France 1IMEP, Grenoble, France DOI: 10.1109/ICMTS.2008.4509341 HOVER FOR ABSTRACT | PDF Xplore | |
| Mixed test structure for soft and hard defect detection F. Rigaud, J. M. Portal, H. Aziza, D. Nee1, J. Vast1, F. Argoud1, B. Borot2 IMT-Technopole de Chateau Gombert, Institut Materiaux Microelectronique Nanosciences de Provence, UMR CNRS 6242, Marseilles, France 1ST Microelectronics, ZI Rousset, Rousset, France 2STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2008.4509313 HOVER FOR ABSTRACT | PDF Xplore | |
| Comb capacitor structures for measurement of post-processed layers D. Roy, J. H. Klootwijk1, N. A. M. Verhaegh, H. H. A. J. Roosen2, R. A. M. Wolters NXP Semiconductors, Eindhoven, The Netherlands 1NXP Semiconductors Research, Eindhoven, Netherlands 2Philips Research, Eindhoven, The Netherlands DOI: 10.1109/ICMTS.2008.4509339 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel biasing technique for addressable parametric arrays B. Smith, U. Annamalai1, A. Arriordaz, V. Kolagunta, J. Schmidt, M. Shroff Freescale Semiconductor, Austin, TX, USA 1University of Arkansas, Austin, TX, USA DOI: 10.1109/ICMTS.2008.4509333 HOVER FOR ABSTRACT | PDF Xplore | |
| Comparison of measurement techniques for advanced photomask metrology S. Smith, A. Tsiamis, M. McCallum1, A. C. Hourd2, J. T. M. Stevenson3, A. J. Walton, R. G. Dixson, R. A. Allen, J. E. Potzick2, M. W. Cresswell2, N. G. Orji2 National Institute for Standards and Technology, Gaithersburg, MD, USA 1Eastfield Industrial Estate, Compugraphics International Limited, Glenrothes, Fife, UK 2Institute of Integrated Micro and Nano Systems, School of Engineering and Electronics Scottish Microelectronics Centre, University of Edinburgh, UK 3Nikon Precision Europe GmbH, West Lothian, UK DOI: 10.1109/ICMTS.2008.4509311 HOVER FOR ABSTRACT | PDF Xplore | |
| On-mask mismatch resistor structures for the characterisation of maskmaking capability S. Smith, A. Tsiamis1, M. McCallum2, A. C. Hourd2, J. T. M. Stevenson, A. J. Walton, S. Enderling Institute of Integrated Micro and Nano Systems, The University of Edinburgh, UK 1Nikon Precision Europe GmbH, West Lothian, UK 2Nikon Precision Europe GmbH, Appleton Place, Appleton Parkway, Livingston, West Lothian, UK DOI: 10.1109/ICMTS.2008.4509343 HOVER FOR ABSTRACT | PDF Xplore | |
| A study of cross-bridge kelvin resistor structures for reliable measurement of low contact resistances N. Stavitski, J. H. Klootwijk1, H. W. van Zeijl2, A. Y. Kovalgin, R. A. M. Wolters3 MESA + Institute for Nanotechnology, University of Twente, Enschede, The Netherlands 1Philips Research, High Tech Campus 4, Eindhoven, The Netherlands 2DIMES, Delft University of Technology, Delft, CT, The Netherlands 3NXP Research Eindhoven, Eindhoven, AE, The Netherlands DOI: 10.1109/ICMTS.2008.4509338 HOVER FOR ABSTRACT | PDF Xplore | |
| Circular Geometry MOS Transistor Analysis of SOI Substrates for High Energy Physics Particle Detectors S. L. Suder, F. H. Ruddell, J. H. Montgomery1, B. M. Armstrong1, H. S. Gamble1, G. Casse1, T. Bowcock1, P. P. Allport Department of Physics, University of Liverpool, UK 1Northern Ireland Semiconductor Research Centre, Queen''s University Belfast, Belfast, UK DOI: 10.1109/ICMTS.2008.4509322 HOVER FOR ABSTRACT | PDF Xplore | |
| Fully considered layout variation analysis and compact modeling of MOSFETs and its application to circuit simulation Takuji Tanaka, Akira Satoh, Mitsuru Yamaji1, Osamu Yamasaki, Hiroshi Suzuki1, Tsuyoshi Sakata, Yoshio Inoue, Masaru Ito2, Seiichiro Yamaguchi2, Hiroshi Arimoto Fujitsu Laboratories Limited, Akiruno, Tokyo, Japan 1FUJITSU VLSI Limited, Akiruno, Tokyo, Japan 2FUJITSU VLSI Laboratories Limited, Akiruno, Tokyo, Japan DOI: 10.1109/ICMTS.2008.4509342 HOVER FOR ABSTRACT | PDF Xplore | |
| Mismatch characterization of a high precision resistor array test structure Weidong Tian, P. Steinmann, E. Beach, I. Khan, P. Madhani Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.2008.4509307 HOVER FOR ABSTRACT | PDF Xplore | |
| Identifying dielectric and resistive electrode losses in high-density capacitors at radio frequencies M. P. J. Tiggelman, K. Reimann1, J. Liu1, M. Klee, W. Keur2, R. Mauczock2, J. Schmitz2, R. J. E. Hueting Philips Research, Eindhoven, Netherlands 1NXP Semiconductors Research, Eindhoven, Netherlands 2Department of Semiconductor Components,Institute for Nanotechnology, University of Twente, MESA Research Institute, Enschede, Netherlands DOI: 10.1109/ICMTS.2008.4509337 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for characterizing metal thickness in damascene CMP technology A. Toffoli, S. Maitrejean, J. D. de Pontcharra, F. de Crecy, D. Bouchu, L. Arnaud, F. Boulanger CEA-LETI/MINATEC, Grenoble, France DOI: 10.1109/ICMTS.2008.4509340 HOVER FOR ABSTRACT | PDF Xplore | |
| 2.6-GHz RF inductive power delivery for contactless on-wafer characterization J. Tompson, A. Dolin1, P. Kinget Department of Electrical Engineering, Columbia University, New York, NY, USA 1Anadigics, Warren, NJ, USA DOI: 10.1109/ICMTS.2008.4509334 HOVER FOR ABSTRACT | PDF Xplore | |
| Investigation of Electrical and Optical CD Measurement Techniques for the Characterisation of On-Mask GHOST Proximity Corrected Features A. Tsiamis, S. Smith1, M. McCallum2, A. C. Hourd3, O. Toublan3, J. T. M. Stevenson3, A. J. Walton3 French Branchraphics, Mentor Limited, Saint Ismier, France 1Eastfield Industrial Estate, Compugraphics International Limited, Glenrothes, Fife, UK 2Nikon Precision Europe GmbH, West Lothian, UK 3Institute of Integrated Micro and Nano Systems, School of Engineering and Electronics, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2008.4509310 HOVER FOR ABSTRACT | PDF Xplore | |
| Prediction of stress-induced characteristic changes for small-scale analog IC Naohiro Ueda, Eri Nishiyama, Hideyuki Aota, Hirobumi Watanabe Electronic Devices Company, Ricoh Company Limited, Kato, Hyogo, Japan DOI: 10.1109/ICMTS.2008.4509323 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel high speed automatic layout system to place and route test structures for parametric test capability A. J. West, S. Mondal, D. Patra, K. Goswami, S. Sural1 Indian Institute of Technology, Kharagpur, India 1National Semiconductor Corporation, Santa Clara, USA DOI: 10.1109/ICMTS.2008.4509316 HOVER FOR ABSTRACT | PDF Xplore | |
| Influence of STI stress on drain current matching in advanced CMOS N. Wils, H. Tuinhout, M. Meijer1 NXP-TMSC Research Center, Eindhoven, Netherlands 1NXP Semiconductors Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2008.4509345 HOVER FOR ABSTRACT | PDF Xplore | |
| Physics and modeling of transistor matching degradation under matched external stress Xiaoju Wu, Zhenwu Chen, P. Madhani Analog Technology Development, Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.2008.4509344 HOVER FOR ABSTRACT | PDF Xplore |
