IEEE International Conference on Microelectronic Test Structures
ICMTS 2005 Program
2005 Program Booklet
By First Author
| Test structure for performance evaluation of 3 dimensional FinFETs Young Joon Ahn, Hye Jin Cho, Hee Soo Kang, Choong-Ho Lee, Chul Lee, Jae-man Yoon, Tae Yong Kim, Eun Suk Cho, Suk-kang Sung, Donggun Park, Kinam Kim, Byung-Il Ryu Device Research Team, Research and Development center, Samung Electronics Company, Yongin si, Gyeonggi, South Korea DOI: 10.1109/ICMTS.2005.1452221 HOVER FOR ABSTRACT | PDF Xplore | |
| Extraction of critical dimension reference feature CDs from new test structure using HRTEM imaging R. A. Allen, A. Hunt1, C. E. Murabito, B. Park, W. F. Guthrie2, M. W. Cresswell Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Accurel Systems International Corporation, Sunnyvale, CA, USA 2Statistical Engineering Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2005.1452203 HOVER FOR ABSTRACT | PDF Xplore | |
| A new method for precise evaluation of dynamic recovery of negative bias temperature instability S. Aota, S. Fujii1, Z. W. Jin, Y. Ito2, K. Utsumi, E. Morifuji, S. Yamada, F. Matsuoka, T. Noguchi System LSX Division I, Semiconductor Company, Toshiba Corporation, Yokohama, Kanagawa, Japan 1Agilent Technologies International Japan Limited, Yokohama, Kanagawa, Japan 2Test System Development Department, Toshiba Microelectronics Corporation, Yokohama, Kanagawa, Japan DOI: 10.1109/ICMTS.2005.1452262 HOVER FOR ABSTRACT | PDF Xplore | |
| Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design N. D. Arora, Li Song, S. Shah, A. Sinha, V. Chang Cadence Design Systems, San Jose, CA, USA DOI: 10.1109/ICMTS.2005.1452281 HOVER FOR ABSTRACT | PDF Xplore | |
| Extraction of time dependent data from time domain reflection transmission line pulse measurements [ESD protection design] R. A. Ashton White Mountain Laboratories, Phoenix, AZ, USA DOI: 10.1109/ICMTS.2005.1452278 HOVER FOR ABSTRACT | PDF Xplore | |
| Design and characterization of a post-processed copper heat sink for smart power drivers [lateral nDMOS drivers] G. Van den bosch, T. Webers, E. Driessens, B. Elattari, D. Wojciechowski1, P. Gassot1, P. Moens1, G. Groeseneken IMEC, Leuven, Belgium 1AMI Semiconductor Belgium BVBa, Oudenaarde, Belgium DOI: 10.1109/ICMTS.2005.1452210 HOVER FOR ABSTRACT | PDF Xplore | |
| Capacitance characterization in integrated circuit development: the intimate relationship of test structure design, equivalent circuit and measurement methodology G. A. Brown Sematech Inc., Austin, TX, USA DOI: 10.1109/ICMTS.2005.1452268 HOVER FOR ABSTRACT | PDF Xplore | |
| A failure analysis test structure for deep sub-micron CMOS copper interconnect technologies A. Cabrini, D. Cantarelli1, P. Cappelletti2, R. Casiraghi2, D. Iezzi2, A. Maurelli2, M. Pasotti2, P. L. Rolandi2, G. Torelli Department of Electronics, University of Pavia, Agrate-Brianza, Milan, Italy 1Central R&D, STMicroelectronics, Agrate Brianza (MI), Italy 2Central R&D, STMicroelectronics, Agrate-Brianza, Agrate Brianza (MI), Italy DOI: 10.1109/ICMTS.2005.1452279 HOVER FOR ABSTRACT | PDF Xplore | |
| Accelerated life time estimation of electrostatic microactuators B. Caillard, Y. Mita1, Y. Fukuta2, T. Shibata1, H. Fujita2 LIMMS, IIS, CNRS, Shibata-Mita Laboratory, Department Electl Engineering, University of Tokyo, Bunkyo, Tokyo, Japan 1Shibata-Mita Laboratory, Department Electl Engineering, University of Tokyo, Bunkyo, Tokyo, Japan 2CIRMM, IIS, Shibata-Mita Laboratory, Department Electl Engineering, University of Tokyo, Bunkyo, Tokyo, Japan DOI: 10.1109/ICMTS.2005.1452234 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel CBCM method free from charge injection induced errors: investigation into the impact of floating dummy-fills on interconnect capacitance Y. W. Chang, H. W. Chang1, T. C. Lu1, Y. King2, W. Ting1, J. Ku1, C. Y. Lu1 Nstitute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan 1Technology Development Center, Macronix International Co., Ltd, Hsinchu, Taiwan 2Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2005.1452275 HOVER FOR ABSTRACT | PDF Xplore | |
| Speed - accuracy trade-off for measurement and characterization of the matching performance of SiGe:C HBTs, applied to a 200 GHz technology L. J. Choi, R. Venegas, S. Decoutere IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.2005.1452248 HOVER FOR ABSTRACT | PDF Xplore | |
| Comparison of SEM and HRTEM CD measurements extracted from test-structures having feature linewidths from 40 nm to 240 nm M. W. Cresswell, B. Park, R. A. Allen, W. F. Guthrie1, R. G. Dixson2, W. M. Tan, C. E. Murabito3 Semiconductor Electronics Division, Electronics and Electrical Engineering Laboratory, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Statistical Engineering Division, Information Technology Laboratory, National Institute for Standards and Technology, Gaithersburg, MD, USA 2Precision Engineering Division, Manufacturing Engineering Laboratory, National Institute for Standards and Technology, Gaithersburg, MD, USA 3NA DOI: 10.1109/ICMTS.2005.1452204 HOVER FOR ABSTRACT | PDF Xplore | |
| Experimental analysis of a Ge-HfO2-TaN gate stack with a large amount of interface states J. A. Croon, B. Kaczer, G. S. Lujan1, S. Kubicek, G. Groeseneken1, M. Meuris IMEC, Leuven, Belgium 1ESAT, Katholieke Universiteit Leuven, Belgium DOI: 10.1109/ICMTS.2005.1452261 HOVER FOR ABSTRACT | PDF Xplore | |
| New extraction method for gate bias dependent series resistance in nanometric double gate transistors A. Cros, S. Harrison, R. Cerutti, P. Coronel, G. Ghibaudo1, H. Brut STMicroelectronics, Crolles, France 1IMEP, Grenoble, France DOI: 10.1109/ICMTS.2005.1452225 HOVER FOR ABSTRACT | PDF Xplore | |
| Mismatch characterisation of chip interconnect resistance J. Deveugele, Libin Yao, M. Steyaert, W. Sansen Katholieke Universiteit Leuven, Leuven, Belgium DOI: 10.1109/ICMTS.2005.1452259 HOVER FOR ABSTRACT | PDF Xplore | |
| MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances R. Difrenza, K. Rochereau1, T. Devoivre, B. Tavel1, B. Duriez1, D. Roy, S. Jullian1, A. Dezzani, R. Boulestin, P. Stolk1, F. Arnaud STMicroelectronics, Crolles, France 1Philips Semiconductors, Crolles, France DOI: 10.1109/ICMTS.2005.1452247 HOVER FOR ABSTRACT | PDF Xplore | |
| Suspended Greek cross test structures for measuring the sheet resistance of non-standard cleanroom materials S. Enderling, C. L. Brown1, S. Smith, M. H. Dicks, J. T. M. Stevenson, A. W. S. Ross, M. Mitkova1, M. N. Kozicki1, A. J. Walton School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK 1Center for Solid State Electronics Research, Arizona State University, Tempe, AZ, USA DOI: 10.1109/ICMTS.2005.1452202 HOVER FOR ABSTRACT | PDF Xplore | |
| Design and implementation of an ultra high precision parametric mismatch measurement system T. Ewert, H. Tuinhoutt1, N. Wils1, J. Olsson Uppsala University, Ångström Laboratory, Sweden 1philips Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2005.1452249 HOVER FOR ABSTRACT | PDF Xplore | |
| An improved LDMOS transistor model that accurately predicts capacitance for all bias conditions S. F. Frere, P. Moens1, B. Desoete1, Wojciechowski D1, A. J. Walton School of Engineering and Electronics, SMC, University of Edinburgh, Edinburgh, UK 1AMI Semiconductor Belgium BVBa, Oudenaarde, Belgium DOI: 10.1109/ICMTS.2005.1452226 HOVER FOR ABSTRACT | PDF Xplore | |
| Recent trends in reliability assessment of advanced CMOS technologies G. Groeseneken, R. Degraeve, B. Kaczer, P. Roussel IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.2005.1452230 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for the characterization of deep trench isolation [The following paper has been withdrawn by the authors] S. Hausser, R. Albus1, H. Schligtenhorst Philips Semiconductors GmbH, Boeblingen 1Philips Semiconductors GmbH, Boeblingen, Germany DOI: 10.1109/ICMTS.2005.1452209 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel test fixture with enhanced signal port isolation capability for on-wafer microwave measurements T. Kaija, E. O. Ristolainen Institute of Electronics, Tampere University of Technology, Tampere, Finland DOI: 10.1109/ICMTS.2005.1452257 HOVER FOR ABSTRACT | PDF Xplore | |
| 90nm CMOS technology characterization at transfer and ramp A. Kelleher, D. Gourley, A. M. Holmes, T. Hepburn, C. Farrell, R. Groves, T. Taskin, J. McMillan, W. Rawlins Intel (Ireland) Limited, Kildare, Ireland DOI: 10.1109/ICMTS.2005.1452208 HOVER FOR ABSTRACT | PDF Xplore | |
 | High speed test structures for in-line process monitoring and model calibration [CMOS applications] M. Ketchen, M. Bhushan1, D. Pearson IBM Research Center, Yorktown Heights, NY, USA 1IBM S and TG, Yorktown Heights, NY, USA DOI: 10.1109/ICMTS.2005.1452212 HOVER FOR ABSTRACT | PDF Xplore |
| Simple modeling expressions for substrate network of on-chip inductors I. C. H. Lai, M. Fujishima School of Frontier Sciences, University of Tokyo, Japan DOI: 10.1109/ICMTS.2005.1452240 HOVER FOR ABSTRACT | PDF Xplore | |
| RF-ESD design and measurement of CMOS LNAs: a comparison between diode and inductive protection P. Leroux, M. Steyaert1 Katholieke Hogeschool Kempen, Belgian Nuclear Research Centre, Geel, Belgium 1ESAT-MICAS, Leuven, Belgium DOI: 10.1109/ICMTS.2005.1452256 HOVER FOR ABSTRACT | PDF Xplore | |
| Assessment of a 90nm PMOS NBTI in the form of products failure rate H. Masuda, D. G. Pierce1, K. Nishitsuru2, K. Machida3 Semiconductor Technology Academic Research Center, Yokohama, Japan 1Sandia Technologies, Inc., Albuquerque, NM, USA 2Agilent Technologies International Japan Limited, Hachioji, Tokyo, Japan 3Mathematical Systems Institute, Inc., Tokyo, Japan DOI: 10.1109/ICMTS.2005.1452231 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure for spatial analysis of hot-carrier-induced photoemission in n-MOSFET T. Matsuda, T. Tanaka, H. Iwata, T. Ohzone1, K. Yamashita2, N. Koike2, K. Tatsuuma2 Department of Electronics and Informatics, Toyama Prefectural University Kurokawa, Kosugi-machi, Imizu-gun, Toyama, Japan 1Faculty of Computer Science and System Engineering, Okayama Prefectural University, Soja-Shi, Okayama, Japan 2ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electric Ind. Co., Ltd., Kyoto, Japan DOI: 10.1109/ICMTS.2005.1452217 HOVER FOR ABSTRACT | PDF Xplore | |
| A study of 90nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure A. Mizumura, T. Ohishi, N. Yokoyama1, M. Nonaka1, S. Tanaka1, H. Ammo Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporation, Atsugi, Kanagawa, Japan 1Nagasaki Technology Center, Sony Semiconductor Kyusyu Corporation, Isahaya, Nagasaki, Japan DOI: 10.1109/ICMTS.2005.1452215 HOVER FOR ABSTRACT | PDF Xplore | |
| A self heating test structure using poly resistors and P+/N diodes to characterize anomalous charge transfers in embedded flash memories P. Mora, P. Waltz, S. Renard, P. Candelier STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2005.1452219 HOVER FOR ABSTRACT | PDF Xplore | |
| A simple and accurate capacitance ratio measurement technique for integrated circuit capacitor arrays Zhenqiu Ning, L. De Schepper, H. . -X. Delecourt, R. Gillon, M. Tack AMI Semiconductor Belgium bvba, Oudenaarde, Belgium DOI: 10.1109/ICMTS.2005.1452251 HOVER FOR ABSTRACT | PDF Xplore | |
| Impact of mask alignment on the tunneling field effect transistor (TFET) T. Nirschl, U. Schaper, J. Einfeld, S. Henzler, M. Sterkel1, J. Singer, M. Fulde1, W. Hansch1, G. Georgakos, D. Schmitt-Landsiedell2 Infineon Technologies AG, Munich, Germany 1Institute for Technical Electronics, Technical University, Munich, Germany 2NA DOI: 10.1109/ICMTS.2005.1452216 HOVER FOR ABSTRACT | PDF Xplore | |
| Verification of layout efficient shield-based de-embedding techniques for on-wafer HBT characterisation up to 30 GHz J. A. O'Sullivan, K. G. McCarthy, A. C. Murphy1, P. J. Murphy Dept. of Electrical and Electronic Engineering, University College Cork, Cork, Ireland 1Freescale Semiconductor, Cork, Ireland DOI: 10.1109/ICMTS.2005.1452241 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure to measure sheet resistances of highly-doped-drain and lightly-doped-drain in CMOSFET T. Ohzone, K. Okada, T. Morishita, K. Komoku, T. Matsuda1, H. Iwata1 Department of Communication Engineering, Okayama Prefectural University, Soja, Okayama, Japan 1Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.2005.1452224 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel mobility-variation-free extraction technique of capacitance coupling coefficient for stacked flash memory cell T. Okagaki, M. Tanizawa, M. Fujinaga, T. Kunikiyo, H. Yuki, K. Ishikawa, Y. Nishikawa, T. Eimori, M. Inuishi, Y. Oji Renesas Technology Corporation, Hyogo, Japan DOI: 10.1109/ICMTS.2005.1452270 HOVER FOR ABSTRACT | PDF Xplore | |
| RF monitoring test structures for advanced RF technologies working up to 100GHz with less than 80µm width A. Perrotin, D. Gloria Central Research and Development, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2005.1452264 HOVER FOR ABSTRACT | PDF Xplore | |
| Multi-purpose EM test structure with electrical verification of the failure spot demonstrated using SWEAT for fast wafer level reliability monitoring A. Pietsch, A. Martin, J. Fazekas Central Reliability Methodology Department, Infineon Technologies, Munich, Germany DOI: 10.1109/ICMTS.2005.1452232 HOVER FOR ABSTRACT | PDF Xplore | |
| Substrate isolation in 0.18um CMOS technology G. A. Rezvani, Jon Tao RF Micro Devices, Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2005.1452244 HOVER FOR ABSTRACT | PDF Xplore | |
| Charge pumping at radio frequencies [MOSFET device interface state density measurement] G. T. Sasse, H. de Vries, J. Schmitz MESA Research Institute, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS.2005.1452273 HOVER FOR ABSTRACT | PDF Xplore | |
| Parameter variation on chip-level U. Schaper, J. Einfeld, A. Sauerbrey Communication Corporate Logic, Infineon Technologies, Munich, Germany DOI: 10.1109/ICMTS.2005.1452250 HOVER FOR ABSTRACT | PDF Xplore | |
| On-wafer radiation pattern measurements of integrated antennas on standard BiCMOS and glass processes for 40-80GHz applications N. Segura, S. Montusclat1, C. Person, S. Tedjini2, D. Gloria1 ENST Bretagne-UBO, LEST UMR 6165 GET, Brest, France 1Central Research and Development, Q-TPS Laboratory, STMicroelectronics, Crolles, France 2ESISAR/LCIS, Valence, France DOI: 10.1109/ICMTS.2005.1452238 HOVER FOR ABSTRACT | PDF Xplore | |
| Improved test structures for the electrical measurement of feature size on an alternating aperture phase-shifting mask S. Smith, A. J. Walton, M. McCallum1, A. C. Hourd2, J. T. M. Stevenson, A. W. S. Ross School of Engineering and Electronics, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1Nikon Cort, Nikon Precision Europe, Livingston, UK 2Eastfield Industrial Estate, Compugraphics International Limited, Glenrothes, Fife, UK DOI: 10.1109/ICMTS.2005.1452205 HOVER FOR ABSTRACT | PDF Xplore | |
| Novel realistic short structure construction for parasitic resistance de-embedding and on-wafer inductor characterization J. Tao, P. Findley, G. A. Rezvani RF Micro Devices, Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2005.1452260 HOVER FOR ABSTRACT | PDF Xplore | |
| Physical meaning of σ/ value estimated with VTH-mismatch evaluation circuit K. Terada, T. Yamauchi, A. Ueki Faculty of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan DOI: 10.1109/ICMTS.2005.1452254 HOVER FOR ABSTRACT | PDF Xplore | |
| EOT measurement for ultra-thin gate dielectrics using LC resonance circuit [MOS devices] A. Teramoto, M. Komura1, R. Kuroda1, K. Watanabe1, S. Sugawa1, T. Ohmi New Industry Creation Hatchery Center, Tohoku University, Sendai, Japan 1Graduate School of Engineering, Tohoku University, Aoba-ku, Sendai, Japan DOI: 10.1109/ICMTS.2005.1452271 HOVER FOR ABSTRACT | PDF Xplore | |
| New applications of cross-talk-based capacitance measurements [CMOS ICs] L. Vendrame, L. Bortesi, A. Bogliolo1 STMicroelectranics, FTM Research and Development, Agrate-Brianza, Italy 1STI, University of Urbino, Urbino, Italy DOI: 10.1109/ICMTS.2005.1452283 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement of inner-chip variation and signal integrity by a 90-nm large-scale TEG [test element group] M. Yamamoto, Y. Hayasi1, H. Endo1, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan 1Hitachi ULSI Systems Company Limited, Tokyo, Japan DOI: 10.1109/ICMTS.2005.1452265 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization and model of on-chip flicker noise with deep Nwell (DNW) isolation for 130nm and beyond SOC M. T. Yang, D. C. W. Kuo, C. W. Kuo, Y. J. Wang, P. P. C. Ho, T. J. Yeh, S. Liu Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2005.1452242 HOVER FOR ABSTRACT | PDF Xplore |
