IEEE International Conference on Microelectronic Test Structures
ICMTS 2004 Program
2004 Program Booklet
By First Author
| A novel test-structure for detail interconnect fabric diagnosis for 90nm process S. Akutsu, N. Ishihara1, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan 1Fuji Research Institute Company, Tokyo, Japan DOI: 10.1109/ICMTS.2004.1309306 HOVER FOR ABSTRACT | PDF Xplore | |
| Recent developments in producing test-structures for use as critical dimension reference materials R. A. Allen, R. Patel, M. W. Cresswell, C. E. Murabito, B. Park, M. D. Edelstein, L. W. Linholm Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2004.1309297 HOVER FOR ABSTRACT | PDF Xplore | |
| Design guide and process quality improvement for treatment of device variations in an LSI chip M. Aoki, S. Ohkawa, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan DOI: 10.1109/ICMTS.2004.1309479 HOVER FOR ABSTRACT | PDF Xplore | |
| Test chip characterization of X architecture diagonal lines for SoC design N. D. Arora, L. Song, S. Shah, K. Joshi, K. Thumaty, A. Fujimura, J. P. Schoellkopf1, H. Brut1, M. Smayling2, T. Nagata2 Cadence Design Systems, Inc., San Jose, CA, USA 1STMicroelectronics, Crolles, France 2Applied Materials, Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS.2004.1309305 HOVER FOR ABSTRACT | PDF Xplore | |
| Transmission line pulse measurements: a tool for developing ESD robust integrated circuits R. A. Ashton White Mountain Laboratories, Phoenix, AZ, USA DOI: 10.1109/ICMTS.2004.1309291 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel measurement method of the spatial carrier lifetime profile based on the OCVD technique S. Bellone, G. D. Licciardo, H. C. Neitzert Depart of Information Engineering and Electrical Engineering, University of Salerno, Fisciano, Salerno, Italy DOI: 10.1109/ICMTS.2004.1309311 HOVER FOR ABSTRACT | PDF Xplore | |
| Accuracy improvement of the "Single Pattern Driver" method for the characterization of interconnect capacitance in the context of nanometer technology development H. Brut, S. Martin, B. Froment STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2004.1309501 HOVER FOR ABSTRACT | PDF Xplore | |
| Development and extraction of high-frequency SPICE models for metal-insulator-metal capacitors W. Z. Cai, S. C. Shastri, M. Azam, C. Hoggatt, G. H. Loechelt, G. M. Grivna, Y. Wen, S. Dow Silicon IC Technology Development, ON Semiconductor Corporation, Phoenix, AZ, USA DOI: 10.1109/ICMTS.2004.1309485 HOVER FOR ABSTRACT | PDF Xplore | |
| Flicker noise characterization of Co-silicide/SiGe contacts using TLM test structures Kun-Ming Chen, Guo-Wei Huang National Nano Device Laboratories, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309472 HOVER FOR ABSTRACT | PDF Xplore | |
| MOSFET drain and induced-gate noise modeling and experimental verification for RF IC design Chih-Hung Chen, Feng Li, Yuhua Cheng1 Department of Electrical and Computer Engineering, McMaster University, Hamilton, ONT, Canada 1Skyworks Solutions, Inc., Irvine, CA, USA DOI: 10.1109/ICMTS.2004.1309300 HOVER FOR ABSTRACT | PDF Xplore | |
| Process and device reliability characterization techniques for advanced CMOS technology: the issues and methodologies S. S. Chung Department of Electmnic Engineering, National Chiao Tung University, Taiwan DOI: 10.1109/ICMTS.2004.1309308 HOVER FOR ABSTRACT | PDF Xplore | |
| High frequency test structures definition for the study of flip-chip process effects on inductor coupling in a BiCMOS process C. Clement, B. Van Haaren, D. Gloria ST Microelectronics, Central R&D, Crolles, France DOI: 10.1109/ICMTS.2004.1309478 HOVER FOR ABSTRACT | PDF Xplore | |
| A test chip to characterise P-MOS transistors produced using a novel organometallic material M. H. Dicks, G. M. Broxton1, J. Thomson2, J. Lobban2, A. M. Gundlach, J. T. M. Stevenson, A. J. Walton Institute for Integrated Micro and Nano Systems, Scottish Microelectronics Centre, School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK 1Electronic Engineering & Physics Division, University of Dundee, Dundee, UK 2Division of Physical and Inorganic Chemistry, University of Dundee, Dundee, UK DOI: 10.1109/ICMTS.2004.1309476 HOVER FOR ABSTRACT | PDF Xplore | |
| Electrical characterization of model-based dummy feature insertion in Cu interconnects K. Y. Y. Doong, K. . -C. Lin1, T. . -C. Tseng, Y. C. Lu, S. C. Lin, L. J. Hung, P. S. Ho, S. Hsieh, K. L. Young, M. S. Liang Taiwan Semiconductor Manufacturing Corporation, Shin-Chu, Taiwan 1Taiwan Semiconductor Manufacturing Corp. Shinchu Taiwan, Shinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309307 HOVER FOR ABSTRACT | PDF Xplore | |
| A new test circuit for the matching characterization of npn bipolar transistors J. Einfeld, U. Schaper, U. Kollmer, P. Nelle1, J. Englisch1, M. Stecher1 Corporate Logic, Infineon Technologies, Munich, Germany 1Automotive & Industrial, Infineon Technologies, Munich, Germany DOI: 10.1109/ICMTS.2004.1309465 HOVER FOR ABSTRACT | PDF Xplore | |
| Impact of pocket implant on MOSFET mismatch for advanced CMOS technology J. Mc Ginley, O. Noblanc1, C. Julien2, S. Parihar1, K. Rochereau1, R. Difrenza2, P. Llinares1 Philips Semiconductors, Crolles Cedex, France 1STMicroelectronics, Crolles Cedex, France 2Motorola Inc., Crolles Cedex, France DOI: 10.1109/ICMTS.2004.1309464 HOVER FOR ABSTRACT | PDF Xplore | |
| Optimization of 2.14 um2 6T-SRAM cell by using cell-like test structures S. Hsieh, R. F. Tsui, W. Lin, J. J. Liaw, K. Y. Doong, C. . -M. M. Wu Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan, R. O. C. DOI: 10.1109/ICMTS.2004.1309481 HOVER FOR ABSTRACT | PDF Xplore | |
| Method of and test structures for measuring intra-layer coupling capacitance based on charge based capacitance measurement technique [IC interconnections] Kai-Ye Huang, Chuan-Jane Chao Winbond Electronics Corporation, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309480 HOVER FOR ABSTRACT | PDF Xplore | |
| Design and measurements of test element group wafer thinned to 10 µm for 3D system in package A. Ikeda, T. Kuwata, S. Kajiwara, T. Fujimura, H. Kuriyaki, R. Hattori, H. Ogi1, K. Hamaguchi1, Y. Kuroki Graduate School of Information Science and Electrical Engineering, Department of Electronics, Kyushu University, Fukuoka, Japan 1Hara Seiki Industry Company Limited, Minamata, Kumamoto, Japan DOI: 10.1109/ICMTS.2004.1309471 HOVER FOR ABSTRACT | PDF Xplore | |
| Optimal frequency range selection for full C-V characterization above 45MHz for ultra thin (1.2-nm) nitrided oxide MOSFETs W. Jeamsaksiri, A. Mercha, J. Ramos, S. Decoutere, F. N. Cubaynes1 Inter University Micro Electronics Center, Leuven, Belgium 1Philips Research Leuven, Leuven, Belgium DOI: 10.1109/ICMTS.2004.1309500 HOVER FOR ABSTRACT | PDF Xplore | |
| Experimental measurements and extraction of the silicide/silicon interface resistance for designing high performance MOS transistor Jae-Hun Jeong, Hoon Lim, Soon-Moon Jung, Joon Bum Park, Jae Kyun Park, Kinam Kim Advanced Technology Development Team, Samsung Electronics Co., Ltd, Kiheung-Eup, Yongin-City, Kyungki-Do, Korea (ROK) DOI: 10.1109/ICMTS.2004.1309496 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel method to obtain 3-port network parameters from 2-port measurements [MOSFET example] A. Jha, J. M. Vasi, S. C. Rustagi1, M. B. Patil Department of Electrical Engineering, IIT Bombay, Mumbai, India 1Institute of Microelectronics, Singapore DOI: 10.1109/ICMTS.2004.1309302 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization on ESD devices with test structures in silicon germanium RF BiCMOS process Ming-Dou Ker, Woei-Lin Wu, Chyh-Yih Chang1 Nanoelectronics & Gigascale Systems Laboratory, National Chiao-Tung University, Hsinchu, Taiwan 1Product and ESD Engineering Department, Industrial Technology Research Institute, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309292 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures to verify ESD robustness of on-glass devices in LTPS technology Ming-Dou Ker, Chih-Kang Deng, Sheng-Chieh Yang1, Yaw-Ming Tasi1 Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 1Advanced Technology Research Center, Toppoly Optoelectronics Corporation, Miaoli, Taiwan DOI: 10.1109/ICMTS.2004.1309293 HOVER FOR ABSTRACT | PDF Xplore | |
| An array cell transistor test structure for the leakage current analysis of stacked capacitor DRAMs with diagonal cell scheme Young Pil Kim, Beom Jun Jin, Gi-Sung Yeo, Sun-Ghil Lee, Siyoung Choi, Uin Chung, Joo Tae Moon, Sang U Kim Serniconductor R&D Center, Sarrisung Electronics Company Limited, Yongin si, South Korea DOI: 10.1109/ICMTS.2004.1309467 HOVER FOR ABSTRACT | PDF Xplore | |
| Merits and limitations of circular TLM structures for contact resistance determination for novel III-V HBTs J. H. Klootwijk, C. E. Timmering Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2004.1309489 HOVER FOR ABSTRACT | PDF Xplore | |
| Implementing laser based failure analysis methodologies using test vehicles D. Lewis, V. Pouget, F. Beaudoin1, T. Beauchene, G. Haller2, R. Desplat3, P. Perdu3, P. Fouillat IXL Laboratory, Talence, France 1Thales Microelectronics, Toulouse, France 2STMicroelectronics, Rousset, France 3CNES, Toulouse, France DOI: 10.1109/ICMTS.2004.1309482 HOVER FOR ABSTRACT | PDF Xplore | |
| An accurate RF CMOS gate resistance model compatible with HSPICE H. W. Lin, S. S. Chung, S. C. Wong1, G. W. Huang2 Department of Electronic Engineering, National Chiao Tung University, Taiwan 1Ali Corporation, Taipei, Taiwan 2National Nano Device Laboratory, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309484 HOVER FOR ABSTRACT | PDF Xplore | |
| An impedance-phase angle (Z-theta) method for capacitance extraction of ultra-thin gate dielectrics at intermediate frequency [MOS devices] J. Lin, Chien-Hwa Chang, S. Prasad, W. Loh Characterization and Reliability, LSI Logic Corporation, Milpitas, CA, USA DOI: 10.1109/ICMTS.2004.1309497 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure to verify the robustness of silicided N+/P+ interface Cheng-Yao Lo, Shyue-Shyh Lin, Wei-Ming Chen, Yuh-Jier Mii Advanced Logic-1, Logic Technology Division, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309473 HOVER FOR ABSTRACT | PDF Xplore | |
| Device characterizations and physical models of strained-Si channel CMOS T. Maeda, T. Numata1, T. Mizuno2, K. Usuda2, A. Tanabe2, T. Tezuka2, S. Nakaharai2, J. Koga2, T. Irisawa2, Y. Moriyama2, N. Hirashita2, N. Sugiyama2, S. Takagi2 University of Tokyo, Kawasaki, Japan 1MIRAI-ASET, MIRAI-AIST, Kawasaki, Japan 2Kawasaki, Japan DOI: 10.1109/ICMTS.2004.1309466 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure for two-dimensional analysis of MOSFETs by hot-carrier-induced photoemission T. Matsuda, A. Muramatsu, H. Iwata, T. Ohzone1, K. Yamashita2, N. Koike2, K. Tatsuuma2 Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan 1Faculty of Computer Science and System Engineering, Okayama Prefectural University, Soja, Okayama, Japan 2ULSI Process Technology Development Center, Semiconductor Company, Matsushita Elecrric Indusrrial Company Limited, Minami, Kyoto, Japan DOI: 10.1109/ICMTS.2004.1309474 HOVER FOR ABSTRACT | PDF Xplore | |
| Gate-last MISFET structures and process for high-k and metal gate MISFETs characterization T. Matsuki, K. Torii, T. Maeda, H. Syoji, K. Kiyono, Y. Akasaka, K. Hayashi, N. Kasai, T. Arikado Semiconductor Leading Edge Technologies, Inc., Ibaraki-ken, Japan DOI: 10.1109/ICMTS.2004.1309310 HOVER FOR ABSTRACT | PDF Xplore | |
| Test circuits for extracting sub-100nm MOSFET technology variations with the MOSFET model HiSIM A. Miura-Mattausch, S. Matsumoto, K. Mizoguchi, D. Miyawaki, F. J. Mattausch, S. Itoh1, K. Morikawa1 Department of Electrical Engineering, Hiroshima University, Higashihiroshima, Japan 1Semiconductor Technology Academic Research Center, Japan DOI: 10.1109/ICMTS.2004.1309493 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluating high leakage effects of low VTH circuits using high VTH devices T. Miyazaki, T. Sakurai Institute of Industrial Science, University of Tokyo, Meguro-ku, Tokyo, Japan DOI: 10.1109/ICMTS.2004.1309487 HOVER FOR ABSTRACT | PDF Xplore | |
| Variation status in 100nm CMOS process and below K. Nagase, S. I. Ohkawa, M. Aoki, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan DOI: 10.1109/ICMTS.2004.1309491 HOVER FOR ABSTRACT | PDF Xplore | |
| On-chip di/dt detector circuit for power supply line T. Nakura, M. Ikeda, K. Asada Department of Electronic Engineering, University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2004.1309294 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for fixing OPC of 200 nm pitch via chain using inner and outer dummy via array T. Nasuno, Y. Matsubara, A. Minami, N. Uchida, H. Kobayashi, H. Aoyama, H. Tsuda, K. Tsujita, W. Wakamiya, N. Kobayashi Research Department2, Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2004.1309295 HOVER FOR ABSTRACT | PDF Xplore | |
| New test structure for high resolution leakage current and capacitance measurements in CMOS imager applications F. Odiot, H. Brut, J. Hurwitz1, L. Grant1, B. Dunne2, J. M. Moragues2 Central R&D, STMicroelectronics, Crolles, France 1Imaging Division, STMicroelectronics, Edinburgh, UK 2STMicroelectronics, Rousset, France DOI: 10.1109/ICMTS.2004.1309490 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization & modeling of low electric field gate-induced-drain-leakage [MOSFET] D. Rideau, A. Dray, F. Gilibert, F. Agut, L. Giguerre1, G. Gouget, M. Minondo, A. Juge STMicroelectronics, Central R&D, Device Modeling, Crolles, France 1Philips, Central R&D, Device Modeling, Crolles, France DOI: 10.1109/ICMTS.2004.1309469 HOVER FOR ABSTRACT | PDF Xplore | |
| From analog to RF design [review] W. Sansen ESAT-MICAS, Katholieke Universiteit Leuven, Leuven, Belgium DOI: 10.1109/ICMTS.2004.1309298 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability S. Saxena, S. Minehane, J. Cheng, M. Sengupta, C. Hess, M. Quarantelli, G. M. Kramer, M. Redford PDF Solutions, Inc.orporated, Richardson, TX, USA DOI: 10.1109/ICMTS.2004.1309492 HOVER FOR ABSTRACT | PDF Xplore | |
| Leakage current correction in quasi-static C-V measurements J. Schmitz, M. H. H. Weusthof, A. J. Hof MESA Research Institute, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS.2004.1309475 HOVER FOR ABSTRACT | PDF Xplore | |
| A new analytical inductance extraction technique of on-wafer spiral inductors H. Shima, T. Matsuoka, K. Taniguchi Department of Electronics and Information Systems, Osaka University, Suita, Osaka, Japan DOI: 10.1109/ICMTS.2004.1309495 HOVER FOR ABSTRACT | PDF Xplore | |
| An accurate measurement and extraction method of gate to substrate overlap capacitance [MOSFETs] M. Shimasue, Y. Kawahara, T. Sano, H. Aoki MODECH, Inc., Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.2004.1309498 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel RFCMOS process monitoring test structure C. B. Sia, B. H. Ong1, K. M. Lim, K. S. Yeo1, M. A. Do1, J. G. Ma1, T. Alam2 Advanced RFIC (S) Private Limited, Singapore 1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 2Cascade Microtech, Inc., OR, USA DOI: 10.1109/ICMTS.2004.1309299 HOVER FOR ABSTRACT | PDF Xplore | |
| An accurate and scalable differential inductor design kit [RFIC applications] C. B. Sia, K. W. Chan, C. Q. Geng, W. Yang, K. S. Yeo1, M. A. Do1, J. G. Ma1, S. Chu2, K. W. Chew2 Advanced RFIC (S) Private Limited, Singapore 1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 2Chartered Semiconductor Manufacturing Private Limited, Singapore DOI: 10.1109/ICMTS.2004.1309303 HOVER FOR ABSTRACT | PDF Xplore | |
| Varactor modeling methodology for simulation of the VCO tuning sensitivity D. Siprak, A. Roithrneier1 Infineon Technologies AG, CL TD SIM PXI, Munich, Germany 1NA DOI: 10.1109/ICMTS.2004.1309494 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for CD and overlay metrology on alternating aperture phase-shifting masks S. Smith, M. McCallum1, A. J. Walton, J. T. M. Stevenson, P. D. Harris1, A. W. S. Ross, A. C. Hourd2, L. Jiang School of Engineering and Electronics, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1Nikon Precision Europe, West Lothian, UK 2Compugraphics International Limited, Glenrothes, Fife, UK DOI: 10.1109/ICMTS.2004.1309296 HOVER FOR ABSTRACT | PDF Xplore | |
| Error evaluation of C-V characteristic measurements in ultra-thin gate dielectrics H. Suto, S. Inaba, K. Ishimaru SoC Research & Development Center, Toshiba Corporation Semiconductor Company, Yokohama, Kanagawa, Japan DOI: 10.1109/ICMTS.2004.1309483 HOVER FOR ABSTRACT | PDF Xplore | |
| New device structure for 18-V, high-performance SOI complementary bipolar LSIs using array transistors and flexible U-grooves Y. Tamaki, K. Tsuji1, O. Ohtani2, H. Nonami, T. Tomatsuri, E. Yoshida, M. Hamamoto, N. Nakazato3 Device Development Center, Hitachi Ltd., Tokyo, Japan 1Hitachi ULSI Systems Company Limited, Ome, Tokyo, Japan 2Renesas Eastern Japan Semiconductor, Inc., Takasaki, Gunma, Japan 3Mechanical Engineering Research Laboratory, Hitachi Ltd., Tsuchiura, Ibaraki, Japan DOI: 10.1109/ICMTS.2004.1309468 HOVER FOR ABSTRACT | PDF Xplore | |
| Further study of VTH-mismatch evaluation circuit K. Terada, K. Fukeda Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan DOI: 10.1109/ICMTS.2004.1309470 HOVER FOR ABSTRACT | PDF Xplore | |
 | Test chip for the development and evaluation of test structures for measuring stress in metal interconnect J. G. Terry, S. Smith, A. J. Walton, A. M. Gundlach, J. T. M. Stevenson, A. B. Horsfall1, K. Wang1, J. M. M. dos Santos1, S. M. Soare2, N. G. Wright1, A. G. O'Neill1, S. J. Bull2 Institute for Integrated Micro and Nano Systems, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1School of Electrical, Electronic and Computer Engineering, University of Newcastle, Newcastle, UK 2School of Chemical Engineering and Advanced Materials, University of Newcastle, Newcastle, UK DOI: 10.1109/ICMTS.2004.1309304 HOVER FOR ABSTRACT | PDF Xplore |
| Measuring the span of stress asymmetries on high-precision matched devices H. P. Tuinhout, A. Bretveld1, W. C. M. Peters2 Philips Research, Eindhoven, Netherlands 1Philip Consumer Electronics IC-Laboratory, Eindhoven, Netherlands 2Philips Semiconductors, Nijmegen, Netherlands DOI: 10.1109/ICMTS.2004.1309463 HOVER FOR ABSTRACT | PDF Xplore | |
| Direct extraction methodology for geometry-scalable RF-CMOS models S. P. Voinigescu, M. Tazlauanu1, P. C. Ho2, M. T. Yang2 ECE Department, University of Toronto, Toronto, ONT, Canada 1Quake Technologies, Inc., Ottawa, ONT, Canada 2Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309486 HOVER FOR ABSTRACT | PDF Xplore | |
| Development of a 90 nm large-scale TEG for evaluation and analysis of signal integrity, yield and variation M. Yamamoto, Y. Hayasi1, H. Endo1, H. Masuda Semiconductor Technology Academic Research Center (STARC), Kouhoku-ku, Yokohama, Japan 1Hitachi ULSI Systems Co., Ltd, Tokyo, Japan DOI: 10.1109/ICMTS.2004.1309309 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization and model of 4-terminal RF CMOS with bulk effect M. T. Yang, Y. J. Wang, T. J. Yeh, P. P. C. Ho, Y. T. Chia, K. L. Young Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309477 HOVER FOR ABSTRACT | PDF Xplore | |
| Transistor test structures for leakage current analysis of partial SOI Kyoung Hwan Yeo, Chang Woo Oh, Sung-Min Kim, Min-Sang Kim, Sung-Young Lee, Ming Li, Hye-Jin Cho, Eun-Jung Yoon, Sung-Hwan Kim, Jeong-Dong Choe, Dong-Won Kim, Donggun Park, Kinam Kim Advanced Technology Development Team, R&D Center, Samsung Electronics Company Limited, Yongin si, Gyeonggi, South Korea DOI: 10.1109/ICMTS.2004.1309488 HOVER FOR ABSTRACT | PDF Xplore |
