IEEE International Conference on Microelectronic Test Structures
ICMTS 2003 Program
2003 Program Booklet
By First Author
| Junction-isolated electrical test structures for critical dimension calibration standards R. A. Allen, M. W. Cresswell, L. W. Linholm Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2003.1197360 HOVER FOR ABSTRACT | PDF Xplore | |
| Measuring the effects of process variations on circuit performance by means of digitally-controllable ring oscillators A. Bassi, A. Veggetti1, L. Croce1, A. Bogliolo2 DI-University of Ferrara, Ferrara, Italy 1STMicroelectronics, Agrate-Brianza, Milan, Italy 2STI-Universita di Urbino, Urbino, Italy DOI: 10.1109/ICMTS.2003.1197464 HOVER FOR ABSTRACT | PDF Xplore | |
| A hybrid table/analytical approach to MOSFET modelling V. Bourenkov, K. G. McCarthy1, A. Mathewson National Microelectronics Research Centre, University College Cork, Ireland 1Department of Electrical and Electronic Engineering, University College Cork, Ireland DOI: 10.1109/ICMTS.2003.1197435 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation of mechanical properties by electrostatic loading of polycrystalline silicon beams R. Cambie, F. Carli1, C. Combi2 Department of Electrical Engineering, University of Pavia, Italy 1Department of Structural Mechanics, University of Pavia, Italy 2MEMS Development Unit, STMicroelectronics, Milan, Italy DOI: 10.1109/ICMTS.2003.1197368 HOVER FOR ABSTRACT | PDF Xplore | |
| Fast and precise subthreshold slope method for extracting gate capacitive coupling coefficient in flash memory cells Caleb Yu-Sheng Cho, Ming-Jer Chen, Chiou-Feng Chen1 Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan 1Actran Systems, Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS.2003.1197459 HOVER FOR ABSTRACT | PDF Xplore | |
| Automatic, wafer-level, low frequency noise measurements for the interface slow trap density evaluation J. A. Chroboczek Commissariat à ľEnergie Atomique, Lahoratoire dElectronique et de la Technologie pour ľlnfomatlque, CEA-DRT-LETI, Grenoble, France DOI: 10.1109/ICMTS.2003.1197409 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures and test methodology for developing high voltage ESD protection A. Concannon, V. Vashchenko, M. ter Beek, P. Hopper National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2003.1197456 HOVER FOR ABSTRACT | PDF Xplore | |
| Influence of masking layer stress on anisotropic silicon etching in TMAH solutions M. Decarli, V. Guarnieri1, R. Pal, F. Giacomozzi1, B. Margesin1, M. Zen1 Dept. of Information and Communication Technology, University of Trento, Trento, Italy 1ITC-IRST, Povo, Trento, Italy DOI: 10.1109/ICMTS.2003.1197364 HOVER FOR ABSTRACT | PDF Xplore | |
| Use of test structures for characterising a novel photosensitive organometallic material for MOS processes M. H. Dicks, G. M. Broxton1, J. Thomson2, J. Lobban2, J. T. Stevenson, A. J. Walton Scottish Microelectronics Centre, School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK 1Department of Applied Physics and Electronic & Mechanical Engineering, University of Dundee, Dundee, UK 2Division of Physical and Inorganic Chemistry, University of Dundee, Dundee, UK DOI: 10.1109/ICMTS.2003.1197362 HOVER FOR ABSTRACT | PDF Xplore | |
| Impact of grain number fluctuations in the MOS transistor gate on matching performance R. Difrenza, J. C. Vildeuil, P. Llinares, G. Ghibaudo1 STMicroelectronics, Crolles, France 1IMEP, Grenoble, France DOI: 10.1109/ICMTS.2003.1197469 HOVER FOR ABSTRACT | PDF Xplore | |
| Design and integration of electrical-based dimensional process-window checking infrastructure K. Y. Y. Doong, R. C. J. Wang, J. C. H. Huang1, S. C. Lin, L. J. Hung, S. Z. Lee, K. L. Young Taiwan Semiconductor Manufacturing Corporation, Hsinchu, Taiwan 1Silicon Canvas, Inc., San Jose, USA DOI: 10.1109/ICMTS.2003.1197423 HOVER FOR ABSTRACT | PDF Xplore | |
| Thermal design considerations for Greek cross test structures S. Enderling, M. H. Dicks, S. Smith, J. T. M. Stevenson, A. J. Walton School of Engineering and Electronics, The University of Edinburgh, Edinburgh, U.K. DOI: 10.1109/ICMTS.2003.1197361 HOVER FOR ABSTRACT | PDF Xplore | |
| Process stress estimation for MEMS RF switches with capacitive test structures L. Ferrario, C. Armaroli, B. Margesin, M. Zen, G. Soncini Microsystems Division, ITC IRST, Trento, Italy DOI: 10.1109/ICMTS.2003.1197369 HOVER FOR ABSTRACT | PDF Xplore | |
| Application of the TRM self-calibration on standard silicon substrates R. Gillon, W. Tatinian, B. Landat1 AMI Semiconductors, Inc., Oudenaarde, Belgium 1AMI Semicond. bvba, Oudenaarde, Belgium DOI: 10.1109/ICMTS.2003.1197425 HOVER FOR ABSTRACT | PDF Xplore | |
| An advanced defect-monitoring test structure for electrical measurements and defect localization Y. Hamamura, T. Kumazawa, K. Tsunokuni1, A. Sugimoto2, H. Asakura2 Production Engineering Research Laboratory, Hitachi and Limited, Yokohama, Japan 1Semiconductor & Integrated Circuits, Hitachi and Limited, Tokyo, Japan 2Device Development Center, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.2003.1197372 HOVER FOR ABSTRACT | PDF Xplore | |
| Test time reduction methods for yield test structures C. Hess, H. Read, J. Ren, L. H. Weiland, Jianjun Cheng1, Chock Gan1, H. Karbasi1, S. Winters1 PDF Solutions, Inc.orporated, San Jose, CA, USA 1PDF Solutions, Inc.orporated, San Diego, CA, USA DOI: 10.1109/ICMTS.2003.1197384 HOVER FOR ABSTRACT | PDF Xplore | |
| Scalable ground-shielded open fixture applied to de-embedding techniques T. Kaija, E. Ristolainen Institute of Electronics, Tampere University of Technology, Tampere, Finland DOI: 10.1109/ICMTS.2003.1197406 HOVER FOR ABSTRACT | PDF Xplore | |
| Optimisation of integrated RF varactors on a 0.35 µm BiCMOS technology S. C. Kelly, J. A. Power, M. O'Neill Analog Devices, Inc., Limerick, Ireland DOI: 10.1109/ICMTS.2003.1197426 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's Ming-Dou Ker, Jeng-Jie Peng1, Hsin-Chin Jiang1 Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Taiwan 1ESD Protection Technology Department, SoC Technology Center, Industrial Technology and Research Institute, Taiwan DOI: 10.1109/ICMTS.2003.1197455 HOVER FOR ABSTRACT | PDF Xplore | |
| Substrate resistance modeling for noise coupling analysis S. Kristiansson, S. P. Kagganti1, T. Ewert2, F. Ingvarson, J. Olsson2, K. O. Jeppson Solid State Elcctronics Laboratory, Department of Microelectronics, Chalmers University of Technology, Gothenburg, Sweden 1Solid State Electronics Laboratory, Department of Microelectronics, Chalmers University of Technology, Gothenburg, Sweden 2ängström Laboratory, Solid State Electronics, University of Uppsala, Uppsala, Sweden DOI: 10.1109/ICMTS.2003.1197429 HOVER FOR ABSTRACT | PDF Xplore | |
| Reliable extraction of interface states from charge pumping method in ultra-thin gate oxide MOSFETs H. C. Lai, N. K. Zous, W. J. Tsai, T. C. Lu, Tahui Wang1, Y. C. King, Sam Pan Advance Device Engineering Department Si-Laboratory, Macronix International Company Limited, Hsinchu, Taiwan 1Institute of Electronics Engineering, National Tsing Hua University, Taiwan DOI: 10.1109/ICMTS.2003.1197421 HOVER FOR ABSTRACT | PDF Xplore | |
| Improvement of poly emitter n-p-n transistor matching in a 0.6 micron mixed signal technology G. Lau, W. Einbrodt, W. Sieber X-FAB Semiconductor Foundries AG, Erfurt, Germany DOI: 10.1109/ICMTS.2003.1197467 HOVER FOR ABSTRACT | PDF Xplore | |
| A new technique to extract intrinsic and extrinsic base-collector capacitances of bipolar transistors using Y-parameter equations Seonghearn Lee Department of Electronic Engineering, Hankuk University of Foreign Studies, Yongin si, Gyeonggi, South Korea DOI: 10.1109/ICMTS.2003.1197431 HOVER FOR ABSTRACT | PDF Xplore | |
 | An integrated test chip for the complete characterization and monitoring of a 0.25µm CMOS technology that fits into five scribe line structures 150µm by 5000µm R. Lefferts, C. Jakubiec Accelerant Networks, Inc., Beaverton, OR, USA DOI: 10.1109/ICMTS.2003.1197382 HOVER FOR ABSTRACT | PDF Xplore |
| A combined test structure with ring oscillator and inverter chain for evaluating optimum high-speed/low-power operation T. Matsuda, H. Iwata, T. Ohzone1, K. Yamashita2, N. Koike2, K. Tatsuuma2 Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan 1Faculty of Computer Science and System Engineering, Okayama Prefectural University, Soja, Okayama, Japan 2WLSI Process Technology Development Center, Semiconductor Company, Matsushita Elecrric Indusrrial Company Limited, Minami, Kyoto, Japan DOI: 10.1109/ICMTS.2003.1197390 HOVER FOR ABSTRACT | PDF Xplore | |
| Polysilicon resistive heated scribe lane test structure for productive wafer level reliability monitoring of NBTI W. Muth, A. Martin, J. von Hagen, D. Smeets, J. Fazekas Infineon Technologies, Munich, Germany DOI: 10.1109/ICMTS.2003.1197440 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for quantum efficiency characterization for silicon image sensors F. Odiot, J. Bonnouvrier, C. Augier, J. M. Raynor1 ST Microelectronics, Central Research and Development Laboratory, Crolles, France 1Imaging Division, STMicroelectronics, Edinburgh, UK DOI: 10.1109/ICMTS.2003.1197366 HOVER FOR ABSTRACT | PDF Xplore | |
| Analysis and characterization of device variations in an LSI chip using an integrated device matrix array S. Ohkawa, M. Aoki, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan DOI: 10.1109/ICMTS.2003.1197386 HOVER FOR ABSTRACT | PDF Xplore | |
| The negative capacitance effect on the C-V measurement of ultra thin gate dielectrics induced by the stray capacitance of the measurement system Y. Okawa, H. Norimatsu, H. Suto1, M. Takayanagi1 Hachioji Semiconductor Parametric Test Division, Agilent Technology International, Hachioji, Tokyo, Japan 1SoC Research and Development Center, Semiconductor Company, Toshiba Corporation, Japan DOI: 10.1109/ICMTS.2003.1197461 HOVER FOR ABSTRACT | PDF Xplore | |
| Impact of gate current on first order parameter extraction in sub-0.1 µm CMOS technologies N. Planes, A. Dray, E. Robilliart, H. Brut Central Research and Development, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2003.1197433 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization and modeling of MOSFET mismatch of a deep submicron technology M. Quarantelli, S. Saxena, N. Dragone, J. A. Babcock, C. Hess, S. Minehane, S. Winters, Jianjun Chen, H. Karbasi, C. Guardiani PDF Solutions, Inc.orporated, San Jose, CA, USA DOI: 10.1109/ICMTS.2003.1197468 HOVER FOR ABSTRACT | PDF Xplore | |
| Series resistance estimation and C(V) measurements on ultra thin oxide MOS capacitors D. Rideau, P. Scheer, D. Roy, G. Gouget, M. Minondo, A. Juge STMicroelectronics, Central Research and Development, Device Modeling, Crolles, France DOI: 10.1109/ICMTS.2003.1197460 HOVER FOR ABSTRACT | PDF Xplore | |
| An electrical monitor of deep trench depth T. Roggenbauer, V. Khemka, V. Parthasarathy, I. Puchades, R. Zhu Motorola SPS, Chandler, AZ, USA DOI: 10.1109/ICMTS.2003.1197363 HOVER FOR ABSTRACT | PDF Xplore | |
| BSIM3 RF models for MOS transistors: a novel technique for substrate network extraction S. C. Rustagi, Huailin Liao, Jinglin Shi, Yong Zhong Xiong Institute of Microelectronics, Singapore DOI: 10.1109/ICMTS.2003.1197427 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure design considerations for RF-CV measurements on leaky dielectrics J. Schmitz, F. N. Cubaynes1, R. J. Havens2, R. de Kort2, A. J. Scholten2, L. F. Tiemeijer2 Philips Research Leuven, University of Twente, Netherlands 1Philips Research Leuven, Leuven, Belgium 2Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2003.1197458 HOVER FOR ABSTRACT | PDF Xplore | |
| Study on STI mechanical stress induced variations on advanced CMOSFETs Y. M. Sheu, K. Y. Y. Doong1, C. H. Lee1, M. J. Chen, C. H. Diaz1 Department of Electronics Engineering, SBIP, National Chiao Tung University, Hsinchu, Taiwan 1Taiwan Semiconductor Manufacturing Company Limited, Taiwan DOI: 10.1109/ICMTS.2003.1197462 HOVER FOR ABSTRACT | PDF Xplore | |
| An improved SPICE model for ferroelectric liquid crystal microdisplays S. Smith, A. J. Walton, I. Underwood, C. Miremont, D. G. Vass1, W. J. Hossack1, M. Birch2, A. Maartney3, R. Nicol4 School of Engineering and Electronics, The University of Edinburgh, Edinburgh, U.K 1Department of Physics and Astronomy, The University of Edinburgh, Edinburgh, U.K 2CRL Opto Ltd., Dalgety Bay, Dunfermline, U.K 3NA 4MicroVue Limited, Dalgety Bay, Dunfermline, U.K DOI: 10.1109/ICMTS.2003.1197438 HOVER FOR ABSTRACT | PDF Xplore | |
| A test circuit for measuring MOSFET threshold voltage mismatch K. Terada, M. Eimitsu Faculty of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan DOI: 10.1109/ICMTS.2003.1197466 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation of mobility in the MOSFET with high leakage current O. Tonomura, Y. Shimamoto, K. Torii, M. Hiratani, S. Saito, J. Yugami Central Research Laboratory Hitachi, Ltd., Tokyo, Japan DOI: 10.1109/ICMTS.2003.1197407 HOVER FOR ABSTRACT | PDF Xplore | |
| Current mirror test structures for studying adjacent layout effects on systematic transistor mismatch H. P. Tuinhout, A. Bretveld1, W. C. M. Peters2 Philips Research, Eindhoven, Netherlands 1Philips Consumer Electronics IC-Laboratories, Eindhoven, Netherlands 2Philips Semiconductors, Nijmegen, Netherlands DOI: 10.1109/ICMTS.2003.1197465 HOVER FOR ABSTRACT | PDF Xplore | |
| New evaluation method for reliability of poly-Si thin film transistors using pico-second time-resolved emission microscope Y. Uraoka, N. Hirai1, H. Yano, T. Hatayama, T. Fuyuki Materials Science, Nara Institute of Science and Technology, Ikoma, Nara, Japan 1Hamamatst Photonics, Ikoma, Nara, Japan DOI: 10.1109/ICMTS.2003.1197457 HOVER FOR ABSTRACT | PDF Xplore | |
| Development of a large-scale TEG for evaluation and analysis of yield and variation M. Yamamoto, H. Endo1, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan 1Hitachi ULSI Systems Company Limited, Tokyo, Japan DOI: 10.1109/ICMTS.2003.1197376 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for analyzing the mechanisms of wafer chemical contaminant removal J. Yan, H. J. Barnaby1, B. Vermiere2, T. Peterson, F. Shadman Chemical & Environmental Engineering, University of Arizona Tucson, Tucson, AZ, USA 1Electrical & Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA 2Ridgetop Group, Inc., Tucson, AZ, USA DOI: 10.1109/ICMTS.2003.1197463 HOVER FOR ABSTRACT | PDF Xplore |
