IEEE International Conference on Microelectronic Test Structures
ICMTS 2001 Program
2001 Program Booklet
By First Author
| Channel width and length dependent flicker noise characterization for n-MOSFETs H. Aoki, M. Shimasue Design Technology Group, Knowledge Seervice, Agilent Technologies International Japan Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.2001.928672 HOVER FOR ABSTRACT | PDF Xplore | |
| Test chips for evaluating strong phase shift lithography R. A. Ashton, B. C. Kane1, J. W. Blatchford, D. M. Shuttleworth Agere Systems, Orlando, FL, USA 1Multilink Technology, Somerset, NJ, USA DOI: 10.1109/ICMTS.2001.928654 HOVER FOR ABSTRACT | PDF Xplore | |
| A new robust on-wafer 1/f noise measurement and characterization system A. Blaum, O. Pilloud, G. Scalea, J. Victory, F. Sischka1 Motorola, Inc., Geneva, Switzerland 1Agilent Technologies, Inc., Boblingen, Germany DOI: 10.1109/ICMTS.2001.928650 HOVER FOR ABSTRACT | PDF Xplore | |
| A general procedure for high-frequency noise parameter de-embedding of MOSFETs by taking the capacitive effects of metal interconnections into account Chih-Hung Chen, M. J. Deen Department of Electrical and Computer Engineering, McMaster University, Hamilton, ONT, Canada DOI: 10.1109/ICMTS.2001.928647 HOVER FOR ABSTRACT | PDF Xplore | |
| Extraction of the induced gate noise, channel thermal noise and their correlation in sub-micron MOSFETs from RF noise measurements Chih-Hung Chen, M. J. Deen, M. Matloubian1, Yuhua Cheng1 Department of Electrical and Computer Engineering, McMaster University, Hamilton, ONT, Canada 1Conexant Systems, Inc., Newport Beach, CA, USA DOI: 10.1109/ICMTS.2001.928651 HOVER FOR ABSTRACT | PDF Xplore | |
| Die cracking evaluation and improvement in ULSI plastic package Kuo-Yu Chou, Ming-Jer Chen, Chiu-Cheng Lin1, Yen-Shien Su1, Chin-Shan Hou1, Tong-Cherng Ong1 Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan 1Technology Reliability Physics Department R&D, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2001.928669 HOVER FOR ABSTRACT | PDF Xplore | |
| Test chip for electrical linewidth of copper-interconnect features and related parameters M. W. Cresswell, N. Arora1, R. A. Allen, C. E. Murabito, C. A. Richter, A. Gupta2, L. W. Linholm, D. Pachura3, P. Bendix3 Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Simplex Solution, Inc., Sunnyvale, CA, USA 2Chartered Semiconductor Manufacturing Private Limited, Milpitas, CA, USA 3LSI Logic, Inc., Milpitas, CA, USA DOI: 10.1109/ICMTS.2001.928659 HOVER FOR ABSTRACT | PDF Xplore | |
| A simple characterization method for MOS transistor matching in deep submicron technologies J. A. Croon, M. Rosmeulen, S. Decoutere, W. Sansen1, H. E. Maes IMEC vzw, Leuven, Belgium 1K.U. Leuven, ESAT, Leuven, Belgium DOI: 10.1109/ICMTS.2001.928664 HOVER FOR ABSTRACT | PDF Xplore | |
| Effect of substrate voltage and oxide thickness on NMOSFET matching characteristics for a 0.18 µm CMOS technology R. Difrenza, P. Llinares, E. Granger, H. Brut, G. Ghibaudo1 STMicroelectronics, Crolles, France 1LPCS-ENSERG, Grenoble, France DOI: 10.1109/ICMTS.2001.928628 HOVER FOR ABSTRACT | PDF Xplore | |
| A new method for measuring the coupling coefficient of a split-gate flash EEPROM without an additional test structure H. Fujiwara, M. Arimoto, T. Kaida, S. Sudo, K. Kurooka, H. Nagasawa, T. Hiroshima, K. Mameno Microelectronics Research Center, SANYO Electric Company Limited, Gifu, Japan DOI: 10.1109/ICMTS.2001.928635 HOVER FOR ABSTRACT | PDF Xplore | |
 | A new test structure to measure precise location of hot-carrier-induced photoemission peak from gate center of subquarter-micron n-MOSFETs M. Funada, T. Matsuda, T. Ohzone, S. Odanaka1, K. Yamashita2, N. Koike2, K. Tatsumma3 Department of Electronics and Informatics, Toyama Prefectural University, Imizu-gun, Toyama, Japan 1Cybermedia Center, Osaka University, Toyonaka, Osaka, Japan 2ULSI Process Technology Development Center, Matsushita Electronics Corp., Minami-ku, Kyoto, Japan 3NA DOI: 10.1109/ICMTS.2001.928666 HOVER FOR ABSTRACT | PDF Xplore |
| Use of electrical test structures to characterize trench profiles etched on SOI wafers N. Guillaume, J. Kiihamaki1, J. Karttunen1, H. Kattelus1 Guest Researcher at NIST, George Washington University, Washington D.C., DC, USA 1VTT Electronics, Finland DOI: 10.1109/ICMTS.2001.928655 HOVER FOR ABSTRACT | PDF Xplore | |
| A new Leff extraction approach for devices with pocket implants T. S. Hsieh, Y. W. Chang, W. J. Tsai, T. C. Lu Special Device & Modeling Department, Macronix International Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2001.928630 HOVER FOR ABSTRACT | PDF Xplore | |
| Effective-channel-length extraction for double-diffused MOSFETs S. Ichikawa, Y. Eshima, K. Terada, T. Matsuki1 Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan 1ULSI Device Development Division, NEC Corporation Limited, Japan DOI: 10.1109/ICMTS.2001.928644 HOVER FOR ABSTRACT | PDF Xplore | |
| A procedure for characterizing the BJT base resistance and Early voltages utilizing a dual base transistor test structure F. Ingvarson, M. Linder1, K. O. Jeppson, Shi-Li Zhang1, J. V. Grahn1, M. Ostling1 Solid State Electronics Laboratory, Department of Microelectronics ED, Chalmers University of Technology, Gothenburg, Sweden 1DeviceTechnology Laboratory, Department of Electronics, Royal Institute of Technology, Kista, Sweden DOI: 10.1109/ICMTS.2001.928633 HOVER FOR ABSTRACT | PDF Xplore | |
| Process monitoring and defect characterization of single photon avalanche diodes J. C. Jackson, A. P. Morrison1, P. Hurley, W. R. Harrell2, D. Damjanovic2, B. Lane, A. Mathewson National Microelectronics Research Centre, University College Cork, Ireland 1Department of Electrical and Electronic Engineering, University College Cork, Ireland 2Department of Electrical and Computer Engineering, Clemson University, South Carolina, U.S.A. DOI: 10.1109/ICMTS.2001.928656 HOVER FOR ABSTRACT | PDF Xplore | |
| C-V extraction method for gate fringe capacitance and gate to source-drain overlap length of LDD MOSFET Jae-Rok Kahng, Jang-Won Moon, Jin-Hyoung Kim Memory R&D Division, Hyundai Electronics Industries Company Limited, Incheon, Gyeonggi, South Korea DOI: 10.1109/ICMTS.2001.928638 HOVER FOR ABSTRACT | PDF Xplore | |
| Contact resistance measurement of a 130-nm-diameter poly-Si plug on a lightly doped single diffusion region in giga-bit DRAMs N. Kasai, H. Koga, Y. Takaishi ULSI Device Development Division, NEC Electron Devices, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.2001.928658 HOVER FOR ABSTRACT | PDF Xplore | |
| Resistor matching characterization for process development using D/A converter S. Katakam, B. Tranchina, J. Bordelon, A. Ramaswamy1, Wooyoung Choi2, S. Chu3 TestChip Technologies, Inc., Dallas, USA 1Sun Microsystems, Inc., USA 2University of Minnesota, USA 3Chartered Semiconductor, Inc., Singapore DOI: 10.1109/ICMTS.2001.928665 HOVER FOR ABSTRACT | PDF Xplore | |
| FeRAM retention analysis method based on memory cell read signal voltage measurement H. Koike, K. Amanuma1, T. Miwa, J. Yamada, H. Toyoshima2 Silicon Systems Research Laboratories, System Devices and Fundamental Research, NEC Corporation Limited, Sagamihara, Kanagawa, Japan 1Second System LSI Division, NEC Electron Devices, Sagamihara, Kanagawa, Japan 2ULSI Device Development Division, NEC Electron Devices, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.2001.928634 HOVER FOR ABSTRACT | PDF Xplore | |
| High frequency MOS transistor matching measurements for the determination of mixer port crosstalk S. Laursen University of Aalborg, Aalborg, Denmark DOI: 10.1109/ICMTS.2001.928629 HOVER FOR ABSTRACT | PDF Xplore | |
| An improved transmission line pulsing (TLP) setup for electrostatic discharge (ESD) testing in semiconductor devices and ICs J. C. Lee, R. Young1, J. J. Liou2, G. D. Croft1, J. C. Bernier3 RF Analog SiGe BiCMOS Device Modeling Group, IBM, Burlington, VT, USA 1Technology Development Department, Intersil Corporation, Melbourne, FL, USA 2School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL, USA 3Reliability Engineering Department, Intersil Corporation, Melbourne, FL, USA DOI: 10.1109/ICMTS.2001.928668 HOVER FOR ABSTRACT | PDF Xplore | |
| Efficient parameter extraction techniques for a new surface-potential-based MOS model for RF applications Wenzhi Liang, R. Van Langevelde1, K. G. McCarthy2, A. Mathewson National Microelectronics Research Centre, Cork, Ireland 1Philips Research Laboratories, Eindhoven, Netherlands 2Department of Electrical and Electronics Engineering, University College Cork, Ireland DOI: 10.1109/ICMTS.2001.928652 HOVER FOR ABSTRACT | PDF Xplore | |
| A new test structure for parasitic resistance extraction in bipolar transistors M. Linder, F. Ingvarson1, K. O. Jeppson1, Shi-Li Zhang, J. V. Grahn, M. Ostling Device Technology Laboratory, Department of Electronics, Royal Institute of Technology, Kista, Sweden 1Solid State Electronics Laboratory Department of Microelectronics ED, Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS.2001.928632 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel approach to the estimation of confidence limits for BJT model sets using a bootstrap technique D. MacSweeney, K. G. McCarthy1, L. Floyd, M. Riordan, L. Sattler, A. Mathewson, J. A. Power2, S. C. Kelly2 National Microelectronics Research Centre, University College Cork, Ireland 1Department of Electrical and Electronic Engineering, University College Cork, Ireland 2Analog Devices, Inc., Limerick, Ireland DOI: 10.1109/ICMTS.2001.928636 HOVER FOR ABSTRACT | PDF Xplore | |
| Comparison of interface trap density measured by capacitance/subthreshold/charge-pumping methods for n-MOSFETs with Si-implanted gate-SiO2 T. Matsuda, R. Takezawa, K. Arakawa, M. Yasuda, T. Ohzone, E. Kameda1 Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan 1Department of Electrical Engineering, Toyama National College of Maritime Technology, Toyama, Japan DOI: 10.1109/ICMTS.2001.928639 HOVER FOR ABSTRACT | PDF Xplore | |
| Oxide thickness dependence of nitridation effects on TDDB characteristics M. K. Mazumder, A. Teramoto, J. Komori, Y. Mashiko ULSI Laboratory, Musubishi Electric Corporation, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.2001.928646 HOVER FOR ABSTRACT | PDF Xplore | |
| New length scaling of current gain factor and characterization method for pocket implanted MOSFET's M. Minondo, G. Gouget, A. Juge Central R&D, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2001.928673 HOVER FOR ABSTRACT | PDF Xplore | |
| Limitations of the two-frequency capacitance measurement technique applied to ultra-thin SiO2 gate oxides A. Nara, N. Yasuda, H. Satake, A. Toriumi1 Advanced LSI Technology Laboratory Corporate Research & Development Center, Toshiba Corporation, Yokohama, Japan 1University of Tokyo, Japan DOI: 10.1109/ICMTS.2001.928637 HOVER FOR ABSTRACT | PDF Xplore | |
| Effects of electrical stress on the frequency performance of 0.18 µm technology NMOSFETs S. Naseh, M. J. Deen, O. Marinov Electrical and Computer Engineering Department, McMaster University, Hamilton, ONT, Canada DOI: 10.1109/ICMTS.2001.928649 HOVER FOR ABSTRACT | PDF Xplore | |
| Statistical SPICE analysis of a 0.18 µm CMOS digital/analog technology during process development N. S. Rankin, Chun Ng1, Leang Sern Ee1, F. Boyland1, E. Quek1, Leung Ying Keung1, A. J. Walton, M. Redford1 Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1Chartered Semiconductor Manufacturing Private Limited, Singapore DOI: 10.1109/ICMTS.2001.928631 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation of the impact of mechanical stress on CMOS device mismatch U. Schaper, C. Linnenbank, U. Kollmer, H. Mulatz, T. Mensing, R. Schmidt1, R. Tilgner1, A. R. Thewes2 Infineon Technologies AG, Munich, Germany 1Corp. Frontend, Corp. Backend, Munich, Germany 2Corp. Research, Munich, Germany DOI: 10.1109/ICMTS.2001.928627 HOVER FOR ABSTRACT | PDF Xplore | |
| A new approach to characterize substrate losses of on-chip inductors L. Schimpf, B. Benna, D. Proetel Texas Instruments Deutschland GmbH, Freising, Germany DOI: 10.1109/ICMTS.2001.928648 HOVER FOR ABSTRACT | PDF Xplore | |
| A study of measurement system noise for sensitive soft breakdown triggering J. Schmitz, H. P. Tuinhout Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2001.928645 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation of the issues involved with test structures for the measurement of sheet resistance and linewidth of copper damascene interconnect S. Smith, A. J. Walton, A. W. S. Ross, G. K. H. Bodammer, J. T. M. Stevenson Department of Electronics and Electrical Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2001.928661 HOVER FOR ABSTRACT | PDF Xplore | |
| A new method for analyzing boron penetration and gate depletion using dual-gate PMOSFETs for high performance G-bit DRAM design N. Takaura, R. Nagai1, H. Asakura2, S. Yamada1, S. Kimura Central Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan 1ELPIDA Memory, Inc., Sagamihara, Kanagawa, Japan 2Device Development Center, Hitachi and Limited, Ome, Tokyo, Japan DOI: 10.1109/ICMTS.2001.928657 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation of high-performance SOI complementary BiCMOS devices by using test structures Y. Tamaki, T. Iwasaki1, K. Tsuji2, Y. Chida2, T. Tomatsuri, E. Yoshida, J. Kumazawa, C. Kamada Device Development Center, Hitachi and Limited, Ome, Tokyo, Japan 1Hitachi Research Laboratory, Hitachi and Limited, Hitachi, Ibaraki, Japan 2Hitachi VLSI Engineering Corporation Limited, Ome, Tokyo, Japan DOI: 10.1109/ICMTS.2001.928670 HOVER FOR ABSTRACT | PDF Xplore | |
| Statistical modeling techniques: FPV vs. BPV N. Telang, J. M. Higman Semiconductor Products Sector, Motorola, Inc., Austin, TX, USA DOI: 10.1109/ICMTS.2001.928640 HOVER FOR ABSTRACT | PDF Xplore | |
| Mismatch and flicker noise characterization of tantalum nitride thin film resistors for wireless applications H. Thibieroz, P. Shaner1, Z. C. Butler2 Digital DNA Labs RF/IF, Motorola, Austin, TX, USA 1Transportation Group, Motorola, Mesa, AZ, USA 2Department of Electrical Engineering, Southern Methodist University, Dallas, TX, USA DOI: 10.1109/ICMTS.2001.928663 HOVER FOR ABSTRACT | PDF Xplore | |
| Impact of transistor noise on high precision parametric matching measurements H. P. Tuinhout, J. H. Klootwijk, W. C. Goeke1, L. K. Stauffer1 Philips Research Laboratories, Eindhoven, Netherlands 1Keithley Instruments, Inc., Cleveland, OH, USA DOI: 10.1109/ICMTS.2001.928662 HOVER FOR ABSTRACT | PDF Xplore | |
| An accurate discrimination method of gate oxide breakdown positions by a new test structure of MOS capacitors H. Uchida, S. Ikeda, N. Hirashita OKI Electric Industry Company Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.2001.928667 HOVER FOR ABSTRACT | PDF Xplore | |
| Analysis of hot carrier effects in low temperature poly-Si TFTs using device simulator Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura1, Y. Tsuchihashi1 Materials Science, Nara Institute of Science and Technology, Ikoma, Nara, Japan 1LCD Division, Matsushita Elecrric Indusrrial Company Limited, Nomi, Ishikawa, Japan DOI: 10.1109/ICMTS.2001.928671 HOVER FOR ABSTRACT | PDF Xplore | |
| Determining the inductance of a through-substrate via using multiple on-wafer test approaches R. Uscola, M. Tutt DigitalDNA Laboratories CST, Motorola, Tempe, AZ, USA DOI: 10.1109/ICMTS.2001.928653 HOVER FOR ABSTRACT | PDF Xplore | |
| Direct extraction of equivalent circuit model parameters for HBTs R. Uscola, M. Tutt DigitalDNA Laboratories, CST, Motorola, Tempe, AZ, USA DOI: 10.1109/ICMTS.2001.928642 HOVER FOR ABSTRACT | PDF Xplore | |
| Modeling of non-linear polysilicon resistors for analog circuit design R. Virkus, D. Weiser, K. Green, D. Richardson, G. Westphal Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.2001.928643 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure and method for capacitance extraction in multi-conductor systems B. Ward, J. Bordelon, S. Prior, B. Tranchina1, Jiann Liu2 TestChip Technologies, Inc., Plano, TX, USA 12600 Technology Drive, Inc., Plano, Texas 2Science-Based Industrial Park, United Microelectronics Corporation, Hsin-Chu City, Taiwan, R.O.C DOI: 10.1109/ICMTS.2001.928660 HOVER FOR ABSTRACT | PDF Xplore | |
| Mis-match characterization of 1.8 V and 3.3 V devices in 0.18 µm mixed signal CMOS technology Ta-Hsun Yeh, J. C. H. Lin, Shyh-Chyi Wong, H. Huang, J. Y. C. Sun Logic Technology Development Division, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2001.928641 HOVER FOR ABSTRACT | PDF Xplore |
