IEEE International Conference on Microelectronic Test Structures
ICMTS 1997 Program
1997 Program Booklet
By First Author
| Wire-segment holographic test structures for statistical interconnect metrology S. A. AbuGhazaleh, J. T. M. Stevenson1, P. Christie, A. J. Walton1 Department of Electrical Engineering, University of Delaware, Newark, USA 1Department of Computer Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589353 HOVER FOR ABSTRACT | PDF Xplore | |
| A statistical method for the analysis of CMOS process fluctuations on dynamic performance M. De Almeida, X. Regnier1, J. M. Daga2, M. Robert2, D. Auvergne2 Aerospatiale, Suresnes, France 1Louis Blériot Research Center, AEROSPATIALE, Suresnes, France 2LIRMM, UMR CNRS Université Montpellier, Montpellier, France DOI: 10.1109/ICMTS.1997.589361 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures to measure the heat capacity of CMOS layer sandwiches M. von Arx, O. Paul, H. Baltes ETH ZurichPhysical Electronics Laboratory, ETH Zurich, Zurich, Switzerland DOI: 10.1109/ICMTS.1997.589399 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for hillock growth, via filling and for measuring the quality of thin films D. J. Bennett, A. O'Hara1, I. Underwood1, A. J. Walton1 Dept. of Electr. Eng., Edinburgh Univ., UK 1Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589295 HOVER FOR ABSTRACT | PDF Xplore | |
| Optical signal injection for high-speed wafer level function test of integrated circuits H. H. Berger, J. Sturm, F. Esfahani, A. Benedix, S. Von Aichberger, B. Muller, K. . -O. Hofacker1 Institute of Microelectronics and Solid State Electronics, Technical University Berlin, Berlin, Germany 1Thesys GmbH, Erfurt, Germany DOI: 10.1109/ICMTS.1997.589326 HOVER FOR ABSTRACT | PDF Xplore | |
| GIDL-induced charge injection for characterization of plasma edge damage in CMOS devices T. Brozek, A. Sridharan, J. Werking1, S. R. Anderson1, Y. D. Chan1, C. R. Viswanathan Department of Electrical Engineering, University of California, Los Angeles, USA 1SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1997.589348 HOVER FOR ABSTRACT | PDF Xplore | |
| New approach for the extraction of gate voltage dependent series resistance and channel length reduction in CMOS transistors H. Brut, A. Juge1, G. Ghibaudo2 SGS-Thomson Microelectron., Crolles, France 1Central R&D-Modeling and characterization, SGS-Thomson Microelectronics, Crolles, France 2Laboratoire de Physique des Composants à Semiconducteurs, URA CNRS-ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1997.589391 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures applied to the rapid prototyping of sensors M. G. Buehler, L. . -J. Cheng, D. P. Martin1 Microdevices Laboratory, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, USA 1Halcyon Microelectronics, Inc., Irwindale, USA DOI: 10.1109/ICMTS.1997.589406 HOVER FOR ABSTRACT | PDF Xplore | |
| Flicker noise characterization of polysilicon resistors in submicron BiCMOS technologies O. Roux dit Buisson, G. Morin SGS-Thomson Microelectronics, Crolles, France DOI: 10.1109/ICMTS.1997.589331 HOVER FOR ABSTRACT | PDF Xplore | |
| An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution J. C. Chen, D. Sylvester, C. Hu, H. Aoki1, S. Nakagawa1, S. . -Y. Oh1 Department of EECS, University of California, Berkeley, USA 1Hewlett Packard Laboratories, Palo Alto, USA DOI: 10.1109/ICMTS.1997.589342 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure and methodology for experimental extraction of threshold voltage shifts due to quantum mechanical effects in MOS inversion layers G. Chindalore, S. Hareland, S. Jallepalli1, A. F. Fasch2, C. M. Maziar, V. K. F. Chia3, S. Smith3 Microelectronics Research Center, Department of Electrical and Computer Engineering, University of Technology, Austin, TX, USA 1Motorola, Austin, TX, USA 2NA 3Charles Evans and Associates, Red Wood, USA DOI: 10.1109/ICMTS.1997.589377 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement and characterization of multi-layered interconnect capacitance for deep submicron VLSI technology Dae-Hyung Cho, Man-Ho Seung, Nam-Ho Kim, Hun-Sup Park, Jae-Kyung Wee1, Young-June Park1, Hong-Shik Min1 Advanced Device Physics Laboratory, System IC R & D Laboratory, Hyundai Electronics Industries Company Limited, Icheon, Gyeonggi, South Korea 1Department of Electrical Engineering, Seoul National University, Seoul, South Korea DOI: 10.1109/ICMTS.1997.589346 HOVER FOR ABSTRACT | PDF Xplore | |
| On wafer noise measurement using bipolar transistor RF test structures S. D. Connor Bipolar Characterization Group, Central Research and Development, G. E. C. Plessey Semiconductors, Lancashire, UK DOI: 10.1109/ICMTS.1997.589329 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for mismatch characterization of MOS transistors in subthreshold regime M. Conti, G. F. Dalla Betta1, S. Orcioni, G. Soncini1, C. Turchetti, N. Zorzi2 Department of Electronics, University of Ancona, Ancona, Italy 1Department of Materials Engineering, University of Trento, Trento, Italy 2Microelectronics Division, I.R.S.T., Trento, Italy DOI: 10.1109/ICMTS.1997.589380 HOVER FOR ABSTRACT | PDF Xplore | |
| Electrical linewidth test structures fabricated in mono-crystalline films for reference-material applications M. W. Cresswell, J. J. Sniegowski1, R. N. Ghoshtagore2, R. A. Allen2, W. F. Guthrie2, L. W. Linholm2 National Institute of Standards and Technology, Gaithersburg, MD, US 1Microelectronic Development Laboratories, Sandia National Laboratories, Albuquerque, NM, USA 2NA DOI: 10.1109/ICMTS.1997.589305 HOVER FOR ABSTRACT | PDF Xplore | |
| Electrical assessment of planarisation for CMP [inter-layer dielectrics] J. P. Elliott, M. Fallon, A. J. Walton, J. T. M. Stevenson, A. O'Hara, A. Shaffi, C. M. Reeves Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589345 HOVER FOR ABSTRACT | PDF Xplore | |
| Novel structure to measure emitter-base misalignment M. Fallon, M. Redford, K. Findlater1, M. Newsam1 National Semiconductor, Larkfield Industrial Estate, Greenock, UK 1Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589374 HOVER FOR ABSTRACT | PDF Xplore | |
| Yield prediction using calibrated critical area modelling G. J. Gaston, G. A. Allan1 GEC Plessey Semiconductors Limited, Plymouth, Devon, UK 1Department of Elect Engineering, Edinburgh University, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589292 HOVER FOR ABSTRACT | PDF Xplore | |
| A new technique and a test structure for evaluating Vth distribution of flash memory cells K. Hakozaki, S. . -I. Sato, K. Iguchi, K. Sakiyama VLSI Development Laboratories, IC Tenri Group, Sharp Corporation, Tenri, Japan DOI: 10.1109/ICMTS.1997.589355 HOVER FOR ABSTRACT | PDF Xplore | |
| New method for the parameter extraction in Si MOSFETs after hot carrier injection S. Hardillier, C. Mourrain, M. J. Bouzid, G. Ghibaudo1 France Telecom, CNET, Meylan, France 1Laboratorie de Physique des Composants à Semiconducteurs, ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1997.589336 HOVER FOR ABSTRACT | PDF Xplore | |
| Determination of defect size distributions based on electrical measurements at a novel harp test structure C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1997.589281 HOVER FOR ABSTRACT | PDF Xplore | |
| Issues on short circuits in large on-chip power MOS-transistors using a modified checkerboard test structure C. Hess, L. H. Weiland, R. Bornefeld1 Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany 1NA DOI: 10.1109/ICMTS.1997.589365 HOVER FOR ABSTRACT | PDF Xplore | |
| Error correction for finite semiconductor resistivity in Kelvin test structures A. S. Holland, G. K. Reeves, H. B. Harrison1 Royal Melbourne Institute of Technology, Melbourne, VIC, Australia 1Griffith University, Nathan, QLD, Australia DOI: 10.1109/ICMTS.1997.589347 HOVER FOR ABSTRACT | PDF Xplore | |
| Digital test circuit design and optimization for AC hot-carrier reliability characterization and model calibration under realistic high frequency stress conditions W. Jiang, H. Le, S. A. Kim, J. E. Chung, Y. . -J. Wu1, P. Bendix1, J. Jensen1, R. Ardans1, S. Prasad1, A. Kapoor1, T. E. Kopley, T. Dungan, P. Marcoux EECS Department, Massachusetts Institute of Technology, Cambridge, MA, USA 1Research and Development, LSI Logic Corporation, Milpitas, USA DOI: 10.1109/ICMTS.1997.589335 HOVER FOR ABSTRACT | PDF Xplore | |
| Test chip and data considerations for MOS parameter extraction P. R. Karlsson, K. O. Jeppson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1997.589375 HOVER FOR ABSTRACT | PDF Xplore | |
| Separation of intrinsic and parasitic MOSFET parameters using a multiple built-in Kelvin test structure N. Kasai, H. Mori1, T. Matsuki, I. Yamamoto, K. Koyama ULSI Device Development Labs, NEC Corporation Limited, Sagamihara, Kanagawa, Japan 1Microelectronics Research Labs, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.1997.589396 HOVER FOR ABSTRACT | PDF Xplore | |
| Improved method for the extraction of oxide charge density and centroid from the current-voltage characteristic shifts in a MOS structure after uniform gate stress R. Kies, G. Ghibaudo, G. Pananakakis, C. Papadas1 Laboratoire de Physique des Composants à Semiconducteurs, UMR CNRS, ENSERG, Grenoble, France 1SGS-Thomson Microelectronics, Crolles, France DOI: 10.1109/ICMTS.1997.589350 HOVER FOR ABSTRACT | PDF Xplore | |
| Design and characterization of SiGe TFT devices and process using Stanford's test chip design environment M. V. Kumar, V. Subramanian, K. C. Saraswat, J. D. Plummer, W. Lukaszek Center for Integrated Systems, University of Stanford, Stanford, USA DOI: 10.1109/ICMTS.1997.589363 HOVER FOR ABSTRACT | PDF Xplore | |
| Reference-length shortening by Kelvin voltage taps in linewidth test structures replicated in monocrystalline silicon films W. E. Lee, W. F. Guthrie, M. W. Cresswell, R. A. Allen, J. J. Sniegowski, L. W. Linholm Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1997.589322 HOVER FOR ABSTRACT | PDF Xplore | |
| A DC voltage capacitance matching tester B. W. McNeill, C. Hanle1 Bell Labs, Lucent Technologies, Inc., Allentown, PA, USA 1Analog Devices, Inc., Wilmington, MA, USA DOI: 10.1109/ICMTS.1997.589394 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for the evaluation of air-bridge interconnection in GaAs IC's fabrication process M. Nakanishi, M. Noda, H. Nakano, T. Sonoda, M. Otsubo Optoelectronic and Microwave Devices Laboratory, Mitsubishi Electric Corporation Limited, Hyogo, Japan DOI: 10.1109/ICMTS.1997.589408 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterisation of the threshold voltage variation: a test chip and the results M. Niewczas Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, Poland DOI: 10.1109/ICMTS.1997.589378 HOVER FOR ABSTRACT | PDF Xplore | |
| A new test structure for interconnect capacitance monitoring P. Nouet, A. Toulouse Laboratoire d'Informatique, de Robotique et ed Microéletronique de Montpellier LIRMM-U.M.R C55060, University of Montpellier 2, MONTPELLIER, France DOI: 10.1109/ICMTS.1997.589343 HOVER FOR ABSTRACT | PDF Xplore | |
| Performance evaluation of CMOS ring-oscillators with source/drain regions fabricated by asymmetric/symmetric ion-implantation T. Ohzone, T. Miyakawa1, T. Matsuda1, T. Yabu1, S. Odanaka1 Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan 1Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan DOI: 10.1109/ICMTS.1997.589356 HOVER FOR ABSTRACT | PDF Xplore | |
| A compact monitoring circuit for real-time on-chip diagnosis of hot-carrier induced degradation H. Oner, B. Bayrakci, Y. Leblebici1 Department of Electrical and Electronics Engineering, Istanbul Technical University, Turkey 1Electronics Laboratory, Integrated Systems Center DOI: 10.1109/ICMTS.1997.589340 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for characterising a damascene CMP interconnect process C. M. Peyne, A. O'Hara, J. T. M. Stevenson, J. P. Elliott, A. J. Walton, M. Fallon Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589369 HOVER FOR ABSTRACT | PDF Xplore | |
| A proposal for modeling substrate coupling in Si-MMICs and its experimental verification up to 40 GHz M. Pfost, H. . -M. Rein AG Halbleiterbauelemente, Ruhr University of Bochum, Bochum, Germany DOI: 10.1109/ICMTS.1997.589332 HOVER FOR ABSTRACT | PDF Xplore | |
| Integrated test circuit to measure polarization characteristics of ferroelectric capacitors for development of mega-bit scale FeRAM M. Takeo, M. Azuma, T. Sumi, K. Tatsuuma Kyoto Research Laboratory, Matsushita Electronics Corporation, Kyoto, Japan DOI: 10.1109/ICMTS.1997.589352 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation of hFE fluctuation of high-performance IDP emitter transistors by using test structures Y. Tamaki, T. Hashimoto, K. Watanabe, T. Shiba1 Device Development Center, Hitachi and Limited, Imai, Tokyo, Japan 1Central Research Laboratory, Hitachi and Limited, Imai, Tokyo, Japan DOI: 10.1109/ICMTS.1997.589388 HOVER FOR ABSTRACT | PDF Xplore | |
 | Test structures for investigation of metal coverage effects on MOSFET matching H. P. Tuinhout, M. Vertregt1 Philips Res. Lab., Eindhoven, Netherlands 1Philips Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1997.589386 HOVER FOR ABSTRACT | PDF Xplore |
| A digital test structure for simultaneous bird's beak length and misalignment measurement in polysilicon emitter bipolar technologies M. Ullan, M. Lozano, J. Santander, E. Lora-Tamayo, S. Nigrin1, P. H. Osborne1 Centro Nacional de Microelectrónica, Barcelona, Spain 1Cheney Manor, GEC Plessey Semiconductors Limited, Swindon, UK DOI: 10.1109/ICMTS.1997.589314 HOVER FOR ABSTRACT | PDF Xplore | |
| On the oxide thickness extraction in deep-submicron technologies E. Vincent, G. Ghibaudo1, G. Morin, C. Papadas SGS THOMSON Microelectronics, Central R&D, Crolles, France 1Laboratorie de Physique des Composants à Semiconducteurs ENSERG, UMR CNRS 5531, Grenoble, France DOI: 10.1109/ICMTS.1997.589349 HOVER FOR ABSTRACT | PDF Xplore | |
| Lateral power MOSFET low-doped drain (LDD) misalignment test structure I. M. Vitomirov, S. N. Seabridge, A. D. Raisanen, T. Tellier Xerox Corporation, Webster, NY, USA DOI: 10.1109/ICMTS.1997.589321 HOVER FOR ABSTRACT | PDF Xplore | |
| Optimization of via contact test structure for electro-migration S. Yamamoto, J. Komori, Y. Takata, M. Sekine, H. Koyama ULSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1997.589338 HOVER FOR ABSTRACT | PDF Xplore | |
| Study of "on-chip" measurement methods of thin film mechanical properties for micromachining Quanbo Zou, Zhijian Li, Litian Liu Institute of Microelectronics, Tsinghua University, Beijing, China DOI: 10.1109/ICMTS.1997.589404 HOVER FOR ABSTRACT | PDF Xplore |
