IEEE International Conference on Microelectronic Test Structures
ICMTS 1996 Program
1996 Program Booklet
By First Author
| Observation of light emissions from hot electrons and latch-up at the cleaved surface of CMOS structures T. Aoki NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1996.535660 HOVER FOR ABSTRACT | PDF Xplore | |
 | Test structures to measure the Seebeck coefficient of CMOS IC polysilicon M. von Arx, O. Paul, H. Baltes Physical Electronics Laboratory, Zurich, Switzerland DOI: 10.1109/ICMTS.1996.535631 HOVER FOR ABSTRACT | PDF Xplore |
| Analysis of charge storage in the base of bipolar transistors and its influence on the parasitic resistance adopting an eight terminal Kelvin test structure S. Asti, T. Cavioni1, A. Neviani, P. Pavan2, M. Stival, L. Vendrame, E. Zanoni2 Dipartimento di Elettronica e Informatica, Università di Padova, Padova, Italy 1Dedicated Products Group, SGS-THOMSON Microelectronics, Cornaredo, Italy 2Dipartimento di Scienze dell'Ingegneria, Università di Modena e Reggio Emila, Modena, Italy DOI: 10.1109/ICMTS.1996.535627 HOVER FOR ABSTRACT | PDF Xplore | |
| Narrow width effects in CMOS n(p)-well resistors C. Auricchio, R. Bez, A. Grossi SGS-Thomson Microelectronics, Central Research and Development, Milan, Italy DOI: 10.1109/ICMTS.1996.535614 HOVER FOR ABSTRACT | PDF Xplore | |
| Influence of die attachment on MOS transistor matching J. Bastos, M. Steyaert, B. Graindourze1, W. Sansen ESAT MICAS, Katholieke Universiteit Leuven, Belgium 1Alcatel Mietec, Oudenaarde, Belgium DOI: 10.1109/ICMTS.1996.535617 HOVER FOR ABSTRACT | PDF Xplore | |
| Matching of MOS transistors with different layout styles J. Bastos, M. Steyaert, B. Graindourze1, W. Sansen ESAT-MICAS, Katholieke Universiteit Leuven, Belgium 1Alcatel Mietec, Belgium DOI: 10.1109/ICMTS.1996.535615 HOVER FOR ABSTRACT | PDF Xplore | |
| A test chip for the development of PIN-type silicon radiation detectors G. F. Dalla Betta, M. Boscardin1, G. Verzellesi, G. U. Pignatel, A. Fazzi2, G. Soncini1 Dipartimento di Ingegneria dei Materiali, Università di Trento, Trento, Italy 1IRST, Trento, Italy 2Dipartimento di Ingegneria Nucleare, Politecnico di Milano, Milan, Italy DOI: 10.1109/ICMTS.1996.535652 HOVER FOR ABSTRACT | PDF Xplore | |
| Microwave frequency measurements and modeling of MOSFETs on low resistivity silicon substrates C. Biber, T. Morf, H. Benedickter, U. Lott, W. Bachtold Laboratory for Electromagnetic Fields and Microwave Electronics, Swiss Federal Institute of Technology, Zurich, Switzerland DOI: 10.1109/ICMTS.1996.535648 HOVER FOR ABSTRACT | PDF Xplore | |
| Matching properties of MOS transistors and delay line chains with self-aligned source/drain contacts M. Bolt, E. Cantatore1, M. Socha, C. Aussems, J. Solo Philips Semiconductors Faselec AG, Zurich, Switzerland 1CERN ECP EDU, Geneva, Switzerland DOI: 10.1109/ICMTS.1996.535616 HOVER FOR ABSTRACT | PDF Xplore | |
| An efficient parameter extraction methodology for the EKV MOST model M. Bucher, C. Lallement, C. C. Enz Electronics Laboratory, ELB-Ecublens, Swiss Federal Institute of Technology, Lausanne, Switzerland DOI: 10.1109/ICMTS.1996.535636 HOVER FOR ABSTRACT | PDF Xplore | |
| Gas sensor test chip M. G. Buehler, M. A. Ryan Jet Propulsion Laboratoiry, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1996.535629 HOVER FOR ABSTRACT | PDF Xplore | |
| A quasi-three-dimensional analysis of ESD failure mechanism and a new ESD structure with rounded drain corner Jae-Hoon Choi, Hyeong-Sun Hong, Yo-Hwan Koh, Gyoo-Yeong Lee, Han-Gu Kim, Han-Sub Yoon Memory Research and Development Division, Hyundai Electronics Industries Company Limited, South Korea DOI: 10.1109/ICMTS.1996.535647 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure for monitoring micro-loading effect of MOSFET gate length Joe-Sun Choi, In-Sool Chung Semiconductor Research and Development Division I, Design Laboratory II, Hyundai Electronics Industries Company Limited, South Korea DOI: 10.1109/ICMTS.1996.535612 HOVER FOR ABSTRACT | PDF Xplore | |
| Automated extraction of matching parameters for bipolar transistor technologies S. D. Connor, D. Evanson Microelectronics Centre, G. B. C. Plessey Semiconductoirs, Lancashire, UK DOI: 10.1109/ICMTS.1996.535618 HOVER FOR ABSTRACT | PDF Xplore | |
| Hybrid optical-electrical overlay test structure [for CMOS] M. W. Cresswell, R. A. Allen, L. W. Linholm, W. F. Guthrie, A. W. Gurnell1 National Institute for Standards and Technology, Gaithersburg, MD, USA 1NA DOI: 10.1109/ICMTS.1996.535613 HOVER FOR ABSTRACT | PDF Xplore | |
| Electrical characterisation and reliability studies of thick film gas sensor structures I. Czech, J. Manea1, J. Roggen2, G. Huyberechts, L. Stals3, L. De Schepper Institute for Material ResearchMaterial Physics Division, Limburg University Centre, Belgium 1Mater. Phys. Div., Limburgs Univ. Centrum, Diepenbeek, Belgium 2Materials and Packaging Division, IMEC, Belgium 3Institute for Material Research, Material Physics Division, Limburg University Centre, Belgium DOI: 10.1109/ICMTS.1996.535628 HOVER FOR ABSTRACT | PDF Xplore | |
| Parametric test engineering optimization: methodology and software system T. T. d'Ouville, F. Mendez, J. Bruines1, L. Zangara2, G. Durieu2 France Telecom CNET Grenoble, France 1Philips Semiconductors, Netherlands 2Dolphin Integration, Meylan, France DOI: 10.1109/ICMTS.1996.535643 HOVER FOR ABSTRACT | PDF Xplore | |
| Spatial distribution of recombination centers in electron irradiated silicon epitaxial layers S. Daliento, A. Sanseverino, P. Spirito, L. Zeni Dipartimento di Ingegneria Elettronica, Universita degli Studi di Napoli Federico II, Napoli, Italy DOI: 10.1109/ICMTS.1996.535639 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure for the measurement of planarisation J. P. Elliott, M. Fallon1, A. J. Walton2, J. T. M. Stevenson, A. O'Hara2 Edinburgh Microfabricutiorl Facility Department of Electrical Engineering, Kings Buildings, University of Edinburgh, Edinburgh, UK 1The University of Edinburgh, Edinburgh, Edinburgh, GB 2Dept. of Electr. Eng., Edinburgh Univ., UK DOI: 10.1109/ICMTS.1996.535664 HOVER FOR ABSTRACT | PDF Xplore | |
| On the impact of spatial parametric variations on MOS transistor mismatch H. Elzinga Philips Semiconductors, Centre Commun CNET-SGS-Thomson, Crolles, France DOI: 10.1109/ICMTS.1996.535641 HOVER FOR ABSTRACT | PDF Xplore | |
| Optimum test structure design for CMOS parasitic transistor characterisation G. J. Gaston, P. Myler GEC Plessey Semiconductors Limited, UK DOI: 10.1109/ICMTS.1996.535663 HOVER FOR ABSTRACT | PDF Xplore | |
| A test chip for the development of porous silicon light emitting diodes R. Guardini, P. Bellutti1, L. Pavesi, G. Soncini1, O. Bisi I.N.F.M. and Dipartimento di Fisica, Università di Trento, Trento, Italy 1Divisione Microsensori ed Integrazione di Sistemi, IRST, Trento, Italy DOI: 10.1109/ICMTS.1996.535651 HOVER FOR ABSTRACT | PDF Xplore | |
| A new approach to determine active doping profiles of bipolar transistors using electrical measurements and a physical device simulator I. Hachicha, P. Fouillat, T. Zimmer, J. P. Dom Cours de la liberation, IXL Universite Bordeaux I, France DOI: 10.1109/ICMTS.1996.535662 HOVER FOR ABSTRACT | PDF Xplore | |
| Control of application specific interconnection on gate arrays using an active checkerboard test structure C. Hess, L. H. Weiland, G. Lau1, P. Simoncit2 Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany 1Thesys Gesellschaft für Mikroelektronik mbH, Erfurt, Germany 2NA DOI: 10.1109/ICMTS.1996.585568 HOVER FOR ABSTRACT | PDF Xplore | |
| A quick address detection of an anomalous memory cell for flash EEPROM T. Himeno, H. Hazama, K. Sakui, K. Kanda, Y. Itoh, J. Miyamoto Semiconductor Device Engineering Laboratory, Toshiba Corporation, Japan DOI: 10.1109/ICMTS.1996.535645 HOVER FOR ABSTRACT | PDF Xplore | |
| A new method of determining the effective channel width and its dependence on the gate voltage K. O. Jeppson, A. W. Bogren, P. R. Karlsson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1996.535637 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure advisor and a coupled, library-based test structure layout and testing environment M. V. Kumar, J. D. Plummer, W. Lukaszek Center for Integrated Systems, University of Stanford, USA DOI: 10.1109/ICMTS.1996.535646 HOVER FOR ABSTRACT | PDF Xplore | |
| A new test structure methodology for MOS hot carrier reliability M. Lee Engineering, Department Information & Communication Engineering, Dong-shin University, Choongnam, South Korea DOI: 10.1109/ICMTS.1996.535657 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterizing the mismatch of submicron MOS transistors S. J. Lovett, R. Clancy, M. Welten, A. Mathewson, B. Mason1 National Microelectronics Research Centre, University College Cork, Cork, Ireland 1GEC Plessey Semiconductors Limited, Plymouth, UK DOI: 10.1109/ICMTS.1996.535619 HOVER FOR ABSTRACT | PDF Xplore | |
| A test chip for ISFET/CMNOS technology development A. Lui, B. Margesin, V. Zanini, M. Zen, G. Soncini, S. Martinoia1 Microsensors and System Integration Division, IRST, Italy 1DIBE-Department of Biophysical iind Electronic Engineering, University of Genova, Genoa, Italy DOI: 10.1109/ICMTS.1996.535632 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure to measure the gate-drain coupling capacitor using accelerated techniques T. Manku Technical University of Nova Scotia, Halifax, NS, Canada DOI: 10.1109/ICMTS.1996.535621 HOVER FOR ABSTRACT | PDF Xplore | |
| Simultaneous determination of threshold voltage, mobility, and parasitic resistance for short-channel MOSFETs Y. Mita, M. Fujishima, K. Hoh Univ. of Tokyo, Japan DOI: 10.1109/ICMTS.1996.535633 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for investigating activated doping concentrations in polycrystalline silicon S. Moran, P. K. Hurley, A. Mathewson National Microelectronics Research Centre, University College, Prospect, Ireland DOI: 10.1109/ICMTS.1996.535649 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for electromigration evaluation in submicron technology S. Morgan, I. De Munari1, A. Scorzoni1, F. Fantini, G. Magri2, C. Zaccherini2, C. Caprile2 Dipartimento di Ingegneria dell'hformazione, Universita degli Studi di Parma, Parma, Italy 1CNR Istituto LAMEL, Bologna, Italy 2SGS-Thomson Microelectronics, Milan, Italy DOI: 10.1109/ICMTS.1996.535661 HOVER FOR ABSTRACT | PDF Xplore | |
| Automatic test chip documentation synthesis W. Nagorski, W. McGee, E. G. Piccioli, L. A. Bair Digital Equipment Corporation, Hudson, MA, USA DOI: 10.1109/ICMTS.1996.535650 HOVER FOR ABSTRACT | PDF Xplore | |
| Kelvin test structure for measuring contact resistance of shallow junctions L. K. Nanver, E. J. G. Goudena, J. Slabbekoorn1 Delft Institute of Microelectronics and Submicron TechnologyDIMES IC Process Research Sector, Delft University of Technnology, Delft, Netherlands 1Inst. of Microelectron. & Submicron Technol., Delft Univ. of Technol., Netherlands DOI: 10.1109/ICMTS.1996.535654 HOVER FOR ABSTRACT | PDF Xplore | |
| Numerical analysis of the effect of geometry on the performance of the Greek cross structure M. I. Newsam, A. J. Walton, M. Fallon Edinburgh Microfabrication Facility Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1996.535655 HOVER FOR ABSTRACT | PDF Xplore | |
| CMOS IC transient radiation effects investigations, model verification and parameter extraction with the test structures laser simulation tests A. Y. Nikiforov, V. I. Chumakov, O. Skorobogatov Specialized Electronic Systems, Moscow, Russia DOI: 10.1109/ICMTS.1996.535656 HOVER FOR ABSTRACT | PDF Xplore | |
| Gate delay time evaluation structure for deep-submicron CMOS LSIs K. Nishimura, M. Urano, M. Ino, K. Takeya, T. Ishihara1, Y. Kado, H. Inokawa NTT LSI Laboratories, Atsugi, Kanagawa, Japan 1NTT LSI Labs., Atsugi, Japan DOI: 10.1109/ICMTS.1996.535634 HOVER FOR ABSTRACT | PDF Xplore | |
| A test chip for interconnect capacitance modelling in a CMOS process P. Nouet, A. Toulouse Laboratoire dE28099Informatique, de Robotique et de Microélectronique de Montpellier LIRMM, Universite Montpellier II, Montpellier, France DOI: 10.1109/ICMTS.1996.535622 HOVER FOR ABSTRACT | PDF Xplore | |
| Asymmetry and mismatch in CMOSFETs with source/drain regions fabricated by various ion-implantation methods T. Ohzone, T. Miyakawa, T. Yabu1, S. Odanaka1 Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan 1Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Osaka, Japan DOI: 10.1109/ICMTS.1996.535640 HOVER FOR ABSTRACT | PDF Xplore | |
| Use of test structures for a wafer-level-reliability monitoring A. Papp, F. Bieringer, D. Koch, H. Kammer, H. Pohle, A. Schlemm, M. Schneegans, H. Vogt Corporate Research and Development, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1996.535658 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for HF characterization of fully differential building blocks E. Peeters, M. Steyaert, W. Sansen Department of Electrical Engineering,ESAT-MICAS, Katholieke Universiteit Leuven, Belgium DOI: 10.1109/ICMTS.1996.535642 HOVER FOR ABSTRACT | PDF Xplore | |
| A new test structure for the evaluation of the injection-level dependence of carrier mobilities G. V. Persiano, S. Bellone1 Department of Electronics Engineering, University of Naples, Naples, Italy 1Department of Information and Electrical Engineering, University of Salerno, Salerno, Italy DOI: 10.1109/ICMTS.1996.535624 HOVER FOR ABSTRACT | PDF Xplore | |
| An electrical test structure to evaluate substrate compatibility with wafer cleaning C. M. Peyne, M. Fallon1, J. T. M. Stevenson1, A. J. Walton1 Newton Industrial Estate, EKC Technology Limited, UK 1Edinburgh Microfabrication Facility Department of Electrical Engineering Kings Buildings, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1996.535882 HOVER FOR ABSTRACT | PDF Xplore | |
| Electrical determination of the phosphorus content in thin phosphosilicate glass films O. Popa, C. Cobianu, D. Dascalu Institute of Microtechnology, Bucharest, Romania DOI: 10.1109/ICMTS.1996.535653 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement of interface states in the LDD region of a MOS transistor using a modified charge pumping technique V. Prabhakar, T. Broiek1, Y. D. Chan2, C. R. Viswanathan Electrical Engineering Department, UCLA, Los Angeles, CA, USA 1Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA 2Rockwell International SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1996.535626 HOVER FOR ABSTRACT | PDF Xplore | |
| Direct extraction method of SOI MOSFET transistors parameters J. P. Raskin, R. Gillon, D. Vanhoenacker, J. P. Colinge1 Laboratoire dE28099Hyperfreqluences, Universite Catholique de Louvain, Louvain-la-Neuve, Belgium 1NA DOI: 10.1109/ICMTS.1996.535644 HOVER FOR ABSTRACT | PDF Xplore | |
| Universal surfaces for the accurate contact resistivity extraction on Kelvin structures with upper and lower resistive layers J. Santander, M. Lozano, A. Gotz, C. Cane, E. Lora-Tamayo Centro Nacional de Microelectrónica, Universidad Autónoma de Barcelona, Barcelona, Spain DOI: 10.1109/ICMTS.1996.535623 HOVER FOR ABSTRACT | PDF Xplore | |
| A new method to determine effective channel length, series resistance and threshold voltage M. Sasaki, H. Ito, T. Horiuchi ULSI Device Development Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.1996.535635 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for automated contactless inline wafer inspection A. V. S. Satya IBM Microelectronics, East Fishkill, NY, USA DOI: 10.1109/ICMTS.1996.535665 HOVER FOR ABSTRACT | PDF Xplore | |
| An improved test structure to characterize ultra-low hot carrier injection in homogeneous conditions L. Selmi, R. Bez1, E. Sangiorgi2 DEIS, University of Bologna, Bologna, Italy 1SGS-THOMSON Microelectronics, Italy 2DIEGM, University of Udine, Udine, Italy DOI: 10.1109/ICMTS.1996.535625 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for thermal monitoring V. Szekely, Z. Kohari, C. Marta, M. Rencz, B. Courtois1 Department of Electron Devices, Technical University of Budapest, Budapest, Hungary 1TIMA Laboratory, Grenoble, France DOI: 10.1109/ICMTS.1996.535630 HOVER FOR ABSTRACT | PDF Xplore | |
| Heating due to bias in GaAs MESFETs J. R. Tellez, R. W. Clarke Department of Electronic & Electrical Engineering, University of Bradford, UK DOI: 10.1109/ICMTS.1996.535638 HOVER FOR ABSTRACT | PDF Xplore | |
| A wafer level monitoring method for plasma-charging damage using antenna PMOSFET test structure H. Watanabe, J. Komori, K. Higashitani, Y. Mashiko, H. Koyama ULSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1996.535659 HOVER FOR ABSTRACT | PDF Xplore | |
| On matching properties and process factors for submicrometer CMOS Shyh-Chyi Wong, Kuo-Hua Pan1, Dye-Jyun Ma2, M. S. Liang3, P. N. Tseng3 Department of Electronics Engineering, Feng Chia University FCU, Taichung, Taiwan 1Institute of Electronics, National Chiao Tung University, HsinChu, Taiwan 2Department of Electrical Engineering, Chung-Hsing University, Taichung, Taiwan 3Taiwan Semiconductor Manufacturing Company Limited, HsinChu, Taiwan DOI: 10.1109/ICMTS.1996.535620 HOVER FOR ABSTRACT | PDF Xplore |
