IEEE International Conference on Microelectronic Test Structures
ICMTS 1995 Program
By First Author
| A new characterization of sub-µm parallel multilevel interconnects and its experimental verification K. Aoyama, K. Ise1, H. Sato, K. Tsuneno, H. Masuda Hitachi and Limited, Imai, Tokyo, Japan 1Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1995.513946 HOVER FOR ABSTRACT | PDF Xplore | |
| Modified transmission line pulse system and transistor test structures for the study of ESD R. A. Ashton AT&T Bell Laboratories Engineering Research Center, Orlando, FL, USA DOI: 10.1109/ICMTS.1995.513959 HOVER FOR ABSTRACT | PDF Xplore | |
| Use of SPIDER for the identification and analysis of process induced damage in 0.35 µm transistors P. Aum, Xiaoyu Li1, V. Prabhakar1, T. Brozek1, C. R. Viswanathan1 SEMATECH, Austin, TX, USA 1Electrical Engineering Department,School of Medicine, University of California, Los Angeles, Los Angeles, CA, USA DOI: 10.1109/ICMTS.1995.513935 HOVER FOR ABSTRACT | PDF Xplore | |
| Mismatch characterization of small size MOS transistors J. Bastos, M. Steyaert, R. Roovers, P. Kinget, W. Sansen, B. Graindourze1, A. Pergoot1, E. Janssens1 Department of Electrical Engineering,ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee, Belgium 1Alcatel Mietec, Oudenaarde, Belgium DOI: 10.1109/ICMTS.1995.513986 HOVER FOR ABSTRACT | PDF Xplore | |
| Depth measurements using alpha particles and upsetable SRAMs M. G. Buehler, M. Reier, G. A. Soli Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1995.513983 HOVER FOR ABSTRACT | PDF Xplore | |
| An efficient method to predict drain current dispersion in MOS transistors from technological parameters fluctuations M. Conti, S. Orcioni, C. Turchetti, P. L. Bellutti1, M. Zen1, N. Zorzi1, G. Soncini2 Department of Electronics, University of Ancona, Ancona, Italy 1Microelectronics Division, IRST, Trento, Italy 2Department of Materials Engineering, University of Trento, Trento, Italy DOI: 10.1109/ICMTS.1995.513974 HOVER FOR ABSTRACT | PDF Xplore | |
| Soft error immunity of 1-Volt CMOS memory cells with MTCMOS technology T. Douseki, S. Mutoh, T. Ueki, J. Yamada NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1995.513955 HOVER FOR ABSTRACT | PDF Xplore | |
| An electrical test structure to evaluate linewidth variations due to proximity effects in optical lithography M. Fallon, J. T. M. Stevenson, A. Walton, A. M. Gundlach1 Edinburgh Microfabrication Facility Department of Electrical Engineerin, University of Edinburgh, Edinburgh, UK 1Dept. of Electr. Eng., Edinburgh Univ., UK DOI: 10.1109/ICMTS.1995.513941 HOVER FOR ABSTRACT | PDF Xplore | |
| An in-process monitoring method for electromigration resistance of multilayered metal interconnects T. Fujii, T. Itoh, H. Ishizuka, K. Okuyama, K. Kubota Semiconductor and Integrated Circuit Div, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1995.513951 HOVER FOR ABSTRACT | PDF Xplore | |
| A new extraction method for unit bipolar junction transistor capacitance parameters N. Gambetta, B. Cialdella, D. Celi, M. Depey1 SGS THOMSON Microelectronics, Central Research and Development Laboratory, France 1LPCS-ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1995.513965 HOVER FOR ABSTRACT | PDF Xplore | |
| Efficient extraction of metal parasitic capacitances G. J. Gaston, I. G. Daniels GEC Plessey Semiconductors Limited, Plymouth, UK DOI: 10.1109/ICMTS.1995.513964 HOVER FOR ABSTRACT | PDF Xplore | |
| Wafer-level electromigration tests on NIST and SWEAT structures F. Giroux, C. Gounelle, P. Mortini1, G. Ghibaudo2 Central Research and Development, SGS-Thomson Microelectronics, France 1Central R&D, SGS-Thomson Microelectron., Crolles, France 2LPCS-ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1995.513978 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement of contact resistance distribution using a 4k contacts array T. Hamamoto, T. Ozaki, M. Aoki1, Y. Ishibashi2 Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP 1ULSI Res. Center, Toshiba Corp., Kawasaki, Japan 2ULSI Research Center, Toshiba Corporation, Kawasaki, Japan DOI: 10.1109/ICMTS.1995.513945 HOVER FOR ABSTRACT | PDF Xplore | |
| Defect parameter extraction in backend process steps using a multilayer checkerboard test structure C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1995.513944 HOVER FOR ABSTRACT | PDF Xplore | |
| Influence of short circuits on data of contact and via open circuits determined by a novel weave test structure C. Hess, L. H. Weiland Institute fo Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1995.513937 HOVER FOR ABSTRACT | PDF Xplore | |
| Resistance modeling of test structures for accurate fault detection in backend process steps using a digital tester C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1995.513985 HOVER FOR ABSTRACT | PDF Xplore | |
 | A new technique for measuring threshold voltage distribution in flash EEPROM devices T. Himeno, N. Matsukawa, H. Hazama, K. Sakui, M. Oshikiri, K. Masuda, K. Kanda, Y. Itoh, J. Miyamoto Semiconductor Device Engineering Laboratory, Toshiba Corporation, Japan DOI: 10.1109/ICMTS.1995.513988 HOVER FOR ABSTRACT | PDF Xplore |
| Precise measurement of P-N junction leakage current generated in Si subsurface M. Horikawa, T. Mizutani1, K. Noda, T. Kitano ULSI Device Development Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan 1Microelectronics Research Laboratories, NEC Corporation Limited, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.1995.513956 HOVER FOR ABSTRACT | PDF Xplore | |
| Statistical modeling tools, methods and applications for integrated circuit manufacturability F. Iravani, M. Habu, E. Khalily Hewlett Packard Company, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1995.513973 HOVER FOR ABSTRACT | PDF Xplore | |
| Leak current characterization in high frequency operation of CMOS circuits fabricated on SOI substrate H. Ito, K. Asada Department of Electronic Engineering, University of Tokyo, Hongo, Tokyo, Japan DOI: 10.1109/ICMTS.1995.513947 HOVER FOR ABSTRACT | PDF Xplore | |
| A capacitance method to determine the metallurgical gate-to-source/drain overlap length of submicron LDD MOSFETs Myung-Suk Jo, Jin-Hyoung Kim1, Sung-Ki Kim1, Han-Sub Yoon1, Dai-Hoon Lee1 Department of Electronic Engineering, Kangnung National University, Kangwon, South Korea 1Semiconductor Research and Development Laboratories, Hyundai Electronics Industries Company Limited, Ichon, Kyonggi, South Korea DOI: 10.1109/ICMTS.1995.513963 HOVER FOR ABSTRACT | PDF Xplore | |
| The Wheatstone bridge as an alignment test structure U. Kaempf Hewlett-Packard SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1995.513940 HOVER FOR ABSTRACT | PDF Xplore | |
| Electrical gate length measurement test structure for short channel MOSFET characteristics evaluation N. Kasai, I. Yamamoto, K. Koyama ULSI Device Development Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.1995.513942 HOVER FOR ABSTRACT | PDF Xplore | |
| Reliability evaluation of thin gate oxide using a flat capacitor test structure M. Katsumata, J. Mitsuhashi, K. Kobayashi, Y. Mashiko, H. Koyama ULSI Laboratory Evaluation & Analysis Center, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1995.513954 HOVER FOR ABSTRACT | PDF Xplore | |
| On-chip measurement of interconnect capacitances in a CMOS process A. Khalkhal, P. Nouet Laboratoire dE28099Informatique, de Robotique et dc Microelectronique de Montpellier, Universite Montpellier II/CNRS, Montpellier, France DOI: 10.1109/ICMTS.1995.513962 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for the evaluation of Si substrates Y. Kokawa, M. Kimura, M. Kume, H. Yamamoto, A. Koyama ULSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1995.513950 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation of charge build-up in wafer processing by using MOS capacitors with charge collecting electrodes H. Kubo, T. Namura, K. Yoneda, H. Ohishi, Y. Todokoro Kyoto Research Laboratory, Matsushita Electronics Corporation, Kyoto, Japan DOI: 10.1109/ICMTS.1995.513936 HOVER FOR ABSTRACT | PDF Xplore | |
| A new test structure to study electromigration at grain boundaries using the single-crystal aluminum interconnection K. Kusuyama, Y. Nakajima, Y. Murakami Electronics and Information Systems Research Laboratory, Nissan Motor Company Limited, Yokosuka, Kanagawa, Japan DOI: 10.1109/ICMTS.1995.513977 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure for the measurement of fast internal signals in CMOS VLSI circuits B. Laquai, H. Richter, B. Hoefflinger IMS, Stuttgart, Germany DOI: 10.1109/ICMTS.1995.513943 HOVER FOR ABSTRACT | PDF Xplore | |
| Direct determination of base transit time for heterojunction bipolar transistors without cutoff frequency measurement Seonghearn Lee Semiconductor Technology Division, Electronics and Telecommunications Research Institute, Taejon, South Korea DOI: 10.1109/ICMTS.1995.513957 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement of patterned film linewidth for interconnect characterization L. W. Linholm, R. A. Allen, M. W. Cresswell, R. N. Ghoshtagore, S. Mayo, H. A. Schafft, J. A. Kramar1, E. C. Teague1 Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Precision Engineering Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1995.513939 HOVER FOR ABSTRACT | PDF Xplore | |
| A test chip for MOS transistor capacitance characterization R. Lorival, P. Nouet Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), Universite Montpellier II/CNRS, Montpellier, France DOI: 10.1109/ICMTS.1995.513961 HOVER FOR ABSTRACT | PDF Xplore | |
| Three-port RF characterization of foundry dual-gate FETs using two-port test structures with on-chip loading resistors U. Lott, W. Baumberger, U. Gisiger1 Laboratory for Electromagnetic Fields and Microwave Electronics, Swiss Federal Institute of Technology, Zurich, Switzerland 1AFIF, Zurich, Switzerland DOI: 10.1109/ICMTS.1995.513966 HOVER FOR ABSTRACT | PDF Xplore | |
| Non-destructive method of shear stress test by new test structure H. Matsushima, T. Wada Matsushita Electronics Corporatio, Quality Laboratory Semiconductor Group, Kyoto, Japan DOI: 10.1109/ICMTS.1995.513938 HOVER FOR ABSTRACT | PDF Xplore | |
| Gate antenna structures for monitoring oxide quality and reliability S. R. Nariani, C. T. Gabriel, D. Pramanik, K. Ng VLSI Technology, Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.1995.513952 HOVER FOR ABSTRACT | PDF Xplore | |
| Electrical characteristics of CMOSFETs with gates crossing source/drain regions at 90° and 45° T. Ohzone, N. Matsuyama Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.1995.513970 HOVER FOR ABSTRACT | PDF Xplore | |
| Source/drain junction leakage current of LDD NMOSFET with various spacer materials Jae-Chul Om, Myung-Suk Jo1, Hyo-Sik Park, In-Sool Chung, Wi-Sik Min Semiconductor Research and Development Laboratory, Hyundai Electronics Industries Company Limited, South Korea 1Department of Electronic Engineering, Kangnung National University, Kangnung, Kangwon, South Korea DOI: 10.1109/ICMTS.1995.513968 HOVER FOR ABSTRACT | PDF Xplore | |
| An automated approach to wafer distribution analysis C. Perello, M. Lozano, J. Millan1, E. Lora-Tamayo Centre Nacional de Microelectrònica, Universitat Autònoma Barcelona, Barcelona, Spain 1Centre Nacional de Microelectron., Univ. Autonoma de Barcelona, Spain DOI: 10.1109/ICMTS.1995.513972 HOVER FOR ABSTRACT | PDF Xplore | |
| Statistics for matching A. Pergoot, B. Graindourze, E. Janssens, J. Bastos1, M. Steyaert1, P. Kinget1, R. Roovers1, W. Sansen1 Alcatel Mietec, Oudenaarde, Belgium 1Department of Electrical Engineering,ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1995.513971 HOVER FOR ABSTRACT | PDF Xplore | |
| United methodology for pre-determination of bipolar transistor SPICE model parameters for low, middle and high power ICs K. O. Petrosjanc, I. A. Kharitonov1, N. I. Rjabov Moscow University of Electronics and Mathematics, Moscow, Russia 1Moscow Univ. of Electron. & Math., Russia DOI: 10.1109/ICMTS.1995.513975 HOVER FOR ABSTRACT | PDF Xplore | |
| Evidence of a correlation between process yields and reliability data for a rad-hard SOI technology V. Riviere, A. Touboul, S. B. Amor1, G. Gregoris2, J. L. Stevenson3, P. S. Yeung3 IXL, URA 846-CNRS, Université Bordeaux 1, Talence, France 1NA 2Alcatel ESpace, Toulouse, France 3Intelsat Limited, Washington D.C., DC, USA DOI: 10.1109/ICMTS.1995.513976 HOVER FOR ABSTRACT | PDF Xplore | |
| A combined CBR-MOS gate structure for mobility and channel width extraction J. Santander, M. Lozano, C. Cane, E. Lora-Tamayo Campus UAB,Centro Nacional de Microelectróica, CSIC, Spain DOI: 10.1109/ICMTS.1995.513987 HOVER FOR ABSTRACT | PDF Xplore | |
| A new hierarchical RSM for TCAD-based device design to predict CMOS development H. Sato, K. Tsuneno, K. Aoyama, T. Nakamura, H. Kunitomo1, H. Masuda Hitachi and Limited, Tokyo, Japan 1Hitachi Micro-computer Engineer, Tokyo, Japan DOI: 10.1109/ICMTS.1995.513991 HOVER FOR ABSTRACT | PDF Xplore | |
| Determination of solid solubility limit of In and Sb in Si using bonded silicon-on-insulator (SOI) substrate A. Sato, K. Suzuki, H. Horie, T. Sugii Fujitsu Laboratories of America, Inc., Atsugi, Japan DOI: 10.1109/ICMTS.1995.513984 HOVER FOR ABSTRACT | PDF Xplore | |
| Stress induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics S. Satoh, G. J. Hemink, F. Hatakeyama1, S. Aritome ULSI Research Center, TOSHIBA Corporation, Kawasaki, Japan 1Microelectronics Center, ULSI Research Center, Kawasaki, Japan DOI: 10.1109/ICMTS.1995.513953 HOVER FOR ABSTRACT | PDF Xplore | |
| Understanding clustering of defects in a sub-0.5 µm CMOS fabricator A. V. S. Satya Zip EMI, IBM Microelectronics, NY, USA DOI: 10.1109/ICMTS.1995.513990 HOVER FOR ABSTRACT | PDF Xplore | |
| The charging and discharging of stress-generated traps inside thin silicon oxide R. S. Scott, D. J. Dumin1 Center for Semiconductor Device Reliability Research, Department of Electrical and Computer Engineering, Clemson University, Clemson, SC, USA 1Clemson University, Clemson, SC, US DOI: 10.1109/ICMTS.1995.513979 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for determining the charge distribution in the oxide of MOS structure Y. Takahashi, S. Imaki, K. Ohnishi, M. Yoshikawa1 Dcpartment of Electronic Engineering College of Science Technology, Nihon University, Funabashi, Chiba, Japan 1Takasaki Radiation Chemistry Research, Establishment Japan Atomic Energy Research Institute, Takasaki, Japan DOI: 10.1109/ICMTS.1995.513981 HOVER FOR ABSTRACT | PDF Xplore | |
| Influence of tilted high-energy ion-implantation upon scaled CMOS structure H. Takatsuka, H. Sato, T. Izawa, T. Hisaeda, H. Goto, S. Kawamura LSI Process Development Div, Fujitsu Laboratories of America, Inc., Kawasaki, Japan DOI: 10.1109/ICMTS.1995.513982 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization of density of trap states at the back interface of SIMOX wafers A. Takubo, T. Hanajiri, T. Sugano, K. Kajiyama1 EE Department, Toyo University, Kawagoe, Japan 1Advanced Semiconductor Technology Laboratory, Nippon Steel Corporation, Kanagawa, Japan DOI: 10.1109/ICMTS.1995.513949 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure and simplified distribution model for identification of base resistance components in self-aligned polysilicon base electrode bipolar transistors M. Tanabe, H. Shimamoto, T. Onai1, K. Washio1 Musashino Office, Hitachi Device Engineering Company Limited, Tokyo, Japan 1Central Research Laboratory, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1995.513958 HOVER FOR ABSTRACT | PDF Xplore | |
| Accurate determination of the main parameters from Vt(Vb) curves of fully-depleted SOI devices A. Toffoli, J. L. Pelloie, O. Faynot, C. Raynaud, B. Giffard, J. Hartmann LETI (CEA Technologies Avancees), Grenoble, France DOI: 10.1109/ICMTS.1995.513948 HOVER FOR ABSTRACT | PDF Xplore | |
| Accurate capacitor matching measurements using floating gate test structures H. P. Tuinhout, H. Elzinga1, J. T. Brugman2, F. Postma2 Philips Research, Philips Electronics N.V., Eindhoven, Netherlands 1Philips Semiconductors, Philips Electronics N.V., France 2Philips Semiconductors, Philips Electronics N.V., Nijmegen, Netherlands DOI: 10.1109/ICMTS.1995.513960 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization and modeling of transistors embedded in a high performance bipolar logic array E. H. Tyler Applied Micro Circuits Corporation, San Diego, CA, USA DOI: 10.1109/ICMTS.1995.513969 HOVER FOR ABSTRACT | PDF Xplore | |
| Wafer mapping using DOE and RSM techniques A. J. Walton, M. Fallon, D. Wilson1 Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK 1Motorola Limited, Glasgow, UK DOI: 10.1109/ICMTS.1995.513989 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization and modeling of MOS mismatch in analog CMOS technology Shyh-Chyi Wong, Jyh-Kang Ting, Shun-Liang Hsu Technology Development Division, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.1995.513967 HOVER FOR ABSTRACT | PDF Xplore | |
| An automatic implementation of dynamic electromigration tests Wei Zhang, Y. H. Cheng, Z. G. Li, W. L. Guo, Y. H. Sun, X. X. Li Electronic Engineering Department Reliability Physics La, Beijing Polytechnic University, Beijing, China DOI: 10.1109/ICMTS.1995.513980 HOVER FOR ABSTRACT | PDF Xplore |
