ICMTS 2024 Program

2024 Program Booklet

By Session

Bonus Talks

B1

How to write excellent papers C. Cagli STMicroelectronics, Crolles, France

Session 1: Layout Dependent Effects

1.1	Layout Dependent Effects Of Passive Devices And Their Impact On Analog Integrated Circuits A. Jayakumar, M. van Dort, M. Vertregt, G. D. J. Smit, R. Lander, I. Liu, P. Volf NXP Semiconductors B.V, Nijmegen, Netherlands DOI: 10.1109/ICMTS59902.2024.10520688 ABSTRACT: Analog blocks on products built using advanced CMOS technologies were seen to have deviating behavior on silicon than estimated by post layout simulations, especially in circuits used for biasing and reference generation. Circuit investigations pointed towards trimming resistor banks used for bias and reference current derivation. To detect possible unmodelled silicon effects experienced by these trimming resistor banks which have different configurations in the various analog blocks on products, a scribe-line test structure was implemented, aimed to capture major product design use-cases and study their effects. The outcome of this study is presented in this paper.	PDF Xplore
1.2	Test Structures for studying the impact of the backend contact metallization on the performance and stress sensitivity of SiGe HBTs O. Dieball, H. Tuinhout, J. Zaal1 Modeling, NXP Semiconductors, Eindhoven, The Netherlands 1Package Innovation, NXP Semiconductors, Nijmegen, The Netherlands DOI: 10.1109/ICMTS59902.2024.10520678 ABSTRACT: Based on a collection of layout realizations of a simplified SiGe HBT test structure, this paper addresses the impact of mechanical stress induced by the backend metallization placed above the base, emitter and collector regions on the electrical performance of these HBTs. Subsequently, the temperature dependencies of the collector currents and their sensitivity to externally applied mechanical stress is investigated. This study provides valuable insights into test structure layout-related performance shifts relevant for layout and design of modelling test structures and high-precision circuit design.	PDF Xplore
1.3	A Step-by-Step Layout Transformation Approach to Differentiate How Multiple Layout Dependent Effects Modify Device and Circuit Performance L. Lu, K. Xia1, R. van Langevelde, C. C. McAndrew, W. Li Front End Innovation, NXP Semiconductors 1Power Management Business Development, TSMC DOI: 10.1109/ICMTS59902.2024.10520696 ABSTRACT: Ring oscillators (ROs) are important components of electronic circuits. Their performance, however, is susceptible to parasitic effects when device sizes scale down. We present a methodology, that uses a series of test structures which step-by-step transform an RO layout into single-device modeling layouts, to differentiate and quantify the impact of individual layout dependent effects on device DC performance. A model that is tuned to fit the DC characteristics of the devices in an RO, which are subject to multiple LDEs, gives correct timing behavior.	PDF Xplore

Session 2:

2.3	A 4H-SiC Trench MOS Capacitor Structure for Sidewall Oxide Characteristics Measurement H. -L. Huang, L. -T. Hsuesh, Y. -C. Tu, B. -Y. Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS59902.2024.10520701 ABSTRACT: Test structure for evaluating gate oxide properties on the trench sidewall in 4H-SiC is proposed. Using the thick bottom oxide and poly-Silicon spacer structure, we are able to measure the capacitance characteristics directly and extract the interface state density. It is observed that typical NO annealing process cannot passivate the trench etching induced defects effectively.	PDF Xplore
2.2	Test Structures of Cross-Domain Interface Circuits with Deep N-Well Layout to Improve CDM ESD Robustness H. -M. Huang, M. -D. Ker Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520690 ABSTRACT: Charged-device model (CDM) electrostatic discharge (ESD) event is a complex reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, various circuit blocks have been integrated into a single chip. In order to avoid noise coupling between circuit blocks or even to reduce power consumption, the SoC chip was often equipped with separated power domains for different circuit blocks. However, the cross-domain interface circuits between different power domains are particularly susceptible to gate-oxide rupture caused by CDM ESD during cross-domain ESD events. In this study, CDM ESD robustness of cross-domain interface circuits with deep N-well (DNW) was investigated through test structures fabricated in a 0.18-μm CMOS technology.	PDF Xplore
2.1	A novel test structure with two active areas for eNVM reliability studies K. Alkema, F. Melul, V. D. Marca1, M. Bocquet1, M. Akbal, A. Regnier, S. Niel2, F. La-Rosa STMicroelectronics Rousset, France 1CNRS, IM2NP UMR 7334, Aix-Marseille University, Marseille, France 2STMicroelectronics Crolles, France DOI: 10.1109/ICMTS59902.2024.10520674 ABSTRACT: This paper presents a test structure with a poly floating gate shared on two actives areas. Programming and erase can be split toward these two regions with a specific arsenic implantation. The aim is to study the tunnel oxide degradation and the injection efficiency of embedded charge storage memory cells.	PDF Xplore

Session 3:

3.3	A Testbed for Cryogenic On-wafer Noise Measurement Using Cold Source Method with Temperature-Dependent Loss Correction G. -W. Huang, B. -Y. Chen, Y. -S. Shiao, C. -W. Chuang, L. -C. Shen, K. -M. Chen, C. -S. Chiu Taiwan Semiconductor Research Institute, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS59902.2024.10520691 ABSTRACT: On-wafer noise measurement at cryogenic temperature is challenging due to complexity of temperature gradient distributions in cryostats. As Keysight Technologies introduce their on-wafer cold source method for stable noise temperature measurement at room temperature, we propose our correct formulas as loss correction to exploit the method to work properly for cryogenic noise temperature measurement, especially as a good fit for those which involve a large number of samples, e.g., Known-Good-Die testing. In this paper, we demonstrate the feasibility of the correction with 16nm, 65nm CMOS, and two InP pHEMT transistors at 4-14GHz. The correction significantly compensates the underestimated noise temperatures by more than 20K. As the results, we suggest that the correction is convenient and more accurate while using the cold source method for cryogenic on-wafer noise temperature measurement.	PDF Xplore
3.2	Gaussian process-based device model toward a unified current model across room to cryogenic temperatures M. Shintani, T. Iwasaki, T. Sato1 Graduate School of Science and Technology, Kyoto Institute of Technology Matsugasaki, Sakyo-ku, Kyoto, Japan 1Graduate School of Informatics, Kyoto University Yoshida-Hon-Machi, Sakyo-ku, Kyoto, Japan DOI: 10.1109/ICMTS59902.2024.10520702 ABSTRACT: While the typical temperature range supported by standard MOSFET models is from -55 to 125 ºC, recent emerging applications require to operate at a wider temperature range, particularly towards lower temperatures. To address these demands, we apply the sparse Gaussian process to build a unified and compact device model for simulating CMOS circuits operating from room to cryogenic temperatures. Unlike neural networks, the sparse Gaussian process prevents overfitting issues. The evaluation of nMOS and pMOS transistors with various dimensions fabricated using a 65 nm node demonstrates that the I-V characteristics are efficiently and accurately modeled from 4 K to 300 K.	PDF Xplore
3.1	Transistor Matrix Array for Measuring Variability and Random Telegraph Noise at Cryogenic Temperatures T. Mizutani, K. Takeuchi, T. Saraya, H. Oka1, T. Mori1, M. Kobayashi, T. Hiramoro Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 1National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan DOI: 10.1109/ICMTS59902.2024.10520700 ABSTRACT: Addressable transistor arrays using 65 nm bulk technology were fabricated and tested at cryogenic temperatures. It was confirmed that variability at 1.5 K slightly degrades compared with 300 K. Random telegraph noise (RTN) was also measured and existence of extremely slow RTN at 1.5 K was confirmed using a quasi-parallel measurement technique. Such test structures will be particularly useful for enhancing cryogenic measurement efficiency.	PDF Xplore

Session 4: Dielectrics and Ferroelectrics

4.1	Analysis and Compensation of the Series Resistance Effects on the Characteristics of Ferroelectric Capacitors M. Massarotto, F. Driussi, M. Bucovaz, A. Affanni, S. Lancaster1, S. Slesazeck1, T. Mikolajick1, D. Esseni DPIA, University of Udine, Udine, Italy 1NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS59902.2024.10520684 ABSTRACT: The energy efficiency of ferroelectric-based devices makes them interesting for many applications. However, their optimization requires a dependable characterization of the ferroelectric (FE) material. In this work, we show and investigate how the series resistance (RS) can strongly impact the current-voltage (I-V) characteristics of Metal-Ferroelectric-Metal (MFM) stacks and distorts the hysteresis curves, which can lead to an inaccurate extraction of the FE parameters and a misleading interpretation of FE switching dynamics. The complex RS effect on the I-V curves cannot be easily compensated, so here we propose, for the first time to our knowledge, a procedure for an improved extraction of the FE parameters even in the presence of a non-negligible series resistance.	PDF Xplore
4.2	Impedance Measurement Platform for Statistical Capacitance and Current Characteristic Measurements of Arrayed Cells with Atto-order Precision K. Saito, T. Suzuki, H. Mitsuda, T. Nozaki, T. Mawaki, R. Kuroda Graduate School of Engineering, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS59902.2024.10520692 ABSTRACT: A novel impedance measurement platform that enables high-precision statistical measurements of C-V and I-V characteristics is presented. The platform consists of 366<sup>H</sup> x 228<sup>V</sup> cell array and a common readout circuit. The pre-formed device under test (DUT) cells of metal-oxide-silicon field-effect-transistors (MOSFETs) and metal-insulator-metal (MIM) capacitors were measured to verify its measurement performance. The results demonstrated that for about 5,000 DUTs, fF-order capacitance with 0.05 % precision and fA-order current with 0.46 % precision were achieved by C-V and I-V measurements, respectively.	PDF Xplore
4.3	Compact expression to model the effects of dielectric absorption on analog-to-digital converters S. Saro, P. Palestri1, E. Caruso2, P. Toniutti2, R. Calabro2, S. Terokhin2, F. Driussi DPIA, University of Udine, Italy 1University of Modena and Reggio, Emilia, Italy 2Infineon Technologies Austria, Villach, Austria DOI: 10.1109/ICMTS59902.2024.10520681 ABSTRACT: An analytical model for the dielectric absorption on capacitors and its impact on the errors induced in ADC conversion is here proposed. The reported simulations are consistent with the results of the R-C model widely used in the literature and well reproduce a large set of capacitance versus frequency and current versus time experiments. We also measured ADC conversion errors due to the dielectric absorption and we demonstrated that such errors can be reproduced by our model just calibrating one single technology parameter.	PDF Xplore

Session 5:

5.2	Droplet Impact Sensing with Low Noise Coplanar Reverse-Electrowetting Test Structures A. Moyo, M. W. Shahzad, S. Smith1, J. Terry1, Y. Mita2, J. Lewis, Y. Li Department of Mechanical and Construction Engineering, Faculty of Engineering and Environment, Northumbria University, Newcastle Upon Tyne, UK 1Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, Edinburgh, UK 2Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS59902.2024.10520253 ABSTRACT: This paper examines the intricate dynamics of droplet impact on coplanar reverse electrowetting systems (CREW), specifically exploring how the electrode ratio and bias voltage interact to affect voltage generation. Employing a systematic experimental approach, we varied the electrode ratio and bias voltage to analyze their effects on the generated voltage during droplet impact. Our findings reveal significant dependencies between these parameters and the voltage output, shedding light on the underlying mechanisms governing energy harvesting efficiency in CREW systems. This research can inform better design strategies for improving energy conversion efficiency in various applications.	PDF Xplore
5.4	Parametric Optimization of RF MEMS Variable Capacitor with High Linearity for C-Band Applications S. Shaheen, P. Lomax, T. Arslan Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520682 ABSTRACT: A novel RF Microelectromechanical System (MEMS) Variable capacitor is proposed to obtain a linear capacitance-voltage response and large tuning ratio. Rectangular electrostatic torsion actuators are connected to each end of the central capacitor plate by using actuator beams. When voltage is provided in the actuator section, the actuator beam assists in providing steady movement of the central plate in an upward direction. Structural optimization of the RF MEMS Varactor is performed from the perspective of capacitance-voltage response by using ANSYS. The research provides a notable dual contribution that includes both substantial tunability and high linearity. It demonstrates a high capacitance tuning ratio of 312% and a 99% linearity factor in the C-V response, indicating a high linearity factor. The optimized design is demonstrated on a 50-ohm coplanar transmission line to obtain S-parameters by using HFSS. Characteristics of RF performance are analyzed by comparing SiO2 with Si3N4 as the dielectric material in this design. At 4.2 GHz, the varactor with Si3N4 shows -50.2 dB isolation, while the varactor with SiO2 shows -48.2 dB isolation at 5.5 GHz. The proposed study shows that the optimized RF MEMS Varactor shows better performance using Si3N4 at lower frequencies, which makes it appropriate for C-Band applications.	PDF Xplore
5.1	Test structure for chemiluminescence measurement in aqueous solutions: initial design A. A. Moreno-Guerrero, C. Dunare, A. J. Walton, P. Lomax, J. G. Terry, I. Underwood School of Engineering, The University of Edinburgh, United Kingdom DOI: 10.1109/ICMTS59902.2024.10520697 ABSTRACT: There is an unmet need for on-chip integration of sensitive chemiluminescence sensors due to their extensive use in chemical analysis. This manuscript introduces a novel test structure for ease of opto-electrical integration in microfluidic systems. The MOS-based structure functions as an optical sensor for Luminol-based analysis and validates the suitability of the semiconductor fabrication process.	PDF Xplore
5.3	Analysis methodology of Deep Trench Isolation Field-Effect Passivation techniques for Image Sensors through dedicated test structures S. Tlemsani, S. Ricq, O. Marcelot1, P. Magnan1 STMicroelectronics, Crolles, France 1Institut Supérieur de l'Aéronautique et de l'Espace (ISAE), Toulouse, France DOI: 10.1109/ICMTS59902.2024.10520689 ABSTRACT: Passivation techniques are mandatory to reduce the CMOS Image Sensors dark current from interfaces. In this work a general analysis methodology is proposed to study the Deep Trench Isolation field-effect passivation thanks to dedicated test structures. Two deep trench isolations are characterized: an electrically active trench and an innovative passive trench using charged Al2O3/SiO2 stacks. The results, validated by TCAD simulations, show that the best passivation is achieved here with the passive trench. Beyond, our approach is demonstrated to be a powerful tool for technologies and pixels developments with a fair passivation efficiency comparison through accumulation or inversion layer carrier concentrations. This work is also a first step toward dark current contribution modeling.	PDF Xplore

Session 6: Wafer Measurements

6.1	Efficient Characterization Methodology for Low-Frequency Noise Monitoring L. Pirro, T. Chohan, P. Liebscher, M. Juettner, F. Holzmueller, R. Jain, Y. Raffel1, K. Seidel1, R. R. Olivo1, A. Zaka, J. Hoentschel GlobalFoundries Fab1 LLC & Co.KG, Dresden, Saxony, Germany 1Fraunhofer-IPMS, Dresden, Saxony, Germany DOI: 10.1109/ICMTS59902.2024.10520698 ABSTRACT: In this work, a novel methodology to characterize the Low-Frequency Noise LFN on large device statistics and suitable for production monitoring is proposed. The maximum drain current fluctuations over time are measured. The slope of the LFN distribution is modeled with physical equations related to the basic device properties. The approach is validated by studying the impact of transistor geometry (different gate width, number of fingers and gate length) as well as gate oxide thickness and characterization temperature. In conclusion, the proposed methodology is tested evaluating different process integration elements. The outcome is compared to classical LFN read-out for final confirmation.	PDF Xplore
6.2	Rapid MOSFET threshold voltage testing for high throughput semiconductor process monitoring M. H. Herman, T. T. Nguyen, K. Wong, J. Johnson, B. Morris Parametric Test Group, Advantest America, San Jose, United States DOI: 10.1109/ICMTS59902.2024.10520252 ABSTRACT: We describe a method for rapid MOSFET threshold voltage (Vt) measurement. Multiple spot Ids measurements are compared to stored reference data. Each spot measurement yields an independent Vt estimate, and these enable quality metric calculation. A Vt and quality metric can be measured within 7 msec, using two spot measurements. The method permits parallel MOS testing.	PDF Xplore
6.3	Statistical investigation of SnOx RRAM memories for switching characteristics A. Panca, A. Serb, S. Stathopoulos, T. Prodromakis Institute for Integrated Micro and Nano Systems, University of Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520675 ABSTRACT: Resistive Random Access Memory (RRAM) has seen significant developments in the past years. An important improvement is to reduce the device-to-device variability that limits RRAM implementation. A proposed approach is to measure a high number of devices to statistically identify trends and evidences behind the cause. Here, we present a method to characterise the RRAM switching behaviour and analyse a large dataset of SnOx RRAM, in a statistical fashion for further optimisation and modelling.	PDF Xplore
6.4	Making Accurate and Consistent Wafer Measurements with Next Generation Guarded True-Kelvin MEMS DC Probes C. B. Sia, Y. Funatoko, I. Kunioka, M. Watanabe, P. Andrews, K. Dawson, M. Sameshima, T. Saeki, J. Yang, J. Li, X. Li, S. Guo, L. Fan, W. M. Lim, E. Wilcox, A. Lord, S. Lastella, N. Kawamata, J. Klattenhoff, J. Kister, M. Losey, M. Slessor FormFactor Inc., Singapore DOI: 10.1109/ICMTS59902.2024.10520687 ABSTRACT: Gate length down-scaling of silicon-based transistor results in very small on-state drain-source resistance, making it challenging for test engineers to perform precise and repeatable wafer measurements. Size reduction of aluminum-capped copper test pads to save on lithography, prototyping and production costs implies that it is very difficult to re-probe the same device with low contact resistance. Novel true-Kelvin MEMS analytical DC probes, new test and modelling strategies are proposed in this paper to address these emerging test challenges.	PDF Xplore

Session 7: S-Parameters and De-embedding

7.1	Understanding the Substrate Effect on De-embedding Structures Fabricated on SOI Wafers Using Electromagnetic Simulation B. N. Wesling, M. Deng1, C. Mukherjee1, T. Mikolajick, J. Trommer, C. Maneux1 NaMLab gGmbH, Dresden, Germany 1IMS, Talence Cedex, France DOI: 10.1109/ICMTS59902.2024.10520694 ABSTRACT: In this paper, we present the fabrication, characterization, and electromagnetic simulation of open pad test structures on silicon-on-insulator substrates, with an emphasis on the impact of the substrate properties on RF performance. Targeting the design of optimal RF test structures for emerging technologies, we demonstrated that a high-resistivity substrate is essential to minimize losses and parasitic capacitances in RF measurements for technologies using silicon-on-insulator wafers.	PDF Xplore
7.2	Modified Bisection Thru-Only Deembedding Algorithm for Long Test Fixtures A. Quint, L. Valenziano, J. Hebeler, T. Zwick, A. Bhutani Institute of Radio Frequency Engineering and Electronics, Karlsruhe Institute of Technology, Karlsruhe, Germany DOI: 10.1109/ICMTS59902.2024.10520703 ABSTRACT: Thru-only deembedding is a simple deembedding method using a single deembedding structure. Common thru-only deembedding methods often have overshoots in the deembedded S-parameters when the deembedding structure is λ/2 long. This is caused in the bisection step. A modified approach is presented, which extracts the phase of the S-parameters of the deembedding structure before the bisection step, performs the bisection on the magnitude of the S-parameters and applies the phase afterwards again, therefore eliminating the overshoots. The accuracy of the proposed algorithm is verified on measured test structures.	PDF Xplore
7.3	Evaluation of Lab-based Lithium Niobate Surface Acoustic Wave Test Structure Using Efficient Maskless Lithography and SMA Connection Approach for Microfluidic Applications M. S. Parvez, S. Hussain, M. Goeckner, C. D. Young, J. -B. J. Lee1 The University of Texas at Dallas, Richardson, TX, USA 1Baylor University, Waco, TX DOI: 10.1109/ICMTS59902.2024.10520693 ABSTRACT: Surface Acoustic Wave (SAW) devices, particularly those made of Lithium Niobate (LiNbO3), are extensively used in telecommunications and microfluidic applications. This work describes the fabrication of a LiNbO3-based SAW test structures using maskless photolithography for rapid device dimension changes as well as introduces a cost-effective technique to solder Sub-Miniature version A (SMA) connectors to delicate substrates such as LiNbO3-based SAWs, without the need to fully create printed circuit boards. The SMA connected device facilitated improved characterization results compared to simple copper tape connections. The characterization accuracy is then validated through simulation.	PDF Xplore

Session 8:

8.3	A Neural Network-based Manufacturing Variability Modeling of GaN HEMTs F. Chavez, D. Bavi, N. C. Miller1, S. Khandelwal School of Engineering, Macquarie University, Australia 1Department of Electrical and Computer Engineering, Michigan State University, USA DOI: 10.1109/ICMTS59902.2024.10520695 ABSTRACT: A new technique to accurately model the manufacturing variability of GaN HEMT using a neural network(NN) is presented in this paper. Compact model parameters are automatically generated through Principal component analysis (PCA) parameters from variations in I-V data. Together with the bias conditions, the compact model parameters are used to train a neural network. The NN-based compact model captures the I-V behavior of 115 GaN HEMT with excellent accuracy. The trained neural network is converted to a standard Verilog-A file that can be imported to a circuit simulator. The NN-based compact model is further evaluated in terms of complexity and simulation speed. The presented technique shows great potential in developing a fast, flexible, and accurate NN-based compact model that can be applied to any device technology.	PDF Xplore
8.2	Method for Suppressing Trap-Related Memory Effects in IV Characterizations of GaN HEMTs J. Bremer, N. Rorsman, M. Thorsell Microwave Electronics Laboratory, Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS59902.2024.10520686 ABSTRACT: A method to suppress trapping-related effects when performing IV characterizations of field effect transistors is presented. Standard IV measurements usually utilize voltage sweeps with fixed start, stop, and step values. At high electric fields in these sweeps, the charging of electron traps with long time constants may occur. The trapped electrons cause different memory effects such as hysteresis and the kink effect. The proposed method suppresses these effects, by reordering the bias points, so to prevent charging due to high preceding electric fields. The method provides more rudimentary IV measurements, useful for e.g. technology evaluation and modeling purposes.	PDF Xplore
8.1	Test Structures to Investigate ESD Robustness of Integrated GaN Devices W. -C. Wang, M. -D. Ker Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520680 ABSTRACT: When more circuit functions are integrated into a single chip fabricated by GaN-on-Silicon process, the on-chip electrostatic discharge (ESD) protection design shall be provided to protect the GaN integrated circuits. In this work, ESD robustness of E-HEMT GaN devices was investigated through test structures that fabricated in a GaN-on-Silicon process. The experimental results showed that the ESD robustness is proportional to the device dimension when the GaN device was operating in the forward mode. In addition, with the gate-coupled design, the ESD level of E-HEMT GaN device can be further improved. Based on the investigation results of this work, the whole-chip ESD protection scheme can be successfully realized by E-HEMT GaN devices.	PDF Xplore
8.4	Use of DC Probes for Multi-MHz Measurements of Crosstalk and Substrate Coupling in Gallium Nitride Power Integrated Circuits M. Cui, S. Lam Department of Electrical and Electronic Engineering, Xi’an Jiaotong-Liverpool University, Suzhou, China DOI: 10.1109/ICMTS59902.2024.10520677 ABSTRACT: With simple compact pads, DC probes were used for measurements of crosstalk and substrate coupling in gallium-nitride (GaN) power integrated circuits (ICs). By proper electrical measurement calibration of the DC probing system, a crosstalk voltage down to 4.4 mV and substrate coupling up to -38 dB were measured up to 25 MHz for a GaN-on-Si power IC, using an oscilloscope and a spectrum analyzer respectively. Despite some accuracy limitations, it is a low-cost viable method for determining especially substrate coupling in power ICs.	PDF Xplore

Session 9:

9.3	Test Structure to Assess Bump Shape Influence on Hybrid Bonding A. Mizushima, K. Misumi, S. Yasunaga, A. Higo, R. Nakane, K. Tsumura1, K. Higashi1, Y. Ochiai, Y. Mita Graduate School of Engineering, The University of Tokyo, Tokyo, Japan 1Toshiba Corporation, Kawasaki, Japan DOI: 10.1109/ICMTS59902.2024.10520685 ABSTRACT: Bump bonding is widely used in CMOS-MEMS integration. As compared to the other technology (planar bonding), bump bonding is more interesting for its simplicity and applicability to wide range of device types. Towards higher density and reliability improvement, the authors have designed and fabricated a test structure. Our new contribution is to intentionally structuralize shapes of bumps to not only a flat head but concave as well as convex ones, expecting better occlusion and passive alignment. To experiment our new idea, the first test structure has been fabricated to assess alignment accuracy.	PDF Xplore
9.2	Electrical behavior of ALD-molybdenum films in the thin-film limit K. van der Zouw, S. D. Dulfer, A. A. I. Aarnink, A. Y. Kovalgin MESA+ Institute for Nanotechnology, University of Twente, AE Enschede, The Netherlands DOI: 10.1109/ICMTS59902.2024.10520676 ABSTRACT: Test structures were designed and fabricated to investigate the electrical properties of ultra-thin molybdenum films obtained by atomic layer deposition. The films were incorporated in conventional Van der Pauw and circular transmission line method test structures to explore the effect of film thickness on the resistivity, temperature coefficient of resistance, contact resistivity, and external electric field applied. The resistivity was shown to depend strongly on film thickness, while the temperature coefficient of resistance changed from positive to negative, indicating a change in the dominant conduction mechanism. A modest field effect was observed for the films in their thickness limit.	PDF Xplore
9.1	An Add-in Test Structure Chip to Unitedly Assess PVD Material Properties in University Open Nanotechnology Platform S. Yasunaga, K. Misumi, A. Mizushima, A. Toyokura, E. Ota, Y. Inoue, M. Fujiwara, N. Kawai, M. Yoda, S. Tsuboi, T. Sawamura, A. Higo, R. Nakane, Y. Ochiai, Y. Mita Department of Electrical Engineering, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS59902.2024.10520699 ABSTRACT: Open nanotechnology platforms at universities and research institutes are becoming essential for agile and rapid microelectronic device research and development. To further extend its capability with more users, process data acquisition and digital transformation is of high priority. In order to uniformly acquire process data in an open platform, where users' process charts are all different, we propose a "chamber sharing system", in which a small test chip designed for easily measuring necessary parameters is loaded in the process chamber together with user's sample, which will be submitted to the platform. As the first realization of such a test chip, we designed and fabricated an 8x8 mm<sup>2</sup> chip for physical vapor deposition, enabling the film's thickness, stress, and conductivity measurement. With easy preparation requiring no cleanroom environment, results compatible with previously reported values were obtained.	PDF Xplore

By First Author

2.1	A novel test structure with two active areas for eNVM reliability studies K. Alkema, F. Melul, V. D. Marca1, M. Bocquet1, M. Akbal, A. Regnier, S. Niel2, F. La-Rosa STMicroelectronics Rousset, France 1CNRS, IM2NP UMR 7334, Aix-Marseille University, Marseille, France 2STMicroelectronics Crolles, France DOI: 10.1109/ICMTS59902.2024.10520674 HOVER FOR ABSTRACT	PDF Xplore
8.2	Method for Suppressing Trap-Related Memory Effects in IV Characterizations of GaN HEMTs J. Bremer, N. Rorsman, M. Thorsell Microwave Electronics Laboratory, Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS59902.2024.10520686 HOVER FOR ABSTRACT	PDF Xplore
B1	How to write excellent papers C. Cagli STMicroelectronics, Crolles, France HOVER FOR ABSTRACT
8.3	A Neural Network-based Manufacturing Variability Modeling of GaN HEMTs F. Chavez, D. Bavi, N. C. Miller1, S. Khandelwal School of Engineering, Macquarie University, Australia 1Department of Electrical and Computer Engineering, Michigan State University, USA DOI: 10.1109/ICMTS59902.2024.10520695 HOVER FOR ABSTRACT	PDF Xplore
8.4	Use of DC Probes for Multi-MHz Measurements of Crosstalk and Substrate Coupling in Gallium Nitride Power Integrated Circuits M. Cui, S. Lam Department of Electrical and Electronic Engineering, Xi’an Jiaotong-Liverpool University, Suzhou, China DOI: 10.1109/ICMTS59902.2024.10520677 HOVER FOR ABSTRACT	PDF Xplore
1.2	Test Structures for studying the impact of the backend contact metallization on the performance and stress sensitivity of SiGe HBTs O. Dieball, H. Tuinhout, J. Zaal1 Modeling, NXP Semiconductors, Eindhoven, The Netherlands 1Package Innovation, NXP Semiconductors, Nijmegen, The Netherlands DOI: 10.1109/ICMTS59902.2024.10520678 HOVER FOR ABSTRACT	PDF Xplore
6.2	Rapid MOSFET threshold voltage testing for high throughput semiconductor process monitoring M. H. Herman, T. T. Nguyen, K. Wong, J. Johnson, B. Morris Parametric Test Group, Advantest America, San Jose, United States DOI: 10.1109/ICMTS59902.2024.10520252 HOVER FOR ABSTRACT	PDF Xplore
2.3	A 4H-SiC Trench MOS Capacitor Structure for Sidewall Oxide Characteristics Measurement H. -L. Huang, L. -T. Hsuesh, Y. -C. Tu, B. -Y. Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS59902.2024.10520701 HOVER FOR ABSTRACT	PDF Xplore
3.3	A Testbed for Cryogenic On-wafer Noise Measurement Using Cold Source Method with Temperature-Dependent Loss Correction G. -W. Huang, B. -Y. Chen, Y. -S. Shiao, C. -W. Chuang, L. -C. Shen, K. -M. Chen, C. -S. Chiu Taiwan Semiconductor Research Institute, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS59902.2024.10520691 HOVER FOR ABSTRACT	PDF Xplore
2.2	Test Structures of Cross-Domain Interface Circuits with Deep N-Well Layout to Improve CDM ESD Robustness H. -M. Huang, M. -D. Ker Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520690 HOVER FOR ABSTRACT	PDF Xplore
1.1	Layout Dependent Effects Of Passive Devices And Their Impact On Analog Integrated Circuits A. Jayakumar, M. van Dort, M. Vertregt, G. D. J. Smit, R. Lander, I. Liu, P. Volf NXP Semiconductors B.V, Nijmegen, Netherlands DOI: 10.1109/ICMTS59902.2024.10520688 HOVER FOR ABSTRACT	PDF Xplore
1.3	A Step-by-Step Layout Transformation Approach to Differentiate How Multiple Layout Dependent Effects Modify Device and Circuit Performance L. Lu, K. Xia1, R. van Langevelde, C. C. McAndrew, W. Li Front End Innovation, NXP Semiconductors 1Power Management Business Development, TSMC DOI: 10.1109/ICMTS59902.2024.10520696 HOVER FOR ABSTRACT	PDF Xplore
4.1	Analysis and Compensation of the Series Resistance Effects on the Characteristics of Ferroelectric Capacitors M. Massarotto, F. Driussi, M. Bucovaz, A. Affanni, S. Lancaster1, S. Slesazeck1, T. Mikolajick1, D. Esseni DPIA, University of Udine, Udine, Italy 1NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS59902.2024.10520684 HOVER FOR ABSTRACT	PDF Xplore
9.3	Test Structure to Assess Bump Shape Influence on Hybrid Bonding A. Mizushima, K. Misumi, S. Yasunaga, A. Higo, R. Nakane, K. Tsumura1, K. Higashi1, Y. Ochiai, Y. Mita Graduate School of Engineering, The University of Tokyo, Tokyo, Japan 1Toshiba Corporation, Kawasaki, Japan DOI: 10.1109/ICMTS59902.2024.10520685 HOVER FOR ABSTRACT	PDF Xplore
3.1	Transistor Matrix Array for Measuring Variability and Random Telegraph Noise at Cryogenic Temperatures T. Mizutani, K. Takeuchi, T. Saraya, H. Oka1, T. Mori1, M. Kobayashi, T. Hiramoro Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 1National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan DOI: 10.1109/ICMTS59902.2024.10520700 HOVER FOR ABSTRACT	PDF Xplore
5.1	Test structure for chemiluminescence measurement in aqueous solutions: initial design A. A. Moreno-Guerrero, C. Dunare, A. J. Walton, P. Lomax, J. G. Terry, I. Underwood School of Engineering, The University of Edinburgh, United Kingdom DOI: 10.1109/ICMTS59902.2024.10520697 HOVER FOR ABSTRACT	PDF Xplore
5.2	Droplet Impact Sensing with Low Noise Coplanar Reverse-Electrowetting Test Structures A. Moyo, M. W. Shahzad, S. Smith1, J. Terry1, Y. Mita2, J. Lewis, Y. Li Department of Mechanical and Construction Engineering, Faculty of Engineering and Environment, Northumbria University, Newcastle Upon Tyne, UK 1Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, Edinburgh, UK 2Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS59902.2024.10520253 HOVER FOR ABSTRACT	PDF Xplore
6.3	Statistical investigation of SnOx RRAM memories for switching characteristics A. Panca, A. Serb, S. Stathopoulos, T. Prodromakis Institute for Integrated Micro and Nano Systems, University of Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520675 HOVER FOR ABSTRACT	PDF Xplore
7.3	Evaluation of Lab-based Lithium Niobate Surface Acoustic Wave Test Structure Using Efficient Maskless Lithography and SMA Connection Approach for Microfluidic Applications M. S. Parvez, S. Hussain, M. Goeckner, C. D. Young, J. -B. J. Lee1 The University of Texas at Dallas, Richardson, TX, USA 1Baylor University, Waco, TX DOI: 10.1109/ICMTS59902.2024.10520693 HOVER FOR ABSTRACT	PDF Xplore
6.1	Efficient Characterization Methodology for Low-Frequency Noise Monitoring L. Pirro, T. Chohan, P. Liebscher, M. Juettner, F. Holzmueller, R. Jain, Y. Raffel1, K. Seidel1, R. R. Olivo1, A. Zaka, J. Hoentschel GlobalFoundries Fab1 LLC & Co.KG, Dresden, Saxony, Germany 1Fraunhofer-IPMS, Dresden, Saxony, Germany DOI: 10.1109/ICMTS59902.2024.10520698 HOVER FOR ABSTRACT	PDF Xplore
7.2	Modified Bisection Thru-Only Deembedding Algorithm for Long Test Fixtures A. Quint, L. Valenziano, J. Hebeler, T. Zwick, A. Bhutani Institute of Radio Frequency Engineering and Electronics, Karlsruhe Institute of Technology, Karlsruhe, Germany DOI: 10.1109/ICMTS59902.2024.10520703 HOVER FOR ABSTRACT	PDF Xplore
4.2	Impedance Measurement Platform for Statistical Capacitance and Current Characteristic Measurements of Arrayed Cells with Atto-order Precision K. Saito, T. Suzuki, H. Mitsuda, T. Nozaki, T. Mawaki, R. Kuroda Graduate School of Engineering, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS59902.2024.10520692 HOVER FOR ABSTRACT	PDF Xplore
4.3	Compact expression to model the effects of dielectric absorption on analog-to-digital converters S. Saro, P. Palestri1, E. Caruso2, P. Toniutti2, R. Calabro2, S. Terokhin2, F. Driussi DPIA, University of Udine, Italy 1University of Modena and Reggio, Emilia, Italy 2Infineon Technologies Austria, Villach, Austria DOI: 10.1109/ICMTS59902.2024.10520681 HOVER FOR ABSTRACT	PDF Xplore
5.4	Parametric Optimization of RF MEMS Variable Capacitor with High Linearity for C-Band Applications S. Shaheen, P. Lomax, T. Arslan Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520682 HOVER FOR ABSTRACT	PDF Xplore
3.2	Gaussian process-based device model toward a unified current model across room to cryogenic temperatures M. Shintani, T. Iwasaki, T. Sato1 Graduate School of Science and Technology, Kyoto Institute of Technology Matsugasaki, Sakyo-ku, Kyoto, Japan 1Graduate School of Informatics, Kyoto University Yoshida-Hon-Machi, Sakyo-ku, Kyoto, Japan DOI: 10.1109/ICMTS59902.2024.10520702 HOVER FOR ABSTRACT	PDF Xplore
6.4	Making Accurate and Consistent Wafer Measurements with Next Generation Guarded True-Kelvin MEMS DC Probes C. B. Sia, Y. Funatoko, I. Kunioka, M. Watanabe, P. Andrews, K. Dawson, M. Sameshima, T. Saeki, J. Yang, J. Li, X. Li, S. Guo, L. Fan, W. M. Lim, E. Wilcox, A. Lord, S. Lastella, N. Kawamata, J. Klattenhoff, J. Kister, M. Losey, M. Slessor FormFactor Inc., Singapore DOI: 10.1109/ICMTS59902.2024.10520687 HOVER FOR ABSTRACT	PDF Xplore
5.3	Analysis methodology of Deep Trench Isolation Field-Effect Passivation techniques for Image Sensors through dedicated test structures S. Tlemsani, S. Ricq, O. Marcelot1, P. Magnan1 STMicroelectronics, Crolles, France 1Institut Supérieur de l'Aéronautique et de l'Espace (ISAE), Toulouse, France DOI: 10.1109/ICMTS59902.2024.10520689 HOVER FOR ABSTRACT	PDF Xplore
8.1	Test Structures to Investigate ESD Robustness of Integrated GaN Devices W. -C. Wang, M. -D. Ker Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520680 HOVER FOR ABSTRACT	PDF Xplore
7.1	Understanding the Substrate Effect on De-embedding Structures Fabricated on SOI Wafers Using Electromagnetic Simulation B. N. Wesling, M. Deng1, C. Mukherjee1, T. Mikolajick, J. Trommer, C. Maneux1 NaMLab gGmbH, Dresden, Germany 1IMS, Talence Cedex, France DOI: 10.1109/ICMTS59902.2024.10520694 HOVER FOR ABSTRACT	PDF Xplore
9.1	An Add-in Test Structure Chip to Unitedly Assess PVD Material Properties in University Open Nanotechnology Platform S. Yasunaga, K. Misumi, A. Mizushima, A. Toyokura, E. Ota, Y. Inoue, M. Fujiwara, N. Kawai, M. Yoda, S. Tsuboi, T. Sawamura, A. Higo, R. Nakane, Y. Ochiai, Y. Mita Department of Electrical Engineering, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS59902.2024.10520699 HOVER FOR ABSTRACT	PDF Xplore
9.2	Electrical behavior of ALD-molybdenum films in the thin-film limit K. van der Zouw, S. D. Dulfer, A. A. I. Aarnink, A. Y. Kovalgin MESA+ Institute for Nanotechnology, University of Twente, AE Enschede, The Netherlands DOI: 10.1109/ICMTS59902.2024.10520676 HOVER FOR ABSTRACT	PDF Xplore