ICMTS 2024 Program

2024 Program Booklet

By Session

Bonus Talks

B1

How to write excellent papers C. Cagli STMicroelectronics, Crolles, France

Session 1: Layout Dependent Effects

1.1	Layout Dependent Effects Of Passive Devices And Their Impact On Analog Integrated Circuits A. Jayakumar, M. van Dort, M. Vertregt, G.D.J. Smit, R. Lander, I. Liu, P. Volf NXP Semiconductors B.V, Nijmegen, Netherlands DOI: 10.1109/ICMTS59902.2024.10520688 ABSTRACT: Analog blocks on products built using advanced CMOS technologies were seen to have deviating behavior on silicon than estimated by post layout simulations, especially in circuits used for biasing and reference generation. Circuit investigations pointed towards trimming resistor banks used for bias and reference current derivation. To detect possible unmodelled silicon effects experienced by these trimming resistor banks having different configurations in various analog blocks on products, a scribe-line test structure was implemented, aimed to capture major product design use-cases and study their effects. The outcome of this study is presented in this paper.	PDF Xplore
1.2	Test structures for studying the impact of the intrinsic contact metallization on the performance and stress sensitivity of SiGe HBTs O. Dieball, H. Tuinhout, Jeroen Zaal1 NXP Semiconductors, Modeling, Eindhoven, the Netherlands 1NXP Semiconductors, Package Innovation, Eindhoven, the Netherlands DOI: 10.1109/ICMTS59902.2024.10520678 ABSTRACT: Based on various layout realizations of a typical SiGe HBT, the electrical impact of the intrinsic contact metallizations as well as their mechanical stress sensitivities are explored. This investigation provides valuable insights into performance shifts, important for design of modelling test structures as well as for high-precision circuit design.	PDF Xplore
1.3	A Step-by-Step Layout Transformation Approach to Differentiate How Multiple Layout Dependent Effects Modify Device and Circuit Performance L. Lu, K. Xia, R. van Langevelde, C. C. McAndrew, W. Li NXP Semiconductors, Front End Innovation, China DOI: 10.1109/ICMTS59902.2024.10520696 ABSTRACT: The ring oscillator is an important component of the electronic device. Its performance, however, is sensitive to parasitic effects when the device sizes scale down to sub-microns. We present a method, utilizing a series of test structures which step-by-step transforms the ring oscillator layout into a single-device modeling layout, to differentiate and quantify the impact of individual layout dependent effects (LDEs) on the device level DC performance. A specially tuned model that fits to the DC performance of the devices in a ring oscillator can give correct timing behavior.	PDF Xplore

Session 2: Reliability

2.1	A novel test structure with two active areas for eNVM reliability studies K. Alkema, F. Melul, V. Della Marca1, M. Bocquet1, M. Akbal, A. Regnier, S. Niel2, F. La-Rosa STMicroelectronics, Rousset, France 1Aix-Marseille University, CNRS, Marseille, France 2STMicroelectronics Crolles, France DOI: 10.1109/ICMTS59902.2024.10520674 ABSTRACT: This paper presents a test structure with a poly floating gate shared on two actives areas. Programming and erase can be split toward these two regions with a specific arsenic implantation. The aim is to study the tunnel oxide degradation and the injection efficiency of embedded charge storage memory cells.	PDF Xplore
2.2	Test Structures of Cross-Domain Interface Circuits with Deep N-Well Layout to Improve CDM ESD Robustness H. -M. Huang, M. -D. Ker National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520690 ABSTRACT: Charged-device model (CDM) electrostatic discharge (ESD) is a complex reliability issue for integrated circuits in advanced CMOS technology. Cross-domain interface circuits are particularly susceptible to CDM ESD during cross-domain ESD events. In this study, CDM ESD robustness of cross-domain interface circuits with deep N-well was investigated through test structures fabricated in a 0.18-μm CMOS technology.	PDF Xplore
2.3	A 4H-SiC Trench MOS Capacitor Structure for Sidewall Oxide Characteristics Measurement H. -L. Huang, L. -T. Hsuesh, Y. -C. Tu, B. -Y. Tsui National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520701 ABSTRACT: Test structure for evaluating gate oxide properties on the trench sidewall in 4H-SiC is proposed. Using the thick bottom oxide and poly-Si spacer structure, we are able to measure the C-V characteristics directly and extract the interface state density. It is observed that typical NO annealing process cannot passivate the trench etching induced defects effectively.	PDF Xplore

Session 3: Cryogenic Characterization

3.1	Transistor Matrix Array for Measuring Variability and Random Telegraph Noise at Cryogenic Temperatures T. Mizutani, K. Takeuchi, T. Saraya, H. Oka1, T. Mori1, M. Kobayashi, T. Hiramoto The University of Tokyo, Tokyo, Japan 1National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan DOI: 10.1109/ICMTS59902.2024.10520700 ABSTRACT: Addressable transistor arrays using 65 nm bulk technology were fabricated and tested at cryogenic temperatures. It was confirmed that variability vs. 1/√𝐿𝑊 relationships at 1.5 K slightly degrades compared with 300 K. Random telegraph noise (RTN) was also measured and existence of extremely slow RTN at 1.5 K was confirmed using a quasi-parallel measurement technique.	PDF Xplore
3.2	Gaussian process-based device model toward a unified current model across room to cryogenic temperatures M. Shintani, T. Iwasaki, T. Sato1 Kyoto Institute of Technology Matsugasaki, Kyoto, Japan 1Kyoto University Yoshida-hon-machi, Kyoto, Japan DOI: 10.1109/ICMTS59902.2024.10520702 ABSTRACT: We apply a Sparse Gaussian process to build a compact model for CMOS circuits operating at cryogenic temperatures. The Sparse Gaussian process prevents overfitting problem unlike neural networks. Evaluation using measurement results of nMOS transistor fabricated by 65 nm demonstrate that the I-V characteristics from 4K to 300K are accurately modeled.	PDF Xplore
3.3	A Testbed for Cryogenic On-wafer Noise Measurement Using Cold Source Method with Temperature-Dependent Loss Correction G. -W. Huang, B. -Y. Chen, Y. -S. J. Shiao, C. -W. Chuang, L. -C. Shen, K. -M. Chen, C. -S. Chiu Taiwan Semiconductor Research Institute, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520691 ABSTRACT: On-wafer noise measurement at cryogenic temperatures is challenging due to complexity of temperature gradient distributions in cryostats. With proposed correction formulas, the cold source method may work properly for cryogenic on-wafer noise measurement and be a good fit for which involves of a large number of samples, e.g., Known-Good-Die Testing.	PDF Xplore

Session 4: Dielectrics and Ferroelectrics

4.1	Analysis and compensation of the series resistance effects on the characteristics of ferroelectric capacitors M. Massarotto, F. Driussi, M. Bucovaz, A. Affanni, S. Lancaster1, S. Slesazeck1, T. Mikolajick1, D. Esseni DPIA, University of Udine Udine, Italy 1NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS59902.2024.10520684 ABSTRACT: Ferroelectric device optimization requires a dependable characterization of the ferroelectric (FE) material. Here, we highlighted how series resistance (RS) impacts the I-V characteristics of Metal-Ferroelectric-Metal (MFM) stacks with peculiar distortions, possibly leading to an inaccurate extraction of the FE parameters and a misleading interpretation of its switching dynamics. For the first time to our knowledge, we here propose a procedure for an improved extraction of the FE parameters even in presence of a significant series resistance.	PDF Xplore
4.2	Impedance Measurement Platform for Statistical Capacitance and Current Characteristic Measurements of Arrayed Cells with Atto-order Precision K. Saito, T. Suzuki, H. Mitsuda, T. Nozaki, T. Mawaki, R. Kuroda Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS59902.2024.10520692 ABSTRACT: A novel impedance measurement platform that enables high-precision statistical measurements of C-V and I-V characteristics is presented. The platform consists of 366H × 228V cell array and a common readout circuit, and the pre-formed device under test (DUT) cells were measured to verify its measurement performance. The results demonstrated that for about 5,000 DUTs, the C-V measurement can measure fF-order capacitance with 0.06 % precision and the I-V measurement can measure fA-order current with 0.6 % precision.	PDF Xplore
4.3	Compact expression to model the effects of dielectric absorption on analog-to-digital converters S. Saro, P. Palestri1, E. Caruso2, P. Toniutti2, R. Calabro2, S. Terokhin2, F. Driussi DPIA, University of Udine Udine, Italy 1University of Modena and Reggio Emilia, Modena, Italy 2Infineon Technologies, Villach, Austria DOI: 10.1109/ICMTS59902.2024.10520681 ABSTRACT: An analytical model for the dielectric absorption on capacitors and its impact on the errors induced in ADC conversion is here proposed. The reported simulations are consistent with the results of the R-C model widely used in the literature and demonstrate that a large set of experiments can be fitted just calibrating a single model parameter.	PDF Xplore

Session 5: MEMs and Sensors

5.1	Test structure for chemiluminescence measurement in aqueous solutions: initial design A. A. Moreno-Guerrero, C. Dunare, A. Walton, P. Lomax, J. Terry, I. Underwood The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520697 ABSTRACT: On-chip integration of sensitive sensors is in high demand due to their extensive applications in chemical analysis. This research introduces a novel test structure for easy opto-electrical integration in microfluidic systems. The architecture has proven versatile for validating the fabrication process and as a final sensor for Luminol-based analysis.	PDF Xplore
5.2	Droplet Impact Sensing with Low Noise Coplanar Reverse-Electrowetting Test Structures A. Moyo, M. W. Shahzad, S. Smith1, J. G. Terry1, Y. Mita2, J. Lewis, Y. Li Northumbria University, Newcastle, UK 1The University of Edinburgh, Edinburgh, UK 2The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS59902.2024.10520253 ABSTRACT: Reverse electrowetting on dielectric (REWOD) has emerged to be a promising sensing technology for low frequency vibrations and deformations. This study aims to use test structures to study the parasitic elements in characterising the coplanar electrode (CREW) configuration of REWOD. This allows for better understanding in device design and optimization.	PDF Xplore
5.3	Analysis methodology of Deep Trench Isolation Field-Effect Passivation techniques for Image Sensors through dedicated test structures S. Tlemsani, S. Ricq, O. Marcelot1, P. Magnan1 STMicroelectronics Crolles, France 1ISAE, Toulouse, France DOI: 10.1109/ICMTS59902.2024.10520689 ABSTRACT: In this work a new methodology is proposed to characterize the Deep Trench Isolation field-effect passivation thanks to dedicated test structures. Two deep trench isolations are studied and quantitatively compared: an electrically active trench and an innovative passive trench using a charged Al2O3/SiO2 stack. The results show that the best passivation is achieved here with the active trench.	PDF Xplore
5.4	Parametric Optimization of RF MEMS Variable Capacitor with high linearity for C-Band Application S. Shaheen, P. Lomax, T. Arslan The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520682 ABSTRACT: A design methodology is proposed to obtain a linear C-V response and large capacitance tuning ratio by avoiding the pull-in effect. The study includes structural optimization of RF Microelectromechanical system (MEMS) varactor, using simulation tools ANSYS and HFSS. The optimized design shows better isolation at 4.2 GHz which makes it appropriate for C-Band applications.	PDF Xplore

Session 6: Wafer Measurements

6.1	Efficient Characterization Methodology for Low-Frequency Noise Monitoring L. Pirro, T. Chohan, P. Liebscher, M. Juettner, F. Holzmueller, R. Jain, Y. Raffel1, K. Seidel1, R. Olivo1, A. Zaka, J. Hoentschel GlobalFoundries, Dresden, Germany 1Fraunhofer-IPMS, Dresden, Germany DOI: 10.1109/ICMTS59902.2024.10520698 ABSTRACT: In this work, a novel methodology to characterize the Low-Frequency Noise LFN on large device statistics is proposed. The maximum drain current fluctuations over time are measured. The slope of the LFN distribution is modeled with physical equations related to the basic device properties. The approach is validated by studying the impact of transistor geometry (different gate width, number of fingers and length) as well as gate oxide thickness and characterization temperature. In conclusion, the proposed methodology is tested evaluating different process integration elements. The outcome is compared to classical 1/f read-out for final confirmation.	PDF Xplore
6.2	Rapid MOSFET threshold voltage testing for high throughput semiconductor process monitoring M. H. Herman, T. T. Nguyen, K. Wong, J. Johnson, B. Morris Advantest Corporation, San Jose,USA DOI: 10.1109/ICMTS59902.2024.10520252 ABSTRACT: We describe a rapid method for testing MOSFET threshold voltage (Vt). Multiple spot Ids measurements are compared to stored reference data. Each spot measurement gives an independent Vt, and multiple Vt estimates are used to generate quality metrics. Two spot measurements permit an accurate Vt within 7 msec.	PDF Xplore
6.3	Statistical investigation of SnOx RRAM memories for switching characteristics A. G. Panca, A. Serb, S. Stathopoulos, T. Prodromakis The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520675 ABSTRACT: Resistive Random Access Memory (RRAM) has seen significant developments in the past years. An important improvement is to solve the device-to-device variability that limits RRAM implementation. A proposed solution is to measure a high number of devices to statistically identify trends and evidences behind the cause. Here, we present a method to characterise the RRAM switching behaviour and analyse a large dataset of SnOx RRAM, in a statistical fashion for further optimization and modelling.	PDF Xplore
6.4	Making Accurate and Consistent Wafer Measurements with Next Generation Guarded True-Kelvin MEMS DC Probes C. B. Sia, Y. Funatoko, I. Kunioka, M. Watanabe, P. Andrews, K. Dawson, M. Sameshima, T. Saeki, J. Yang, J. Li, X. Li, S. Guo, L. Fan, W. M. Lim, E. Wilcox, A. Lord, S. Lastella, N. Kawamata, J. Klattenhoff, J. Kister, M. Losey, M. Slessor FormFactor Inc., Singapore DOI: 10.1109/ICMTS59902.2024.10520687 ABSTRACT: As silicon-based transistor scales down, it becomes increasingly challenging for test engineers to perform precise and repeatable waferb measurements. Reducing aluminium-capped copper test pads to 30μm×30μm and smaller means that new test strategies with novel true Kelvin MEMS probes are needed to overcome these emerging test challenges.	PDF Xplore

Session 7: S-Parameters and De-embedding

7.1	Understanding the substrate effect on de-embedding structures fabricated on SOI wafers using electromagnetic simulation B. Neckel Wesling, M. Deng1, C. Mukherjee1, T. Mikolajick, J. Trommer, C. Maneux1 NaMLab, Dresden, Germany 1IMS, Talence Cedex, France DOI: 10.1109/ICMTS59902.2024.10520694 ABSTRACT: In this paper, we present the fabrication, characterization and electro-magnetic (EM) simulation of open pad test-structures, emphasizing the impact of substrate properties on RF performance. We demonstrate that a high-resistivity substrate is essential to minimize losses and capacitances in RF measurements for technologies using Silicon on Isolator (SOI) wafers.	PDF Xplore
7.2	Modified Bisection Thru-Only Deembedding Algorithm for Long Test Fixtures A. Quint, L. Valenziano, J. Hebeler, T. Zwick, A. Bhutani Karlsruhe Institute of Technology, Karlsruhe, Germany DOI: 10.1109/ICMTS59902.2024.10520703 ABSTRACT: Thru-only deembedding is a simple deembedding method using a single deembedding structure. Common thru-only deembedding methods often have overshoots in the deembedded S-parameters when the deembedding structure is λ2 long. This is caused in the bisection step. A modified approach is presented, which extracts the phase of the S-parameters of the deembedding structure before the bisection step, performs the bisection on the magnitude of the S-parameters and applies the phase afterwards again, therefore eliminating the overshoots. The accuracy of the proposed algorithm is verified on measured test structures.	PDF Xplore
7.3	Evaluation of Lab-based Lithium Niobate Surface Acoustic Wave Test Structure Using Efficient Maskless Lithography and SMA Connection Approach for Microfluidic Applications M. S. Parvez, S. Hussain, M. Goeckner, C. D. Young, J. -B. Lee The University of Texas at Dallas, Richardson, USA 1Baylor University, Waco, USA DOI: 10.1109/ICMTS59902.2024.10520693 ABSTRACT: Surface Acoustic Wave (SAW) devices, particularly those made of Lithium Niobate (LiNbO3), are extensively used in telecommunications and microfluidic applications. This work describes the fabrication of a LiNbO3-based SAW test structures using maskless photolithography for rapid device dimension changes as well as introduces a cost-effective technique to solder SMA connectors to delicate substrates such as LiNbO3-based SAWs, without the need to fully create printed circuit boards. The SMA connected device facilitated improved characterization results compared to simple copper tape connections. The characterization accuracy is then validated through simulation.	PDF Xplore

Session 8: GaN Technology

8.1	Test Structures to Investigate ESD Robustness of GaN Devices for Applications of Circuit Integration W. -C. Wang, M. -D. Ker National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520680 ABSTRACT: ESD robustness of E-HEMT GaN devices was investigated through test structures fabricated in a GaN-on-Silicon process. The experimental results showed that the ESD robustness is proportional to the device dimension when it was operating in the forward mode. In addition, with the gate-coupled design, the ESD level of E-HEMT GaN device can be further improved.	PDF Xplore
8.2	Method for GaN HEMT IV Characterization Without Trap-Related Memory Effects J. Bremer, N. Rorsman, M. Thorsell Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS59902.2024.10520686 ABSTRACT: A new method to perform IV output characterizations of FETs is presented, which minimizes the influence of trap-related memory effects. This is achieved by minimizing the charging effects caused by the electric fields of preceding measurement points. The proposed method provides rudimentary IV characteristics, useful for technology evaluation and modeling purposes.	PDF Xplore
8.3	A Neural Network-based Manufacturing Variability Modeling of GaN HEMTs F. Chavez, D. Bavi, N. C. Miller1, S. Khandelwal Macquarie University, Macquarie Park, Australia 1Michigan State University, USA DOI: 10.1109/ICMTS59902.2024.10520695 ABSTRACT: A new technique to accurately model the manu- facturing variability of GaN HEMT using neural network(NN) is presented. PCA is used to automatically generate parameters from variations in I-V data, which are then used to train the NN. The trained NN model captures the I-V behavior of 115 GaN HEMT with excellent accuracy.	PDF Xplore
8.4	Use of DC Probes for Multi-MHz Measurements of Crosstalk and Substrate Coupling in Gallium Nitride Power Integrated Circuits M. Cui, S. Lam Xi’an Jiaotong-Liverpool University, Suzhou, China DOI: 10.1109/ICMTS59902.2024.10520677 ABSTRACT: With simple compact pads, DC probes were used for measurements of crosstalk and substrate coupling in gallium-nitride power integrated circuits. By proper calibration, a crosstalk voltage down to 4.4 mV and substrate coupling up to -38 dB were measured up to 25 MHz, using an oscilloscope and spectrum analyzer respectively.	PDF Xplore

Session 9: Process/Material Monitoring

9.1	An add-in Test Structure Chip to Unitedly Assess PVD Material Properties in University Open Nanotechnology Platform S. Yasunaga, K. Misumi, A. Mizushima, A. Toyokura, E. Ota, Y. Inoue, M. Fujitawa, N. Kawai, M. Yoda, S. Tsuboi, T. Sawamura, A. Higo, R. Nakane, Y. Ochiai, Y. Mita The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS59902.2024.10520699 ABSTRACT: Open nanotechnology platform at universities and research institutes is becoming an essential tool for agile and rapid microelectronic devices research and development. To further extend its capability with more users, process data acquisition and digital transformation (DX) is of high priority. In order to uniformly acquire process data in an open platform, where users’ process charts are all different, we are developing an add-on test structure chip. In the conference, we would like to share a chip design and measurement results to assess material parameters deposited by physical vapor deposition (sputtering and evaporation) materials.	PDF Xplore
9.2	Electrical behavior of ALD-molybdenum films in the thin-film limit K. van der Zouw, S. D. Dulfer, A. A. I. Aarnink, A. Y. Kovalgin University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS59902.2024.10520676 ABSTRACT: The thin-film electrical properties of molybdenum layers grown by atomic layer deposition were determined. Among others, four-point collinear probe, Van der Pauw, and (circular) transfer length method [(C)TLM] structures were designed and fabricated, which allowed to determine the sheet resistance (Rsh), temperature coefficient of resistance (TCR), contact resistance (Rc), transfer length (LT), and the field effect in a few nm thin Mo films.	PDF Xplore
9.3	Test Structure to Assess Bump Shape Influence on Hybrid Bonding A. Mizushima, K. Misumi, S. Yasunaga, A. Higo, R. Nakane, K. Tsumura1, K. Higashi1, Y. Ochiai, Y. Mita2 The University of Tokyo, Tokyo, Japan 1TOSHIBA CORPORATION, Kawasaki, Japan 2The University of Tokyo, Tokyo, Japan;  DOI: 10.1109/ICMTS59902.2024.10520685 ABSTRACT: Bump bonding is widely used in CMOS-MEMS integration. As compared to the other technology (planar bonding), bump bonding is more interesting for its simplicity and applicability to wide range of device types. Towards higher density and reliability improvement, the authors have designed and fabricated a test structure. Our new contribution is to intentionally structuralize shapes of bumps to not only a flat head but concave as well as convex ones, expecting better occlusion and passive alignment. To experiment our new idea, the first test structure has been fabricated to assess alignment accuracy and resistance.	PDF Xplore

By First Author

2.1	A novel test structure with two active areas for eNVM reliability studies K. Alkema, F. Melul, V. Della Marca1, M. Bocquet1, M. Akbal, A. Regnier, S. Niel2, F. La-Rosa STMicroelectronics, Rousset, France 1Aix-Marseille University, CNRS, Marseille, France 2STMicroelectronics Crolles, France DOI: 10.1109/ICMTS59902.2024.10520674 HOVER FOR ABSTRACT	PDF Xplore
8.2	Method for GaN HEMT IV Characterization Without Trap-Related Memory Effects J. Bremer, N. Rorsman, M. Thorsell Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS59902.2024.10520686 HOVER FOR ABSTRACT	PDF Xplore
B1	How to write excellent papers C. Cagli STMicroelectronics, Crolles, France HOVER FOR ABSTRACT
8.3	A Neural Network-based Manufacturing Variability Modeling of GaN HEMTs F. Chavez, D. Bavi, N. C. Miller1, S. Khandelwal Macquarie University, Macquarie Park, Australia 1Michigan State University, USA DOI: 10.1109/ICMTS59902.2024.10520695 HOVER FOR ABSTRACT	PDF Xplore
8.4	Use of DC Probes for Multi-MHz Measurements of Crosstalk and Substrate Coupling in Gallium Nitride Power Integrated Circuits M. Cui, S. Lam Xi’an Jiaotong-Liverpool University, Suzhou, China DOI: 10.1109/ICMTS59902.2024.10520677 HOVER FOR ABSTRACT	PDF Xplore
1.2	Test structures for studying the impact of the intrinsic contact metallization on the performance and stress sensitivity of SiGe HBTs O. Dieball, H. Tuinhout, Jeroen Zaal1 NXP Semiconductors, Modeling, Eindhoven, the Netherlands 1NXP Semiconductors, Package Innovation, Eindhoven, the Netherlands DOI: 10.1109/ICMTS59902.2024.10520678 HOVER FOR ABSTRACT	PDF Xplore
6.2	Rapid MOSFET threshold voltage testing for high throughput semiconductor process monitoring M. H. Herman, T. T. Nguyen, K. Wong, J. Johnson, B. Morris Advantest Corporation, San Jose,USA DOI: 10.1109/ICMTS59902.2024.10520252 HOVER FOR ABSTRACT	PDF Xplore
2.2	Test Structures of Cross-Domain Interface Circuits with Deep N-Well Layout to Improve CDM ESD Robustness H. -M. Huang, M. -D. Ker National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520690 HOVER FOR ABSTRACT	PDF Xplore
2.3	A 4H-SiC Trench MOS Capacitor Structure for Sidewall Oxide Characteristics Measurement H. -L. Huang, L. -T. Hsuesh, Y. -C. Tu, B. -Y. Tsui National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520701 HOVER FOR ABSTRACT	PDF Xplore
3.3	A Testbed for Cryogenic On-wafer Noise Measurement Using Cold Source Method with Temperature-Dependent Loss Correction G. -W. Huang, B. -Y. Chen, Y. -S. J. Shiao, C. -W. Chuang, L. -C. Shen, K. -M. Chen, C. -S. Chiu Taiwan Semiconductor Research Institute, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520691 HOVER FOR ABSTRACT	PDF Xplore
1.1	Layout Dependent Effects Of Passive Devices And Their Impact On Analog Integrated Circuits A. Jayakumar, M. van Dort, M. Vertregt, G.D.J. Smit, R. Lander, I. Liu, P. Volf NXP Semiconductors B.V, Nijmegen, Netherlands DOI: 10.1109/ICMTS59902.2024.10520688 HOVER FOR ABSTRACT	PDF Xplore
1.3	A Step-by-Step Layout Transformation Approach to Differentiate How Multiple Layout Dependent Effects Modify Device and Circuit Performance L. Lu, K. Xia, R. van Langevelde, C. C. McAndrew, W. Li NXP Semiconductors, Front End Innovation, China DOI: 10.1109/ICMTS59902.2024.10520696 HOVER FOR ABSTRACT	PDF Xplore
4.1	Analysis and compensation of the series resistance effects on the characteristics of ferroelectric capacitors M. Massarotto, F. Driussi, M. Bucovaz, A. Affanni, S. Lancaster1, S. Slesazeck1, T. Mikolajick1, D. Esseni DPIA, University of Udine Udine, Italy 1NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS59902.2024.10520684 HOVER FOR ABSTRACT	PDF Xplore
9.3	Test Structure to Assess Bump Shape Influence on Hybrid Bonding A. Mizushima, K. Misumi, S. Yasunaga, A. Higo, R. Nakane, K. Tsumura1, K. Higashi1, Y. Ochiai, Y. Mita2 The University of Tokyo, Tokyo, Japan 1TOSHIBA CORPORATION, Kawasaki, Japan 2The University of Tokyo, Tokyo, Japan;  DOI: 10.1109/ICMTS59902.2024.10520685 HOVER FOR ABSTRACT	PDF Xplore
3.1	Transistor Matrix Array for Measuring Variability and Random Telegraph Noise at Cryogenic Temperatures T. Mizutani, K. Takeuchi, T. Saraya, H. Oka1, T. Mori1, M. Kobayashi, T. Hiramoto The University of Tokyo, Tokyo, Japan 1National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan DOI: 10.1109/ICMTS59902.2024.10520700 HOVER FOR ABSTRACT	PDF Xplore
5.1	Test structure for chemiluminescence measurement in aqueous solutions: initial design A. A. Moreno-Guerrero, C. Dunare, A. Walton, P. Lomax, J. Terry, I. Underwood The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520697 HOVER FOR ABSTRACT	PDF Xplore
5.2	Droplet Impact Sensing with Low Noise Coplanar Reverse-Electrowetting Test Structures A. Moyo, M. W. Shahzad, S. Smith1, J. G. Terry1, Y. Mita2, J. Lewis, Y. Li Northumbria University, Newcastle, UK 1The University of Edinburgh, Edinburgh, UK 2The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS59902.2024.10520253 HOVER FOR ABSTRACT	PDF Xplore
6.3	Statistical investigation of SnOx RRAM memories for switching characteristics A. G. Panca, A. Serb, S. Stathopoulos, T. Prodromakis The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520675 HOVER FOR ABSTRACT	PDF Xplore
7.3	Evaluation of Lab-based Lithium Niobate Surface Acoustic Wave Test Structure Using Efficient Maskless Lithography and SMA Connection Approach for Microfluidic Applications M. S. Parvez, S. Hussain, M. Goeckner, C. D. Young, J. -B. Lee The University of Texas at Dallas, Richardson, USA 1Baylor University, Waco, USA DOI: 10.1109/ICMTS59902.2024.10520693 HOVER FOR ABSTRACT	PDF Xplore
6.1	Efficient Characterization Methodology for Low-Frequency Noise Monitoring L. Pirro, T. Chohan, P. Liebscher, M. Juettner, F. Holzmueller, R. Jain, Y. Raffel1, K. Seidel1, R. Olivo1, A. Zaka, J. Hoentschel GlobalFoundries, Dresden, Germany 1Fraunhofer-IPMS, Dresden, Germany DOI: 10.1109/ICMTS59902.2024.10520698 HOVER FOR ABSTRACT	PDF Xplore
7.2	Modified Bisection Thru-Only Deembedding Algorithm for Long Test Fixtures A. Quint, L. Valenziano, J. Hebeler, T. Zwick, A. Bhutani Karlsruhe Institute of Technology, Karlsruhe, Germany DOI: 10.1109/ICMTS59902.2024.10520703 HOVER FOR ABSTRACT	PDF Xplore
4.2	Impedance Measurement Platform for Statistical Capacitance and Current Characteristic Measurements of Arrayed Cells with Atto-order Precision K. Saito, T. Suzuki, H. Mitsuda, T. Nozaki, T. Mawaki, R. Kuroda Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS59902.2024.10520692 HOVER FOR ABSTRACT	PDF Xplore
4.3	Compact expression to model the effects of dielectric absorption on analog-to-digital converters S. Saro, P. Palestri1, E. Caruso2, P. Toniutti2, R. Calabro2, S. Terokhin2, F. Driussi DPIA, University of Udine Udine, Italy 1University of Modena and Reggio Emilia, Modena, Italy 2Infineon Technologies, Villach, Austria DOI: 10.1109/ICMTS59902.2024.10520681 HOVER FOR ABSTRACT	PDF Xplore
5.4	Parametric Optimization of RF MEMS Variable Capacitor with high linearity for C-Band Application S. Shaheen, P. Lomax, T. Arslan The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520682 HOVER FOR ABSTRACT	PDF Xplore
3.2	Gaussian process-based device model toward a unified current model across room to cryogenic temperatures M. Shintani, T. Iwasaki, T. Sato1 Kyoto Institute of Technology Matsugasaki, Kyoto, Japan 1Kyoto University Yoshida-hon-machi, Kyoto, Japan DOI: 10.1109/ICMTS59902.2024.10520702 HOVER FOR ABSTRACT	PDF Xplore
6.4	Making Accurate and Consistent Wafer Measurements with Next Generation Guarded True-Kelvin MEMS DC Probes C. B. Sia, Y. Funatoko, I. Kunioka, M. Watanabe, P. Andrews, K. Dawson, M. Sameshima, T. Saeki, J. Yang, J. Li, X. Li, S. Guo, L. Fan, W. M. Lim, E. Wilcox, A. Lord, S. Lastella, N. Kawamata, J. Klattenhoff, J. Kister, M. Losey, M. Slessor FormFactor Inc., Singapore DOI: 10.1109/ICMTS59902.2024.10520687 HOVER FOR ABSTRACT	PDF Xplore
5.3	Analysis methodology of Deep Trench Isolation Field-Effect Passivation techniques for Image Sensors through dedicated test structures S. Tlemsani, S. Ricq, O. Marcelot1, P. Magnan1 STMicroelectronics Crolles, France 1ISAE, Toulouse, France DOI: 10.1109/ICMTS59902.2024.10520689 HOVER FOR ABSTRACT	PDF Xplore
8.1	Test Structures to Investigate ESD Robustness of GaN Devices for Applications of Circuit Integration W. -C. Wang, M. -D. Ker National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520680 HOVER FOR ABSTRACT	PDF Xplore
7.1	Understanding the substrate effect on de-embedding structures fabricated on SOI wafers using electromagnetic simulation B. Neckel Wesling, M. Deng1, C. Mukherjee1, T. Mikolajick, J. Trommer, C. Maneux1 NaMLab, Dresden, Germany 1IMS, Talence Cedex, France DOI: 10.1109/ICMTS59902.2024.10520694 HOVER FOR ABSTRACT	PDF Xplore
9.1	An add-in Test Structure Chip to Unitedly Assess PVD Material Properties in University Open Nanotechnology Platform S. Yasunaga, K. Misumi, A. Mizushima, A. Toyokura, E. Ota, Y. Inoue, M. Fujitawa, N. Kawai, M. Yoda, S. Tsuboi, T. Sawamura, A. Higo, R. Nakane, Y. Ochiai, Y. Mita The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS59902.2024.10520699 HOVER FOR ABSTRACT	PDF Xplore
9.2	Electrical behavior of ALD-molybdenum films in the thin-film limit K. van der Zouw, S. D. Dulfer, A. A. I. Aarnink, A. Y. Kovalgin University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS59902.2024.10520676 HOVER FOR ABSTRACT	PDF Xplore