ICMTS 2022 Program

2022 Program Booklet

By Session

Session 1: Process Characterization I

1.1	Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization M. Udo, M. Islam1, H. Onodera2 Graduate School of Informatics, Kyoto University, Yoshida-honmachi, Sakyo-ku, Kyoto 606-8501, JAPAN 1Graduate School of Engineering, Kyoto University, Kyoto Daigaku Katsura, Nishikyo-ku, Kyoto 615-8510, JAPAN 2Faculty of Informatics, Osaka Gakuin University, 2-36-1 Kishibe-Minami, Suita 564-8511, JAPAN DOI: 10.1109/ICMTS50340.2022.9898111 ABSTRACT: Ring oscillator circuits are useful for the characterization of MOS transistors under switching operation. Accurate characterization of per-gate variation becomes difficult when the ring oscillator consists of many stages or contains heterogeneity. We propose a homogeneous ring oscillator structure with a staggered layout for the accurate characterization of per-gate characteristics. Using a header transistor instead of a NAND gate for oscillation control, our proposed structure can realize a 3-stage RO where the three stages have equal delay contributions. Measurement results from a 65 nm test chip confirm our proposed structure for gate-level characterization.	PDF Xplore
1.2	Test Structures for Characterising the Fabrication of Miniature Reference Electrodes C. Dunare, S. Zhang, J. R. K. Marland, A. Tsiamis, P. Sullivan, I. Underwood, J. G. Terry, A. J. Walton, S. Smith1 School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, Edinburgh, Scotland, UK 1School of Engineering, Institute for Bioengineering, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS50340.2022.9898104 ABSTRACT: Robust and reliable micro-scale integrated electrochemical sensors need a reference electrode that can provide a stable electrochemical potential. This can be achieved using a silver/silver chloride (Ag/AgCl) electrode, produced by the chemical chlorination of a thin patterned silver layer. Well understood and controlled processes are required to produce the Ag/AgCl electrode. This paper shows how previously reported test structures have been used to characterise and inform the fabrication procedure. Wafer mapping of these structures was carried out using a Python controlled measurement system, consisting of a semi-automatic prober connected to an HP4062UX based analyser. The measurements were analysed to determine whether the chlorination process was affected by the test structure geometry. This was found to have no clear effect on chlorination.	PDF Xplore
1.3	Design of Low-Cost Test Structures for Measuring Within-Die Process Skew Variations A. Majumdar, N. Chong AMD Inc., San Jose, CA 95124 DOI: 10.1109/ICMTS50340.2022.9898217 ABSTRACT: The potential for expanding the use of ring oscillators (ROs) into a new and, as yet, unexplored area was reported in [1]. Simply stated, departures in strengths of PMOS and NMOS transistors from nominal, cause changes in duty-cycles at different nodes of ROs. Given the right RO design, both DC & AC contributions of transistors to process-skew can be determined at the same time.In this paper we address the related engineering problem of creating such RO designs that are specifically tuned for sensing process-skew. Design criteria and methodology are defined for ROs that are sensitive to and amplify the effect of process-skew. Example designs of such ROs are presented along with simulation results to demonstrate their efficacy as process-skew sensors. The simplicity of the proposed designs allows distributing many instances of these sensors on a die, in turn, creating the possibility of characterizing within-die process skew variations.	PDF Xplore
1.4	Combined Machine Learning Techniques For Characteristics Classification and Threshold Voltage Extraction of Transistors H. M. Koçak, J. Mitard1, A. T. Naskali Department of Computer Engineering, Galatasaray University, Istanbul, Turkey 1Compute and Memory Department, IMEC, Leuven, Belgium DOI: 10.1109/ICMTS50340.2022.9898251 ABSTRACT: We present an autonomous 2-step Machine Learning based approach for characteristics classification and key parameter extraction for transistors. The first step is a multi-model ensemble, composed of Machine Learning, more particularly a Convolutional Neural Network (CNN) approach to enable fast classification of transistor characteristics. The second step is another CNN model to extract the threshold voltage parameters that enable us to measure the performance of ultra-scaled MOSFETs. Our CNN-based classifier has demonstrated accuracy above 90% with an execution time significantly faster than that of the current human expert-based methods while our Vth extractor has demonstrated less than 8mV error rate in the filtered dataset that comes from the classifier. The proposed techniques which do not incorporate hard-coded domain knowledge, and are also tested with input data coming from 16nm-node FinFET technology and evaluated by a consensus of experts to prove the universality of the models using the same parameters.	PDF Xplore

Session 2: RF

2.1	S-Parameter Measurement and EM Simulation of Electronic Devices towards THz frequency range C. Yadav, S. Fregonese1, M. Cabbia1, M. Deng1, M. De Matos1, T. Zimmer1 National Institute of Technology Calicut, Kozhikode, Kerala, India 1IMS Laboratory, University of Bordeaux, France DOI: 10.1109/ICMTS50340.2022.9898233 ABSTRACT: In this paper, we present on-wafer S-parameter measurement of silicon-based devices up to 500 GHz and EM simulation analysis up to 750GHz. The EM simulation is carried out with RF probe models and without RF probe model (intrinsic EM simulation) up to 750 GHz. To understand difference between EM simulation predictions with and without RF probe model in frequency range 500 - 750 GHz, electric field distributions in the DUTs are analysed.	PDF Xplore
2.2	300-GHz Back-Radiation On-Chip-Antenna Measurement with Electromagnetic-Wave-Absorption Sheet S. Lee, K. Katayama1, K. Takano1, M. Fujita2, M. Toyoda2, S. Hara3, I. Watanabe3, A. Kasamatsu3, S. Amakawa1, T. Yoshida1, M. Fujishima1 Inst. of Innovative Research, Tokyo Inst. of Technol., Yokohama, Japan 1Grad. School of Advanced Sci. and Eng., Hiroshima Univ., Higashihiroshima, Japan 2New Business Produce Div., Maxell, Ltd., Otokuni, Japan 3Advanced ICT Research Inst., Nat’l. Inst. of Info. and Comms. Technol., Koganei, Japan DOI: 10.1109/ICMTS50340.2022.9898229 ABSTRACT: A method is demonstrated to improve measurement accuracy for a back-radiation (inward-directed-radiation) on-chip antenna using a 300-GHz electromagnetic-wave absorption sheet. Electromagnetic-wave reflection owing to the material beneath a chip substrate occurs during the on-wafer measurement, leading to the input-impedance variance of that antenna at the feeding port, therefore, should be reduced using the method.	PDF Xplore
2.3	Modeling and Verificaion of Millimeter-Wave nMOSFET up to 50 GHz in 180 nm CMOS Technology K. Sekine, K. Takano, Y. Umeda Department of Electrical Engineering, Tokyo University of Science, Chiba, Japan DOI: 10.1109/ICMTS50340.2022.9898222 ABSTRACT: In recent years, research on the millimeter-wave band has become popular as 5G (fifth generation) becomes more widespread. 5G uses the 28 GHz band to achieve high-speed, high-capacity wireless communications. Therefore, attempts have been made to use relatively inexpensive legacy processes in the millimeter-wave band. The problem with the legacy process is that there is no model for the millimeter-wave band. When designing a circuit with nonlinear behavior, it is necessary that the model works at least at its second harmonic frequency. In this study, we present the modeling method of an nMOSFET up to 50 GHz fabricated in the 180 nm CMOS process, and verify it using a 20 GHz oscillator with the second harmonic frequency of 40 GHz [1,2]. We show that the difference between the simulated and measured oscillation frequencies is below 5 %.	PDF Xplore
2.4	Optimal Test Structures for the Characterization of Integrated Transformers at mm-wave frequencies using the Open/Thru De-embedding Technique M. Lauritano, P. Baumgartner Intel Germany, Neubiberg, Germany DOI: 10.1109/ICMTS50340.2022.9898235 ABSTRACT: This article investigates the characterization of integrated transformers at mm-wave frequencies using the open/thru de-embedding methodology. Using electromagnetic simulations, layout guidelines for the test fixture are derived which allow to obtain good accuracy of the extracted parameters in spite of the simple method. Several test structures implementing these guidelines are fabricated on a testchip in a 16nm CMOS process and measured to demonstrate the concept.	PDF Xplore

Session 3: Reliability

3.1	Two-pads per electrode in-situ test structure for micron-scale flip-chip bonding reliability of chip-on-chip device Y. Ebihara, A. Mizushima, T. Yoda1, K. Hirakawa1, M. Iwase1, M. Ogasawara1, A. Higo, Y. Ochiai, Y. Mita School of Engineering, The University of Tokyo, Japan 1Laboratory for Future Interdisciplinary Research of Science and Technology, Tokyo Institute of Technology, Japan DOI: 10.1109/ICMTS50340.2022.9898248 ABSTRACT: Arrayed CMOS-MEMS Devices are often made separately, and they are face-to-face flip-chip bonded for electrical connection. We propose an in-situ testing method by “two-pad-per- electrode” design to check the contact of bonding pads, which enables testing bonding contact between production chips and identification of the place of defects.	PDF Xplore
3.2	Characterizing Aging Degradation of Integrated Circuits with a Versatile Custom Array of Reliability Test Structures A. Santana-Andreo, P. Martin-Lloret, E. Roca, R. Castro-Lopez, F. V. Fernandez IMSE, CSIC-Universidad de Sevilla, Seville, Spain DOI: 10.1109/ICMTS50340.2022.9898256 ABSTRACT: This work presents an integrated circuit array with custom test structures for the characterization of aging phenomena that includes three types of commonly-used circuits: inverters, single-stage amplifiers, and current mirrors. The array allows the characterization of these circuit blocks through a wide variety of metrics and different accelerated stress and operating conditions. This characterization clearly shows the stochastic nature of aging and the importance of a dedicated test structure to fully understand it at the circuit level.	PDF Xplore
3.3	Utilization of Poly Heater Test Structures in the Characterization of Bias Temperature Instability Y. -H. Cheng, M. Cook, D. Allman Corporate Research and Development, East Greenwich, RI 02818, USA DOI: 10.1109/ICMTS50340.2022.9898183 ABSTRACT: Test structures with a poly heater and a dedicated diode were employed in the characterization of bias temperature instability for 5V MOS devices in a 0.18μm CMOS smart power technology. Utilization of poly heater provides in situ temperature changes to allow different temperatures for stress and measurement and produces BTI degradation results with reduced relaxation in measurement, in good agreement with data from fast measurement system. Methodology for feedback temperature control was established and can be applied to different shapes and geometries of poly heater test structures. The test approach of utilizing poly heater for NBTI characterization provides a tool for fast NBTI assessment of wafer level reliability.	PDF Xplore

Session 4: Process Characterization II

4.1	Layout-Dependent Vertical and In-Plane Leakage Current Reduction of Organic Thin-Film Transistors by Layer Contact Restriction K. Oshima, K. Kuribara1, T. Sato Graduate School of Informatics, Kyoto University, Yoshida-hon-machi, Sakyo, Kyoto 606-8501, Japan 1National Institute of Advanced Industrial Science and Technology (AIST) DOI: 10.1109/ICMTS50340.2022.9898196 ABSTRACT: Organic thin-film transistors (OTFTs) are promising devices for designing flexible large-area sensor circuits. However, owing to the low carrier mobility of n-type organic semiconductors and relatively high leakage currents, the on/off current ratio cannot be sufficiently high, making the stable logic operation of OTFT circuits difficult. In this paper, the evaluation and reduction of layout-dependent leakage currents in OTFTs are presented. Experiments revealed that the layout design, in which the source and drain electrodes were contained within the gate metal and the semiconductor area, reduced the leakage current and improved the pull-down voltage level of the bottom-gate top-contact (BG-TC) OTFT logic gates. Additionally, the rail-to-rail operation of the OTFT logic gates was successfully demonstrated.	PDF Xplore
4.2	Temperature Characterizations of Multi-Unit and Multi-finger Dependencies on AlGaN/GaN Ridge HEMTs H. Aoki, N. Kuroda1, A. Yamaguchi1, K. Nakahara R&D Center, ROHM Co., Ltd, Kyoto 615-8585, Japan 1Core Technology R&D Division, R&D Center, ROHM Co., Ltd, Kyoto 615-8585, Japan DOI: 10.1109/ICMTS50340.2022.9898230 ABSTRACT: Temperature and geometry dependencies on drain current including hole injection current, self-heating, and current collapse by buffer potential of AlGaN/GaN ridge HEMTs (known as gate injection transistors) have been characterized with our dedicated test structures including multi-finger and multi-unit devices in addition to the gate length and width variations.	PDF Xplore
4.3	Single Device MOSFET Series Resistance Extraction Methods: Comparison Between Newer and Older K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, JAPAN DOI: 10.1109/ICMTS50340.2022.9898270 ABSTRACT: Older and newer methods for extracting MOSFET source/drain series resistance are compared and discussed. Both methods use a single device for extraction, and tries to exploit internal bias modulation induced by varying applied drain voltage. It will be shown that the older method does not properly work in its original form, since it is strongly affected by only a slight change of mobility caused by applied biases, especially by weak velocity saturation. The newer method, which overcomes this problem by taking into account the dependence of mobility on both gate and drain biases, is used to graphically illustrate how the mobility change affects the older one.	PDF Xplore

Session 5: Memory

5.1	Embedded measurement of the SET switching time of RRAM memory cells F. Jebali, E. Muhr, M. Alayan, M. C. Faye, D. Querlioz1, F. Andrieu2, E. Vianello2, G. Molas2, M. Bocquet, J. M. Portal Aix-Marseille Univ., Marseille, France 1Université Paris-Saclay, 91120 Palaiseau, France 2CEA, LETI, Grenoble, France DOI: 10.1109/ICMTS50340.2022.9898162 ABSTRACT: This paper presents an embedded measurement circuit dedicated to the extraction of the SET switching time of RRAM memory cells. A brief overview of the measurement circuit, designed in a hybrid 130nm technology with HfO2 BEoL RRAMs, is given with emphasis on the write termination (WT) mechanism and the switching time acquisition thanks to a Time-to-Digital Converter (TDC) shift and capture mechanism. The experimental test set-up and test conditions are then described, including automated measurement script. Following our test procedure, we are able to extract the measured RRAM resistance values and the associated SET switching times, using a de-embedding process. Resistances and SET switching time values fully complies with the ones obtained in the literature through heavy waveguide measurement setups, validating our approach.	PDF Xplore
5.2	Statistical Modeling of SRAM PUF Cell Mismatch Shift Distribution After Hot Carrier Injection Burn-In K. Liu, K. Takeuchi1, H. Shinohara2 Information, Production and Systems, Research Center, Waseda University, Kitakyushu, Japan 1Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 2Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan DOI: 10.1109/ICMTS50340.2022.9898258 ABSTRACT: This article presents statistical modeling for bitcell mismatch shift with respect to hot carrier injection (HCI) burn-in on a static random access memory (SRAM)-based physically unclonable function (PUF). A compound distribution based on a Poisson distribution and a Gamma distribution is used to model the mismatch shift. The Poisson distribution models the number of injected hot carriers, and the Gamma distribution models the mismatch shift value induced by a certain number of injected hot carriers. This model is evaluated by testing chips fabricated in a 130-nm CMOS process. Experimental results collected from 2-min to 8-min HCI burn-in match the model well. Results also show that the number of injected hot carriers has a linear relation with the burn-in time to the power 0.6.	PDF Xplore
5.3	SuperCAST: a full free addressable memory array V. D. Marca, J. Guilleau-Tavernier, P. Laine, F. Melul, M. Bocquet, T. Kempf1, L. Welter1, J. -M. Moragues1, A. Regnier1, J. -M. Portal Aix-Marseille Université, 13397 Marseille, France 1STMicroelectronics, 13106 Rousset, France DOI: 10.1109/ICMTS50340.2022.9898189 ABSTRACT: In this paper we present a full free addressable 4kb EEPROM memory array. This test structure based on CAST vehicle has been upgraded with flexible addressing logic to select any numbers of cells on single or multiple word lines. To this aim, column/row shift registers, to enable an easy cell biasing, have been implemented in an embedded non-volatile memory environment. High voltage circuits, driven by low voltage shift registers, are used to bias selected cells for electrical characterizations and reliability tests purposes. This kind of structure has been developed to improve the efficiency of electrical characterization laboratory, resulting in an enhanced acquisition with respect to standard CAST test techniques, opening the path to fine statistical analysis.	PDF Xplore
5.4	CMOS Platform TEG for Development of High Performance Synaptic Devices Y. -J. An, S. -H. Kim, K. -W. Song, H. -J. Shin, T. -G. Ryu, S. -B. Eadi, H. -M. Kwon1, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejoen, Korea 1Department of Semiconductor Processing Equipment, Semiconductor Convergence Campus of Korea Polytechnics College, Ansung, Korea DOI: 10.1109/ICMTS50340.2022.9898228 ABSTRACT: In this paper, complementary metal-oxide-semiconductor (CMOS) based test structure platform is proposed for development of high performance synaptic devices. The main idea of this platform is that everyone who has high performance synaptic device solution can form the devices on top of the platform wafers with only three photolithography steps without design burden of CMOS circuits for accurate characterization of huge number of synaptic devices up to 250,000 within 10 minutes. The proposed platform is comprised of 16 ⨉ 16, 64 ⨉ 64, and 512 ⨉ 512 NMOS array chips where each chip has three analog DEMUXs for accurate measurement of the synaptic devices. The CMOS TEGs in the platform was designed using a 0.18 μm CMOS foundry with BEOL up to metal 4 layers. The CMOS test element groups (TEG) can be utilized to evaluate the main characteristics of synaptic devices, such as variability, reliability, statistical analysis and applicability to neuromorphic chips. We demonstrated the performance and the application of the TEG by integrating and characterizing synaptic devices on these TEG.	PDF Xplore

Session 6: Materials Characterization

6.1	An Evaluation for Quality Inspection of Epitaxial Layer and Heavily-doped 4H-SiC Substrate by Simple Schottky Barrier Diode and MOS Capacitor K. -W. Chu, C. -W. Tseng1, B. -Y. Tsui1, Y. -C. S. Wu, C. -J. Yang2, C. Hsu2 Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C 1Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C 2Innovation Technology Research Center, GlobalWafers Co., Ltd., Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS50340.2022.9898247 ABSTRACT: Reducing the crystal defects in SiC is an important issue. In this work, we propose a short turn-around method using simple SBD and MOSC devices to reflect the electrically-active defect density in the substrate. Simple SBD and MOSC structures are fabricated on n− epi-layer/n+ substrate or pure n+ substrate that have different defect densities. The n− epi-layer SBDs for high-defect wafers generate high yield loss, a more comprehensive leakage current distribution, and a stronger bias-dependent leakage current than low-defect alternatives. The pure n+ substrate SBDs of high-defect wafers only reveal a higher leakage level than the low-defect alternatives. This phenomenon may be caused by the variation of doping concentration or Schottky barrier height. The pure n+ substrate MOSCs show a higher yield loss than the n− epi-layer MOSCs based on TZDB, where the leakage level is identical for both the high-defect and the low-defect wafers. It is suggested that the epitaxial quality can be evaluated by using the simple SBD, where the heavily-doped substrate is not suitable. Both the n− epi-layer and the pure n+ substrate MOSCs cannot reflect electrically-active defect densities for the TZDB phenomena.	PDF Xplore
6.2	Application of a Test Structure for Minimising Seed Layer Thickness of Electroplated Ferromagnetic Films A. W. S. Ross, C. M. Dover, S. Smith1, J. G. Terry, A. R. Mount2, A. J. Walton School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, Edinburgh, Scotland, UK 1School of Engineering, Institute for Bioengineering, The University of Edinburgh, Edinburgh, Scotland, UK 2School of Chemistry, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS50340.2022.9898250 ABSTRACT: This paper presents a previously documented full wafer test structure, designed to quantify the effect of seed layer thickness and conductivity on the plating uniformity of patterned electroplated structures. With magnetic films, non-magnetic seed layers need to be as thin as possible to minimise unwanted eddy currents. This paper uses the test structure to quantify the IR drop on the electroplated film and demonstrates how current distribution structures can be simply used to significantly improve wafer plating uniformity when using seed layer thicknesses of a few nanometers.	PDF Xplore
6.3	Test Measurements for Charge Trapping in Different Polarization Ferroelectric FETs S. Deng, K. Ni, S. K. Kurinec Department of Electrical & Microelectronic Engineering, Rochester Institute of Technology, Rochester, New York 14623, USA DOI: 10.1109/ICMTS50340.2022.9898271 ABSTRACT: This study presents a measurement methodology to reveal the effects of ferroelectric polarization switching, charge trapping and de-trapping effects in Ferroelectric Field Effect Transistors (FeFETs). Combining the write pulse and transfer characteristics read for Memory Window (MW) determination with one-spot measurement demonstrates the interplay between the polarization switching and charge trapping effects. These measurements have been done on n channel FeFETs fabricated in-house with 10nm ferroelectric hafnium zirconium oxide as the gate dielectric.	PDF Xplore

Session 7: Yield

7.1	DFI Filler Cells -- New Embedded Type of Test Structures for Non-Contact Detection of Electrical Defects on Product Wafers S. Lam, C. Hess, L. Weiland, M. Moe, X. W. Shen, J. Chen, I. De, M. Strojwas, T. Brozek PDF Solutions, Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS50340.2022.9898254 ABSTRACT: A new type of test structures has been developed for process monitoring and defect detection on product wafers. The structures are part of PDF Solutions’ proprietary Design-for-Inspection™ (DFI) system. They electrically tested in a non-contact way using a dedicated and specially optimized e-Beam tool. They are designed to be compatible with standard cells and to be used as filler cells in standard cell-based logic designs. The paper presents the design and usage of such DFI structures as well as illustrated results collected from scanning product wafers containing embedded DFI filler cells.	PDF Xplore
7.2	Contact Fail Monitoring with an Epi Resistance Test Structure for 7nm FinFET Product C. H. Lee, B. W. Jeong1, S. Wu, M. Kim1, X. Chen, K. Onishi, C. Manya, L. Anastos, J. Sim, M. Angyal Fabless Foundry Interaction, Processor Product Engineering, IBM Systems, NY 12533-6683 1Samsung Electronics Co. Ltd., Hwasung-City, Gyeonggi-Do, 445-701, Republic of Korea DOI: 10.1109/ICMTS50340.2022.9898262 ABSTRACT: This paper describes a test site and yield issues in FinFET product. We present the test structure and the early failure detection method for 7nm FinFET product.	PDF Xplore

Session 8: Test

8.1	Issues and advances in rapid Quasi-Static CV for high throughput semiconductor process monitoring M. H. Herman, D. Jang, M. Nagel, B. Morris Parametric Test Group, Advantest America, San Jose, United States DOI: 10.1109/ICMTS50340.2022.9898273 ABSTRACT: A rapid Quasi-Static Capacitance-Voltage (QSCV) method has been advanced to extract simultaneous Cp and Rp values. Multi-segment voltage stimulus waveforms generate digitized currents from single or parallel DUTs. Resulting current vectors are resolved into Rparallel (Rp) and C parallel (Cp) components using vector analysis methods. We compare QSCV and LCR methods and discuss instrument and modeling issues.	PDF Xplore
8.2	Procedure for Controlling Pad Scrub During High-Temperature Wafer Probing D. Hall, B. Smith, D. Pechonis, M. Nelson, G. Tranquillo1 NXP Semiconductors, Austin, TX, USA 78750 1Celadon Systems, Inc., Burnsville, MN, USA 55337 DOI: 10.1109/ICMTS50340.2022.9898166 ABSTRACT: Stability and control of high-temperature wafer probing was studied. A new procedure was demonstrated that enables control of the probe needle scrub distance at elevated temperatures. Initial scrub measurements were made and compared for three probe card motherboards at 125 °C, 150 °C, and 175 °C. Then, applying the new procedure, scrub distance was measured at 175 °C for the three motherboards over 144 hours of probing. The new procedure enabled control (and thus, minimization) of the probe pad scrub distances.	PDF Xplore

Session 9: Device Characterization

9.1	dGPLVM: A Nonparametric Device Model for Statistical Circuit Simulation K. Shimozato, T. Sato Graduate School of Informatics, Kyoto University, Yoshida-hon-machi, Sakyo, Kyoto 606-8501, Japan DOI: 10.1109/ICMTS50340.2022.9898216 ABSTRACT: In this study, a novel statistical device model, dGPLVM, is proposed. In dGPLVM, device variation is compactly represented using low-dimensional latent variables and temperature dependence can be incorporated. The fitting accuracy of the dGPLVM and the generated device characteristics obtained through sampling in the latent space are validated using the measurement results of commercial power MOSFETs. Verilog-A implementation of the proposed method demonstrates its practicality.	PDF Xplore
9.2	Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers J. van Zoeren, L. K. Nanver Faculty of EEMCS, University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS50340.2022.9898239 ABSTRACT: Two hole-current extraction methods are discussed as potential checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers on n-substrates. Both methods are unaffected by leakage currents related to defects near the junction. The one method is commonly used: the slope of the collector current in a lateral pnp Gummel plot is determined. The validity of this method is limited by series resistance and Early-voltage/punch-through effects related to depletion of the base region. The other method applies a differential measurement to determine a hole spreading current with an ideal slope. This method is not limited by depletion width variations but if the electron-to-hole current-ratio is too high, detrimental parasitic electron currents are induced.	PDF Xplore
9.3	Characterization and Monitoring Platform for Single-Photon Avalanche Diodes in the Development of a Photon-to-Digital Converter Technology S. Parent, F. Vachon, V. Gauthier, A. Paquette, J. Deschamps, T. Rossignol, P. Arsenault, C. Paulin, J. Lemay, N. Roy, M. Côté, D. Dupont, S. Martel, H. Dautet, S. A. Charlebois, J. -F. Pratte Institut Interdisciplinaire d'Innovation Technologique, Université de Sherbrooke, Sherbrooke, Canada DOI: 10.1109/ICMTS50340.2022.9898180 ABSTRACT: This paper reports on a wafer-level test platform for Single-Photon Avalanche Diodes (SPADs) manufactured at Teledyne DALSA (Canada) and designed by Université de Sherbrooke. The platform enables in-foundry end-of-process active testing of SPADs in Geiger-mode, thanks to a dedicated integrated circuit and probe card installed on a wafer prober.	PDF Xplore

Session 10: Novel Device Characterization

10.1	Test Structure of Bi-stable Spring towards TopoMEMS Ising Machine Y. Mita, M. Ezawa, K. Tsuji, E. Lebrasseur, T. Sawamura, S. Tsuboi, A. Mizushima, Y. Ochiai, A. Higo Graduate School of Engineering, The University of Tokyo (UTokyo), Tokyo, Japan DOI: 10.1109/ICMTS50340.2022.9898227 ABSTRACT: Recently, Ising Model attracts much attention for future quantum annealing computer. We are investigating the World's first Topological Micro Electro Mechanical Systems (TopoMEMS) representation of the Ising Model. As the core component, we propose a unique “compress-and-latch” bi-stable spring structure. Two key parameters identified were an initial gap and stress relief structure. Test structures have been designed, fabricated, and parametrically tested. It was experimentally found that there exists a design window to realize 25um-stroke bistable operation with application voltage as low as 9V.	PDF Xplore
10.2	A two-step parameter extraction methodology for graphene field-effect transistors K. Jeppson Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS50340.2022.9898249 ABSTRACT: Accurate device models and parameter extraction methods are of utmost importance for characterizing graphene field-effect transistors and for predicting their performance in circuit applications. For DC characterization, accurate extraction of the transconductance parameter (i.e., low-field mobility) and series resistance is of particular importance. In this paper, methods for extraction of these parameters will be discussed.A first-order mobility degradation model that can be used to separate information about mobility degradation and series resistance for a set of graphene field-effect transistors will also be discussed.	PDF Xplore
10.3	On-Chip Nano Pulse Test Element Group for Analysis of Synaptic Devices T. -G. Ryu, S. -H. Kim, K. -W. Song, H. -J. Shin, Y. -J. An, S. -B. Eadi, H. -M. Kwon1, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejoen, Korea 1Department of Semiconductor Processing Equipment, Semiconductor Convergence Campus of Korea Polytechnics College, Ansung, Korea DOI: 10.1109/ICMTS50340.2022.9898163 ABSTRACT: In this paper, on-chip pulse test element groups (TEGs) were proposed to evaluate the main characteristics of synaptic devices as a function of pulse width and height, especially in nanosecond region. On-chip generation of nanosecond level pulses are highly necessary to evaluate the dependence of synaptic device characteristics on the pulse width and pulse height, because the increase or decrease of current/conductance of synaptic device is a key for neuromorphic application. We demonstrated the performance and the application of the TEGs by integrating and measuring memristors on these TEGs.	PDF Xplore
10.4	Introduction of a Reset MOSFET to Mitigate the Influence of Ionic Movement in Perovskite MOSFET Photodetector Measurements J. Liu, R. Haroldson1, G. Verkhogliadov2, D. Lin3, Q. Gu3, A. A. Zakhidov4, W. Hu5, C. D. Young6 Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson 75080, USA 1Department of Physics, The University of Texas at Dallas, Richardson 75080, USA 2The School of Physics and Engineering, ITMO University, St. Petersburg 197101, Russia 3Department of Electrical and Computer Engineering, North Carolina State Univeristy, Raleigh 27695, USA 4Department of Physics, The University of Texas at Dallas, Richardson, USA 5Department of Laboratory Medicine, Sichuan University, Chengdu 610041, China 6Department of Materials Science and Engineering, Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson 75080, USA DOI: 10.1109/ICMTS50340.2022.9898238 ABSTRACT: A Reset MOSFET is added to a perovskite MOSFET-based photodetector to serve as a current source to mitigate the influence of ionic movement on the performance of the photodetector. With the added MOSFET, the hysteresis is significantly reduced, and the dark current is controllable. The on/off ratio resumes to 106 and an ultrasensitive responsivity (over 80, 000 A/W) is achieved under only 13 nW/cm2 red (665 nm) light intensity.	PDF Xplore

By First Author

5.4	CMOS Platform TEG for Development of High Performance Synaptic Devices Y. -J. An, S. -H. Kim, K. -W. Song, H. -J. Shin, T. -G. Ryu, S. -B. Eadi, H. -M. Kwon1, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejoen, Korea 1Department of Semiconductor Processing Equipment, Semiconductor Convergence Campus of Korea Polytechnics College, Ansung, Korea DOI: 10.1109/ICMTS50340.2022.9898228 HOVER FOR ABSTRACT	PDF Xplore
4.2	Temperature Characterizations of Multi-Unit and Multi-finger Dependencies on AlGaN/GaN Ridge HEMTs H. Aoki, N. Kuroda1, A. Yamaguchi1, K. Nakahara R&D Center, ROHM Co., Ltd, Kyoto 615-8585, Japan 1Core Technology R&D Division, R&D Center, ROHM Co., Ltd, Kyoto 615-8585, Japan DOI: 10.1109/ICMTS50340.2022.9898230 HOVER FOR ABSTRACT	PDF Xplore
3.3	Utilization of Poly Heater Test Structures in the Characterization of Bias Temperature Instability Y. -H. Cheng, M. Cook, D. Allman Corporate Research and Development, East Greenwich, RI 02818, USA DOI: 10.1109/ICMTS50340.2022.9898183 HOVER FOR ABSTRACT	PDF Xplore
6.1	An Evaluation for Quality Inspection of Epitaxial Layer and Heavily-doped 4H-SiC Substrate by Simple Schottky Barrier Diode and MOS Capacitor K. -W. Chu, C. -W. Tseng1, B. -Y. Tsui1, Y. -C. S. Wu, C. -J. Yang2, C. Hsu2 Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C 1Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C 2Innovation Technology Research Center, GlobalWafers Co., Ltd., Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS50340.2022.9898247 HOVER FOR ABSTRACT	PDF Xplore
6.3	Test Measurements for Charge Trapping in Different Polarization Ferroelectric FETs S. Deng, K. Ni, S. K. Kurinec Department of Electrical & Microelectronic Engineering, Rochester Institute of Technology, Rochester, New York 14623, USA DOI: 10.1109/ICMTS50340.2022.9898271 HOVER FOR ABSTRACT	PDF Xplore
1.2	Test Structures for Characterising the Fabrication of Miniature Reference Electrodes C. Dunare, S. Zhang, J. R. K. Marland, A. Tsiamis, P. Sullivan, I. Underwood, J. G. Terry, A. J. Walton, S. Smith1 School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, Edinburgh, Scotland, UK 1School of Engineering, Institute for Bioengineering, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS50340.2022.9898104 HOVER FOR ABSTRACT	PDF Xplore
3.1	Two-pads per electrode in-situ test structure for micron-scale flip-chip bonding reliability of chip-on-chip device Y. Ebihara, A. Mizushima, T. Yoda1, K. Hirakawa1, M. Iwase1, M. Ogasawara1, A. Higo, Y. Ochiai, Y. Mita School of Engineering, The University of Tokyo, Japan 1Laboratory for Future Interdisciplinary Research of Science and Technology, Tokyo Institute of Technology, Japan DOI: 10.1109/ICMTS50340.2022.9898248 HOVER FOR ABSTRACT	PDF Xplore
8.2	Procedure for Controlling Pad Scrub During High-Temperature Wafer Probing D. Hall, B. Smith, D. Pechonis, M. Nelson, G. Tranquillo1 NXP Semiconductors, Austin, TX, USA 78750 1Celadon Systems, Inc., Burnsville, MN, USA 55337 DOI: 10.1109/ICMTS50340.2022.9898166 HOVER FOR ABSTRACT	PDF Xplore
8.1	Issues and advances in rapid Quasi-Static CV for high throughput semiconductor process monitoring M. H. Herman, D. Jang, M. Nagel, B. Morris Parametric Test Group, Advantest America, San Jose, United States DOI: 10.1109/ICMTS50340.2022.9898273 HOVER FOR ABSTRACT	PDF Xplore
5.1	Embedded measurement of the SET switching time of RRAM memory cells F. Jebali, E. Muhr, M. Alayan, M. C. Faye, D. Querlioz1, F. Andrieu2, E. Vianello2, G. Molas2, M. Bocquet, J. M. Portal Aix-Marseille Univ., Marseille, France 1Université Paris-Saclay, 91120 Palaiseau, France 2CEA, LETI, Grenoble, France DOI: 10.1109/ICMTS50340.2022.9898162 HOVER FOR ABSTRACT	PDF Xplore
10.2	A two-step parameter extraction methodology for graphene field-effect transistors K. Jeppson Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS50340.2022.9898249 HOVER FOR ABSTRACT	PDF Xplore
1.4	Combined Machine Learning Techniques For Characteristics Classification and Threshold Voltage Extraction of Transistors H. M. Koçak, J. Mitard1, A. T. Naskali Department of Computer Engineering, Galatasaray University, Istanbul, Turkey 1Compute and Memory Department, IMEC, Leuven, Belgium DOI: 10.1109/ICMTS50340.2022.9898251 HOVER FOR ABSTRACT	PDF Xplore
7.1	DFI Filler Cells -- New Embedded Type of Test Structures for Non-Contact Detection of Electrical Defects on Product Wafers S. Lam, C. Hess, L. Weiland, M. Moe, X. W. Shen, J. Chen, I. De, M. Strojwas, T. Brozek PDF Solutions, Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS50340.2022.9898254 HOVER FOR ABSTRACT	PDF Xplore
2.4	Optimal Test Structures for the Characterization of Integrated Transformers at mm-wave frequencies using the Open/Thru De-embedding Technique M. Lauritano, P. Baumgartner Intel Germany, Neubiberg, Germany DOI: 10.1109/ICMTS50340.2022.9898235 HOVER FOR ABSTRACT	PDF Xplore
2.2	300-GHz Back-Radiation On-Chip-Antenna Measurement with Electromagnetic-Wave-Absorption Sheet S. Lee, K. Katayama1, K. Takano1, M. Fujita2, M. Toyoda2, S. Hara3, I. Watanabe3, A. Kasamatsu3, S. Amakawa1, T. Yoshida1, M. Fujishima1 Inst. of Innovative Research, Tokyo Inst. of Technol., Yokohama, Japan 1Grad. School of Advanced Sci. and Eng., Hiroshima Univ., Higashihiroshima, Japan 2New Business Produce Div., Maxell, Ltd., Otokuni, Japan 3Advanced ICT Research Inst., Nat’l. Inst. of Info. and Comms. Technol., Koganei, Japan DOI: 10.1109/ICMTS50340.2022.9898229 HOVER FOR ABSTRACT	PDF Xplore
7.2	Contact Fail Monitoring with an Epi Resistance Test Structure for 7nm FinFET Product C. H. Lee, B. W. Jeong1, S. Wu, M. Kim1, X. Chen, K. Onishi, C. Manya, L. Anastos, J. Sim, M. Angyal Fabless Foundry Interaction, Processor Product Engineering, IBM Systems, NY 12533-6683 1Samsung Electronics Co. Ltd., Hwasung-City, Gyeonggi-Do, 445-701, Republic of Korea DOI: 10.1109/ICMTS50340.2022.9898262 HOVER FOR ABSTRACT	PDF Xplore
5.2	Statistical Modeling of SRAM PUF Cell Mismatch Shift Distribution After Hot Carrier Injection Burn-In K. Liu, K. Takeuchi1, H. Shinohara2 Information, Production and Systems, Research Center, Waseda University, Kitakyushu, Japan 1Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 2Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan DOI: 10.1109/ICMTS50340.2022.9898258 HOVER FOR ABSTRACT	PDF Xplore
10.4	Introduction of a Reset MOSFET to Mitigate the Influence of Ionic Movement in Perovskite MOSFET Photodetector Measurements J. Liu, R. Haroldson1, G. Verkhogliadov2, D. Lin3, Q. Gu3, A. A. Zakhidov4, W. Hu5, C. D. Young6 Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson 75080, USA 1Department of Physics, The University of Texas at Dallas, Richardson 75080, USA 2The School of Physics and Engineering, ITMO University, St. Petersburg 197101, Russia 3Department of Electrical and Computer Engineering, North Carolina State Univeristy, Raleigh 27695, USA 4Department of Physics, The University of Texas at Dallas, Richardson, USA 5Department of Laboratory Medicine, Sichuan University, Chengdu 610041, China 6Department of Materials Science and Engineering, Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson 75080, USA DOI: 10.1109/ICMTS50340.2022.9898238 HOVER FOR ABSTRACT	PDF Xplore
1.3	Design of Low-Cost Test Structures for Measuring Within-Die Process Skew Variations A. Majumdar, N. Chong AMD Inc., San Jose, CA 95124 DOI: 10.1109/ICMTS50340.2022.9898217 HOVER FOR ABSTRACT	PDF Xplore
5.3	SuperCAST: a full free addressable memory array V. D. Marca, J. Guilleau-Tavernier, P. Laine, F. Melul, M. Bocquet, T. Kempf1, L. Welter1, J. -M. Moragues1, A. Regnier1, J. -M. Portal Aix-Marseille Université, 13397 Marseille, France 1STMicroelectronics, 13106 Rousset, France DOI: 10.1109/ICMTS50340.2022.9898189 HOVER FOR ABSTRACT	PDF Xplore
10.1	Test Structure of Bi-stable Spring towards TopoMEMS Ising Machine Y. Mita, M. Ezawa, K. Tsuji, E. Lebrasseur, T. Sawamura, S. Tsuboi, A. Mizushima, Y. Ochiai, A. Higo Graduate School of Engineering, The University of Tokyo (UTokyo), Tokyo, Japan DOI: 10.1109/ICMTS50340.2022.9898227 HOVER FOR ABSTRACT	PDF Xplore
4.1	Layout-Dependent Vertical and In-Plane Leakage Current Reduction of Organic Thin-Film Transistors by Layer Contact Restriction K. Oshima, K. Kuribara1, T. Sato Graduate School of Informatics, Kyoto University, Yoshida-hon-machi, Sakyo, Kyoto 606-8501, Japan 1National Institute of Advanced Industrial Science and Technology (AIST) DOI: 10.1109/ICMTS50340.2022.9898196 HOVER FOR ABSTRACT	PDF Xplore
9.3	Characterization and Monitoring Platform for Single-Photon Avalanche Diodes in the Development of a Photon-to-Digital Converter Technology S. Parent, F. Vachon, V. Gauthier, A. Paquette, J. Deschamps, T. Rossignol, P. Arsenault, C. Paulin, J. Lemay, N. Roy, M. Côté, D. Dupont, S. Martel, H. Dautet, S. A. Charlebois, J. -F. Pratte Institut Interdisciplinaire d'Innovation Technologique, Université de Sherbrooke, Sherbrooke, Canada DOI: 10.1109/ICMTS50340.2022.9898180 HOVER FOR ABSTRACT	PDF Xplore
6.2	Application of a Test Structure for Minimising Seed Layer Thickness of Electroplated Ferromagnetic Films A. W. S. Ross, C. M. Dover, S. Smith1, J. G. Terry, A. R. Mount2, A. J. Walton School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, Edinburgh, Scotland, UK 1School of Engineering, Institute for Bioengineering, The University of Edinburgh, Edinburgh, Scotland, UK 2School of Chemistry, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS50340.2022.9898250 HOVER FOR ABSTRACT	PDF Xplore
10.3	On-Chip Nano Pulse Test Element Group for Analysis of Synaptic Devices T. -G. Ryu, S. -H. Kim, K. -W. Song, H. -J. Shin, Y. -J. An, S. -B. Eadi, H. -M. Kwon1, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejoen, Korea 1Department of Semiconductor Processing Equipment, Semiconductor Convergence Campus of Korea Polytechnics College, Ansung, Korea DOI: 10.1109/ICMTS50340.2022.9898163 HOVER FOR ABSTRACT	PDF Xplore
3.2	Characterizing Aging Degradation of Integrated Circuits with a Versatile Custom Array of Reliability Test Structures A. Santana-Andreo, P. Martin-Lloret, E. Roca, R. Castro-Lopez, F. V. Fernandez IMSE, CSIC-Universidad de Sevilla, Seville, Spain DOI: 10.1109/ICMTS50340.2022.9898256 HOVER FOR ABSTRACT	PDF Xplore
2.3	Modeling and Verificaion of Millimeter-Wave nMOSFET up to 50 GHz in 180 nm CMOS Technology K. Sekine, K. Takano, Y. Umeda Department of Electrical Engineering, Tokyo University of Science, Chiba, Japan DOI: 10.1109/ICMTS50340.2022.9898222 HOVER FOR ABSTRACT	PDF Xplore
9.1	dGPLVM: A Nonparametric Device Model for Statistical Circuit Simulation K. Shimozato, T. Sato Graduate School of Informatics, Kyoto University, Yoshida-hon-machi, Sakyo, Kyoto 606-8501, Japan DOI: 10.1109/ICMTS50340.2022.9898216 HOVER FOR ABSTRACT	PDF Xplore
4.3	Single Device MOSFET Series Resistance Extraction Methods: Comparison Between Newer and Older K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, JAPAN DOI: 10.1109/ICMTS50340.2022.9898270 HOVER FOR ABSTRACT	PDF Xplore
1.1	Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization M. Udo, M. Islam1, H. Onodera2 Graduate School of Informatics, Kyoto University, Yoshida-honmachi, Sakyo-ku, Kyoto 606-8501, JAPAN 1Graduate School of Engineering, Kyoto University, Kyoto Daigaku Katsura, Nishikyo-ku, Kyoto 615-8510, JAPAN 2Faculty of Informatics, Osaka Gakuin University, 2-36-1 Kishibe-Minami, Suita 564-8511, JAPAN DOI: 10.1109/ICMTS50340.2022.9898111 HOVER FOR ABSTRACT	PDF Xplore
2.1	S-Parameter Measurement and EM Simulation of Electronic Devices towards THz frequency range C. Yadav, S. Fregonese1, M. Cabbia1, M. Deng1, M. De Matos1, T. Zimmer1 National Institute of Technology Calicut, Kozhikode, Kerala, India 1IMS Laboratory, University of Bordeaux, France DOI: 10.1109/ICMTS50340.2022.9898233 HOVER FOR ABSTRACT	PDF Xplore
9.2	Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers J. van Zoeren, L. K. Nanver Faculty of EEMCS, University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS50340.2022.9898239 HOVER FOR ABSTRACT	PDF Xplore