IEEE International Conference on Microelectronic Test Structures

ICMTS 2020 Program

2020 Program Booklet

By Session

Experimental Set-Up For Novel Energy Efficient Charge-based Resistive RAM (RRAM) Switching
P. Trotti, G. Pillonet, G. Molas, S. Oukassi, E. Nowak
CEA, LETI, Univ. Grenoble Alpes, Grenoble, France
DOI: 10.1109/ICMTS48187.2020.9107936
ABSTRACT: This work explores a new method to reduce the energy consumption during the writing of process-spread resistive-based memories (RRAM), based on setting an initial electrical charge into a writing capacitor rather than applying constant voltage over a fixed time. By connecting a charged capacitor (constant charge source, CQS) to a RRAM device, we benefit of a lower energy requirement for setting the memory cells, for a given success rate. We propose a RRAM set circuit model, where switching conditions were extrapolated from experimental data. We then benchmark our proposed writing procedure with respect to the constant voltage source (CVS) scheme. Finally, we give experimental proof of concept by realization of a circuit interface that integrates the CQS protocol and is connected to a RRAM load. Results support the fact that setting the initial charge is a better choice to efficiently control the variability of the filamentary process in RRAM.

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Session 1: Advanced Measurement Techniques

1.1	Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics S. Nishizawa, K. Ito¹ Faculty of Engineering, Fukuoka University, 8-19-1, Nanakuma, Jyonan-Ku, Fukuoka, JAPAN ¹Graduate School of Science and Engineering, Saitama University DOI: 10.1109/ICMTS48187.2020.9107931 ABSTRACT: Extraction method of process variation is proposed. Process monitor circuits are widely used for the extraction of process variation, however adding special purpose circuit increase the silicon area. Usually, silicon chips are tested electrically and functionally after the fabrication. IDDQ test is an electrical test which measures leakage current and find the fault in the target chip. Scan-test is a functional test which inputs and measures the internal signal vector using scan-flip-flop. We propose to an extraction method of process variation utilizing IDDQ test and retention characteristics of scan-flip-flop. This method enables process variation extraction without any extra process monitor circuit. Test structures are implemented into silicon chips and result shows global variation shift is extracted as threshold voltage shift.	PDF Xplore
1.2	Calibration of CBCM Measurement Hardware B. Smith, E. Onyegam, D. Hall, B. Verzi NXP Semiconductors, Austin, Texas, USA DOI: 10.1109/ICMTS48187.2020.9107913 ABSTRACT: Charge-based capacitance (CBCM) measurements require precise measurement of AC currents. This work describes a test structure that produced periodic pulses of current to mimic a CBCM circuit. It was measured in both wafer form on a parametric test system and in package form on a functional test system. Average currents from 600 pA to $10 \mu \mathrm{A}$ at frequencies between 290 kHz and 2.6 GHz were measured on both systems. The parametric tester was shown to be capable of measuring AC currents across that entire range of currents and frequencies. The functional tester was capable at high frequencies, but showed measurement errors at lower currents, seemingly in agreement with its DC current measurement specifications. This technique could be used to validate the limits of any test hardware prior to designing an AC circuit.	PDF Xplore

Session 2: Parametric Tests

2.1	Standardization of Specific Contact Resistivity Measurements using Transmission Line Model (TLM) S. Grover, S. Sahu, P. Zhang¹, K. O. Davis², S. K. Kurinec Rochester Institute of Technology, USA, Rochester, New York ¹Michigan State University, USA, East Lansing, MI ²University of Central Florida, USA, Orlando, FL DOI: 10.1109/ICMTS48187.2020.9107911 ABSTRACT: The transmission line model (TLM) method is most commonly used to determine the specific contact resistivity of metal -semiconductor contacts. Inconsistencies have been observed in the literature in reported values of specific contact resistivities in devices ranging in their dimensions, e.g between those in nm-μm scaled integrated circuit devices and mm-cm scaled photovoltaic devices indicating that the contact resistivity extraction may depend on dimensions. Therefore, TLM test geometries need to be specified. This paper discusses the effect of the TLM width on extracted transfer length. The effect of pad length is investigated using the Exact Field Solution model. Linear and circular TLM test structures were created and tested on Al, NiSi/Al on p+n and n+p substrates. Specific contact resistivitiy values agree in both wide linear and circular TLM methods. However, sheet resistance values differ.	PDF Xplore
2.2	Automated Generation, Fabrication and Measurement of Parametric Test Structures for Rapid Prototyping Using Optical Maskless Lithography P. Sullivan, A. Tsiamis, M. Rondé, A. J. Walton, S. Smith, J. G. Terry The School of Engineering, The University of Edinburgh, UK DOI: 10.1109/ICMTS48187.2020.9107929 ABSTRACT: This paper describes the use of open-source electronic design automation tools, which have been developed and adapted for maskless lithography, to enable automation of the design, layout and measurement of parametric test structures. Two test structures are presented as case studies for characterisation of microelectronic and micro-electromechanical systems technologies using electrical and profilometry measurements respectively.	PDF Xplore
2.3	Characterization of parametric mismatch attributable to plastic chip encapsulation H. Tuinhout, A. Damian¹, A. Z. -v. Duijnhoven CTO / Modeling, Characterization & SPICE Libraries, Nijmegen NXP Semiconductors, Eindhoven, Netherlands ¹Package Core Technology, Nijmegen NXP Semiconductors, Netherlands DOI: 10.1109/ICMTS48187.2020.9107916 ABSTRACT: This paper uses a high-spatial-resolution test structure and associated high-precision data analysis approach to characterize deterministic and random performance changes of semiconductor devices induced by local mechanical stress variations in plastic encapsulated chips. The results quantify substantial systematic effects caused by lead frame mounting and wire bonding as well as subtle random variability occurrences attributable to the spatial distribution of silica particles in the molding compound. The occurrence of these random silica particle effects is proven by comparing results of unprotected chips to results of those that received a chipcoat gel stress buffer layer prior to plastic chip encapsulation.	PDF Xplore
2.4	Extraction of Ultra-Low Contact Resistivity by End-Resistance Method B. -Y. Tsui, Y. -H. Lee, D. -Y. Wu, Y. -J. Lee¹, M. -Y. Li¹ Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R. O. C. ¹Taiwan Semiconductor Research Institute, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS48187.2020.9107910 ABSTRACT: Accuracy of extracting ultra-low contact resistivity by the end-resistance method is evaluated. As the contact length becomes smaller than the transfer length, the end-resistance approaches the contact resistance, and the error decreases with the reduction of contact length and contact resistivity. The contact resistivity lower than $10^{-9}\Omega-\mathrm{c}\mathrm{m}^{2}$ can be extracted with accuracy lower than $3\times 10^{-10}\Omega-\mathrm{c}\mathrm{m}^{2}$. This end-resistance method is verified by self-aligned transmission line model test structure. Statistic analysis of the distribution of contact resistance and the uniformity of the contact interface are also demonstrated.	PDF Xplore

Session 3: Noise Measurements

3.1	Area-Efficient and Bias-Flexible Inline Monitoring Structure for Fast Characterization of RTN and Transistor Local Mismatch in Advanced Technologies A. Jayakumar, N. Chan, L. Pirro, O. Zimmerhackl, M. Otto, T. Kleissner, J. Hoentschel GLOBALFOUNDRIES Fab1 LLC & Co.KG, Wilschdorfer Landstrasse 101, Dresden, Saxony, Germany DOI: 10.1109/ICMTS48187.2020.9107935 ABSTRACT: An improved set of Scribe Line Monitors (SLMs) with high device densities have been designed for inline monitoring of Random Telegraph Noise (RTN) and transistor local mismatch. This infrastructure offers increased statistics from measurement on a single wafer with parallel Device Under Test (DUT) testing capability thereby having an efficient testing time. The characterization results from engineering silicon are presented in this paper.	PDF Xplore
3.2	Test Structures for Noise Reduction of Fully Depleted-Silicon on Insulator p-Type Tunneling FET Using Channel Orientation H. -D. Song, H. -S. Song, S. B. Eadi, H. -W. Choi, G. -W. Lee, H. -D. Lee Department of Electronics Engineering, Chungnam National University, 99 Daehak-ro, Yuseong-gu, Daejeon DOI: 10.1109/ICMTS48187.2020.9107915 ABSTRACT: The focus of this study was on the effect of channel orientation on tunneling field effect transistors (TFET). The proposed test patterns were rotated basic TFETs built on silicon on insulator substrates. The patterns were rotated in the (210) and (110) directions in the layout of the test setup. The DC characteristics, subthreshold slopes, and noise were measured. The results show that the on-current and subthreshold slope of the TEFTs were improved up to 8.8 times and 49.6%, respectively. The low-frequency noise was also enhanced approximately 100 times. The reason for the improvements appears to be that the reduced effective tunneling length increases tunneling probability.	PDF Xplore
3.3	Increased Delay Variability due to Random Telegraph Noise under Dynamic Back-gate Tuning M. Udo, K. Murakami, A. K. M. M. Islam¹, H. Onodera Department of Communications and Computer Engineering, Kyoto University Yoshida-honmachi, Sakyo-ku, Kyoto, JAPAN ¹Department of Electrical Engineering, Kyoto University Kyoto Daigaku Katsura, Nishikyo-ku, Kyoto, JAPAN DOI: 10.1109/ICMTS48187.2020.9107919 ABSTRACT: Dynamic back-gate voltage tuning is an effective technique for run-time optimization of energy consumption in an LSI. In this paper, we present our observation that variability due to RTN under back-gate voltage tuning increases significantly at low voltage operation. We investigate on the mechanism of the increase of variability and its impact on circuit performance using a ring oscillator based test chip fabricated in a 65 nm FDSOI process. Measurement results imply that additional care needs to be taken for circuits under dynamic voltage tuning.	PDF Xplore

Session 4: MEMS Device Characterisation

4.1	Automated Wafer-Level Characterisation of Electrochemical Test Structures for Wafer Scanning I. Schmueser, C. L. Mackay¹, F. Moore, K. Doherty, J. P. Elliott¹, A. R. Mount¹, A. J. Walton, S. Smith, J. G. Terry School of Engineering, The University of Edinburgh, Edinburgh, U.K. ¹School of Chemistry, The University of Edinburgh, Edinburgh, U.K. DOI: 10.1109/ICMTS48187.2020.9107903 ABSTRACT: This paper presents an automated system for the electrochemical characterization of micro-scale test structures at the wafer level, with the objective to identify good devices suitable for full characterization and packaging. The integration of the onwafer characterization enables an initial quality assessment of the devices prior to packaging and thus minimizes the packaging of faulty sensors. The prototype system integrates the essential elements for automated on-wafer in-line electrochemical systems characterization, thereby confirming the suitability of this approach for implementation on commercial automated probers, which are generally available for parametric testing. The system’s capabilities are demonstrated for a standard three-electrode cell design typically employed in electrochemical sensing applications. Finally, the system’s potential is established by wafer mapping the performance of electrochemical microelectrode devices through integration with a semi-automatic probe station.	PDF Xplore
4.2	Verification and Induction Method for Low Frequency Response Failure Modes in Acoustic MEMS G. Hantos, D. Marc P.Y. School of Engineering & Physical Sciences Research Institute of Sensors, Signals and System, Heriot-Watt University, Edinburgh, Scotland DOI: 10.1109/ICMTS48187.2020.9107925 ABSTRACT: In this paper we present a novel verification and induction method for low frequency response failure modes in MEMS microphones. Response from the device is captured before and after the occurrence of a defect present on the diaphragm of the microphone and induced by focus ion beam machining. The deviation in the frequency response of the microphone shows a good agreement with analytical results.	PDF Xplore
4.3	A Rapid, Reliable and Less-destructive On-chip Mass Measurement for 3D Composite Material Testing Microstructures G. Hwang, C. David¹, A. Paris¹, D. Decanini¹, A. Mizushima², Y. Mita LIMMS-CNRS, Institute of Industrial Science, University of Tokyo, Japan ¹C2N-CNRS, University Paris-Sud, University Paris-Saclay, Palaiseau, France ²VLSI Design and Education Center, The University of Tokyo, 2-11-16, Yayoi, Bunkyo-ku, Tokyo, Japan DOI: 10.1109/ICMTS48187.2020.9107932 ABSTRACT: Mass measurements of complex three-dimensional microstructures are essential to the design and development of microsystems. However, the mass measurements of such microstructures require several manipulation steps which are not well controlled. We have demonstrated a rapid, reliable and less-destructive on-chip mass measurement method by incorporating with AFM micromanipulation. It is based on AFM pick-measure-place micromanipulation using Van der Waals attraction and the mass measurement by resonant frequency shift. The measurement sensitivity revealed to be 25 Hz/pg and it could be promising to characterize MEMS with complex geometries and composite materials.	PDF Xplore
4.4	Test structure and measurement system for characterising the electrochemical performance of nanoelectrode structures I. Schmueser, E. O. Blair, Z. Isiksacan, Y. Li, D. K. Corrigan¹, A. A. Stokes, J. G. Terry, A. R. Mount¹, A. J. Walton School of Engineering, The University of Edinburgh, Edinburgh, UK ¹School of Chemistry, The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS48187.2020.9107930 ABSTRACT: This paper presents a complete test structure and characterisation system for the evaluation of nanoelectrode technology. It integrates microfabricated nanoelectrodes for electrochemical measurements, 3D printing and surface tensionconfined microfluidics. This system exploits the inherent analytical advantages of nanoelectrodes that enables their operation with small volume samples, which has potential applications for onwafer measurements.	PDF Xplore

Session 5: Materials Characterization

5.1	Multiscale modeling of CeO2/La2 O3 stacks for material/defect characterization B. Dianat, A. Padovani¹, L. Larcher¹ Department of Sciences and Method for Engineering, University of Modena and Reggio Emilia Via Amendola 2, Reggio Emilia, Italy ¹Applied Materials - MDLx Italy R&D Via Meuccio Ruini 74/L, Reggio Emilia, Italy DOI: 10.1109/ICMTS48187.2020.9107922 ABSTRACT: Presence of defects in high-k dielectric materials will affect device’s electrical properties, thus, defect/material characterization is of great importance. We present a simulation-based methodology relying on an accurate description of charge trapping and transport that is useful to extract relevant information on material and defect characteristics. This methodology was applied to cerium oxide and lanthanum oxide high-k dielectric materials and as a result, material properties alongside defect characteristics were extracted. Consequently, main charge conduction mechanism was identified to be trap-assisted tunneling (TAT).	PDF Xplore
5.2	Electrical and optical localisation of leakage current and breakdown point in SiOC:H low-k dielectrics M. Vidal-Dhô, Q. Hubert, P. Gonon¹, B. Pelissier¹, P. Lentrein, P. Ray, J. -M. Moragues, P. Fornara STMicroelectronics, Rousset, France ¹LTM CNRS, Grenoble, France DOI: 10.1109/ICMTS48187.2020.9107909 ABSTRACT: This paper presents a novel methodology to observe the leakage current origin in SiOC:H low-$\kappa$ intermetallic dielectric as well as a method to localise electrically the breakdown point in usual comb/serpentine/comb structures. Our results indicate that high leakage current is a consequence of a global moisture-induced SiOC:H dielectric modification and demonstrate that EMMI observations of such leakage current is possible. Besides, we have disclosed and validated a fast electrical breakdown localisation method fully compatible with automated test steps such as Parametric Test to track eventual weaknesses in reliability structures for instance.	PDF Xplore
5.4	OxRAM BER Scaling Trends on 4 kb Mixed-Diameter Test Vehicle J. Sandrini, C. Cagli, L. Grenouillet, N. Castellani, V. Meli, F. Gaillard CEA-LETI, Minatec Campus, 17 rue des Martyrs, Grenoble Cedex 9, France DOI: 10.1109/ICMTS48187.2020.9107927 ABSTRACT: In this work we present a 4 kb OxRAM test structure which includes devices of diameter ranging from 30 nm to 170 nm. Thanks to a quasi-continuous range of cell sizes, this matrix allows to evaluate the impact of aggressive cell scaling over several performance metrics within the same test vehicle. Hereafter we study mainly the endurance results. We report how the High Resistive State increases by reducing the device size, and how this value drifts toward higher resistances differently according to the OxRAM area. Moreover, we discuss how smaller cells show a lower endurance, and how dual-bit cell configurations could compensate for these effects at the cost of doubling the dedicated area. We finally demonstrate that dual-bit cells allow a 10x reduction of the bit error rate compared to single cells of equivalent area.	PDF Xplore
5.5	Coaxial Circular Test Structure Applicable to both Ohmic and Schottky Characteristics for ZnO/Si Heterojunctions Assessment N. Miyazawa, N. Usami, H. Wang¹, T. Kubo¹, H. Segawa¹, Y. Mita, A. Higo² Department of Electrical Engineering and Information Systems, The University of Tokyo ¹Research Center for Advanced Science and Technology, The University of Tokyo ²Systems Design Lab, School of Engineering, The University of Tokyo DOI: 10.1109/ICMTS48187.2020.9107928 ABSTRACT: Characterizing junction is essential in new devices research. We are investigating a hybrid infrared-sensitive opto-electronic device on silicon-based large scale integrated circuits, among others, PbS colloidal quantum dots/ZnO/Si hybrid IR detector. To assess such new materials we propose a coaxial circular test structure. The structure is composed of common-central inner (circular) and outer (doughnut) electrodes. In addition to traditional Circular TLM (CTLM) test structure, which was used for ohmic contact, the junction type (ohmic or Schottky) can be identified and quantitatively be analyzed by measuring various gaps and surface areas of the proposed structure (Coaxial CTLM, CCTLM). The measurement using test structure on our n-type ZnO / n-type Si heterojunction sample revealed that the junction was Schottky type, which was opposite to our expectation.	PDF Xplore

Session 6: MEMS Process Characterization

6.1	A nondestructive analysis method for the frontside-release process of thermal sensors C. Liu, J. Fu, Y. Hou, R. Liu¹, Q. Zhou, D. Chen Key Laboratory of Microelectronic Device & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China ¹Wuxi Innovation Center for Internet of Things, Jiangsu Wuxi, China DOI: 10.1109/ICMTS48187.2020.9107917 ABSTRACT: Thermal sensors always have suspended structure to improve their performance. Frontside-release process is a crucial technology to fabricate suspended structure. It is of great importance to monitor the release states; however, the traditional microscope observations are destructive. In this paper, a nondestructive analysis method for the frontside-release process by analyzing the equivalent thermal conductance of thermal sensor is proposed. The measured equivalent thermal conductances of IR FPAs are consistent with the theoretical analysis results, which verifies the feasibility of this method.	PDF Xplore
6.2	Drop-in test structure chip to visualize residual stress of Ru/Cu film grown by atomic layer deposition and supercritical fluid deposition N. Usami, E. Ota¹, A. Higo¹, T. Momose², Y. Mita Department of Electrical Engineering and Information Systems (EEIS), The University of Tokyo ¹Systems Design Lab. (d.lab), School of Engineering, The University of Tokyo ²Department of Materials Engineering, The University of Tokyo DOI: 10.1109/ICMTS48187.2020.9107904 ABSTRACT: We propose a drop-in test structure chip to evaluate residual stress. The structure was applied to evaluate supercritical fluid deposition (SCFD) Cu film over atomic layer deposition (ALD) Ru/TiO 2 film. In an early development stage of such emerging technology, researchers make experiments with a small sample chip in a small chamber. Small chips make classical stress evaluation methods such as wafer curvature radius measurement inappropriate due to high chip stiffness. We propose to “dropin” altogether the sample chip and an additional tiny test chip equipped with free-standing MEMS test structure. The MEMS directly visualizes stress of the deposited material for both tensile and compressive ones. Researchers can continue the device fabrication process on the sample chip while obtaining stress information of the deposited layer by test structure chip. In this paper, in-plane rotating stress sensors were utilized for stress visualization. We proceeded SCFD with two different conditions. The results revealed that SCFD Cu film had tensile stress at the low-temperature condition and compressive stress at the hightemperature condition.	PDF Xplore
6.3	Microheater isolation characterisation to aid the optimisation of a MEMS Leidenfrost engine A. Buchoux, P. Agrawal¹, G. G. Wells¹, R. Ledesma-Aguilar¹, A. J. Walton, J. G. Terry, G. Mchale¹, K. Sefiane, A. A. Stokes School of Engineering, The University of Edinburgh, Edinburgh, UK ¹Faculty of Engineering & Environment, Northumbria University Newcastle upon Tyne, UK DOI: 10.1109/ICMTS48187.2020.9107902 ABSTRACT: This paper reports on the implementation of test structures to characterize the design of a microheater that facilitates localized heating to power a Leidenfrost micro-engines. The test structures are designed to characterize the effect on heat transfer of trenches etched into the silicon substrate. With no trench, the temperature difference is $\triangle \mathrm{T}=11.9$ oC. The temperature measured across the 412 $\mu \mathrm{m}$ deep “long” trench was 43.6 °C while it was 40.4 °C for the “short” trench. The results show that increasing the depth of the trench increases the temperature difference across the trench $(19.9{}^{\circ}\mathrm{C}$ increase for going from 73 $\mu \mathrm{m}$ to 412 $\mu \mathrm{m}$, for the “short” channel) while the length of the trench has a much less significant effect $(3.2{}^{\circ}\mathrm{C}$ increase from “short” to “long” trench, for a depth of 412 $\mu \mathrm{m})$. The test structure measurements agreed well with simulation results confirming the validity of using computer aided design as an integral part in the development of microheater designs.	PDF Xplore
6.4	Test Structure for Measuring the Selectivity in Vapour Etch Processes M. Rondé, A. J. Walton, J. G. Terry School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, UK DOI: 10.1109/ICMTS48187.2020.9107934 ABSTRACT: Etch selectivity between layers is critical in the fabrication of microelectronics and microsystems. This is particularly true in the case of isotropic gas/vapour etching methods used to release free standing structures through the selective etching of sacrificial layers. Commonly used structural materials have been reported to be largely inert when exposed to a given vapour etchant, indicating high selectivity when measured against typical sacrificial layers. However, there is growing evidence that these structural layers are actually etched at an enhanced rate if they are located in the proximity of the sacrificial layer being removed. Hence, removal rates given in the literature that have resulted from measurements of layers that have been etched in isolation can no longer be trusted to characterize critical etch processes in device fabrication. In this paper, a test structure is reported that enables a far more accurate determination of the etch selectivity between sacrificial and structural materials. The method is demonstrated by a XeF2 vapour etch of a polysilicon sacrificial layer located above a silicon nitride structural layer. A dataset is presented for the polysilicon and silicon nitride layers, which shows a selectivity of 5:4.	PDF Xplore

Session 7: RF Device Characterization

7.1	Novel Statistical Modeling and Parameter Extraction Methodology of Cutoff Frequency for RF-MOSFETs C. Tanaka, Y. Iguchi, A. Sueoka, S. Yoshitomi Memory Division, Kioxia Corporation 2-5-1, Kasama, Sakae-ku, Yokohama, Japan DOI: 10.1109/ICMTS48187.2020.9107914 ABSTRACT: The cutoff frequency fluctuation in RF-MOSFET has been investigated. Detailed analysis for capacitance fluctuation as well as the extraction of an intrinsic MOSFET parameter were performed. The extracted process parameters were verified by the framework of effective mobility. The global statistical model of cutoff frequency was successfully developed in terms of capacitance fluctuation, considering intrinsic (channel and bulk charge) and extrinsic (overlap and fringe) capacitance components separately and identifying the major variability sources for cutoff frequency by using extracted parameter.	PDF Xplore
7.2	Influence of series resistance on the experimental extraction of FinFET noise parameters A. Tataridou, G. Ghibaudo, C. Theodorou IMEP-LAHC Univ. Grenoble Alpes, Univ. Savoie Mont Blanc CNRS, Grenoble INP, Institute of Engineering Univ. Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS48187.2020.9107908 ABSTRACT: In this paper we demonstrate for the first time how the series resistance of an advanced CMOS device, such as the FinFET, can lead to an incorrect extraction of low-frequency noise parameters. In particular, the use of the carrier number fluctuations with correlated mobility fluctuations model is shown to be very sensitive to the transistor series resistance. We demonstrate how the classic fitting methods can lead to an underestimated value in the extraction of the mobility fluctuations factor $\Omega$. Furthermore, we present an original method for suppressing this effect, by taking advantage of the series resistance immune Y-function.	PDF Xplore
7.3	Comparison of nMOSFET Structures for Millimeter-Wave Frequencies in 0.18-μm CMOS technology T. Hagiwara, N. Yamaki, K. Takano, Y. Umeda Department of Electrical Engineering, Tokyo University of Science, Yamazaki, Chiba, Japan DOI: 10.1109/ICMTS48187.2020.9107912 ABSTRACT: We present two nMOSFET structures with the high maximum oscillation frequency (fmax) in 1P5M 0.18-$\mu$m CMOS technology to use it for millimeter-wave applications. One is a compact-type structure, and another is a round-table-type structure. By reducing their parasitics, we achieve the fmax of 95 GHz, which is approximately 2 times or more compared to that of the conventional structure. It is shown that the fmax of the round-table-type structure is approximately 10 GHz higher than that of the compact-type structure.	PDF Xplore
7.4	Investigation of Test Structures for the Characterization of Very Fast Electro Static Discharge Events M. Lauderdale, E. Onyegam, S. Ruth, A. Gerdemann NXP Semiconductors, Austin, Texas, USA DOI: 10.1109/ICMTS48187.2020.9107924 ABSTRACT: New wafer technologies and chip design requirements are increasingly susceptible to damage from smaller Electro Static Discharge events (ESD). A new method is sought to evaluate ESD risk posed by processing equipment and the effectiveness of proposed upgrades. This paper proposes and investigates a packaged test structure designed to measure ESD events. The test chip would run in the place of production parts during equipment and package level process evaluations. A design is proposed, developed and preliminary test results demonstrating feasibility are shown.	PDF Xplore
7.5	Application of Broadband RF Metrology to Integrated Circuit Interconnect Reliability Analyses: Monitoring Copper Interconnect Corrosion in 3D-ICs P. K. Amoah, J. Perez, Y. S. Obeng Nanoscale Device Characterization Division, Physical Measurement Laboratory, National Institute of Standards and Technology, 100 Bureau Drive, Gaithersburg, MD DOI: 10.1109/ICMTS48187.2020.9107926 ABSTRACT: In this paper we describe the application of highfrequency electromagnetic wave (in microwave frequency / radio frequency (RF in the range, i.e., 3 kHz - 300 GHz) based techniques to probe material and structural changes that occur in integrated circuits. These techniques fall under the general area of “Broadband Dielectric Spectroscopy”. In this paper, we describe corrosion of the redistribution layer (RDL), required for the implementing 3-D integrated circuits (3D-ICs), during hightemperature storage. As an illustration of our techniques, we use the RF signal loss between ports 1 and 2 on a typical vector network analyzer (i.e., RF insertion loss, S21), to monitor the oxidation of the RDL copper interconnects. We compare the RF signal loss results to the direct current-resistance that was measured simultaneously with the S21. Using electrodynamic simulations, partition the RF signal loss in corroded copper interconnects, and discuss the significance of the roughness at the air-copper oxide interface.	PDF Xplore

Session 8: MOSFET characterization

8.1	Anomalous Scaling of Parasitic Capacitance in FETs with a High-K Channel Material A. E. M. Smink, M. J. de Jong, H. Hilgenkamp, W. G. van der Wiel, J. Schmitz MESA + Institute for Nanotechnology, University of Twente, Enschede, AE, The Netherlands DOI: 10.1109/ICMTS48187.2020.9107901 ABSTRACT: We investigate the operation of FETs with a high-K channel material, SrTiO3, (K=300). The transistors show low-leakage, high-capacitance operation with a sub-nm equivalent oxide thickness, in line with expectations. In depletion however, the gate-source capacitance appears to have an unusual 1/3power dependence on the device length and width. This awkward scaling behaviour is analyzed in detail in this paper and possible consequences for SrTiO3 devices and related 2D-material transistors are discussed. It is argued to relate to the high-permittivity channel. This high permittivity is further experimentally shown to result in strong short-channel effects in $10-\mu \mathrm{m} -$long FETs, in spite of the highly scaled equivalent oxide thickness, when the operation temperature is lowered to 4.2 K.	PDF Xplore
8.2	Comparison of Extraction Methods for Threshold Voltage Shift in NBTI Characterization Y. -H. Cheng, M. Cook, C. Kendrick Corporate Research and Development, N Semiconductor 1900 South County Trail, East Greenwich, RI, USA DOI: 10.1109/ICMTS48187.2020.9107918 ABSTRACT: Negative bias temperature instability (NBTI) is a major concern for CMOS reliability. In this paper extraction methods for threshold voltage shift from drain current versus gate voltage transfer curve and from single drain current value in NBTI characterization of PMOS 3.3 V device in a 180 nm CMOS process were compared with good agreement from ultra-fast measurements at microsecond time scale. The analysis provides validation methodology of spot drain current measurement for fast determination of threshold voltage shift in NBTI characterization for the specific technology and device. After validation, spot current method can be applied to standard testers as well as test systems with fast measurement capabilities.	PDF Xplore
8.3	Integrated Variability Measurements of 28 nm FDSOI MOSFETs down to 4.2 K for Cryogenic CMOS Applications B. C. Paz, L. L. Guevel, M. Cassé, G. Billiot, G. Pillonnet, A. Jansen¹, S. Haendler², A. Juge², E. Vincent², P. Galy², G. Ghibaudo, M. Vinet, S. d. Franceschi¹, T. Meunier, F. Gaillard MINATEC Campus, CEA-Leti, Université Grenoble Alpes, Grenoble, France ¹CEA-IRIG, Université Grenoble Alpes, Grenoble, France ²STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS48187.2020.9107906 ABSTRACT: Mismatch performance of 28 nm FDSOI technology is electrically characterized at low temperatures using integrated on-chip addressing for a matrix of transistors. The first statistical results ever published on FDSOI variability at 4.2 K provide valuable information for future compact transistor modeling in cryogenic circuit design. Slight increase of the threshold voltage mismatch is observed at low temperature. Nevertheless, the suppression of fluctuations in the random distribution of dopants for the fully-depleted transistor channel leads to a smaller threshold voltage variability for FDSOI at 4.2 K compared to advanced Bulk technology at room temperature.	PDF Xplore

Session 9: Optoelectronic Device Characterization

9.1	Comparison of cut-back method and optical backscatter reflectometry for wafer level waveguide characterization A. Peczek, C. Mai¹, G. Winzer¹, L. Zimmermann¹ IHP Solutions Gmb, Im Technologiepark 25, Frankfurt Oder, Germany ¹IHP, Im Technologiepark 25, Frankfurt Oder, Germany DOI: 10.1109/ICMTS48187.2020.9107905 ABSTRACT: The optimum optical characterization method suitable for wafer level waveguide testing is an important issue for silicon photonic methodology. In this paper we focus on comparing the two most widespread measurement techniques: cut-back and optical backscatter reflectometry.	PDF Xplore
9.2	Diode design for studying material defect distributions with avalanche-mode light emission M. Krakers, T. Knezevic, K. M. Batenburg, X. Liu, L. K. Nanver MESA+ Institute, Faculty of EEMCS, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS48187.2020.9107933 ABSTRACT: Avalanche-mode visual light emission in Si diodes is shown to be useful for rapid assessment of the origin of non-ideal currents. In the test structure design, it was important to consider the breakdown-voltage distribution, diode size and contact positioning to obtain light-spot appearances at positions related to bulk defect distributions.	PDF Xplore
9.3	Experimental and simulation analysis of carrier lifetimes in GaAs/AlGaAs Avalanche Photo-Diodes F. Driussi, A. Pilotto, D. De Belli, M. Antonelli¹, F. Arfelli², G. Biasiol³, G. Cautero¹, R. H. Menk¹, C. Nichetti¹, L. Selmi⁴, T. Steinhartova², P. Palestri DPIA, Università degli Studi di Udine, Udine, Italy ¹Elettra-Sincrotrone Trieste S.C.p.A, Area Science Park Basovizza, Trieste, Italy ²Department of Physics, Università di Trieste, Trieste, Italy ³IOM CNR, Laboratorio TASC, Area Science Park Basovizza, Trieste, Italy ⁴Department of Medical Imaging, University of Saskatchewan, Saskatoon, Canada DOI: 10.1109/ICMTS48187.2020.9107920 ABSTRACT: Extensive experimental characterization and TCAD simulation analysis have been used to study the dark current in Avalanche Photo-Diodes (APDs). The comparison between the temperature dependence of measurements and simulations points out that SRH generation/recombination is responsible for the observed dark current. After the extraction of the carrier lifetimes in the GaAs layers, they have been used to predict the APD collection efficiency of the photo-generated currents under realistic operation conditions and as a function of the photogeneration position inside the absorption layer.	PDF Xplore
9.4	Test Setup Optimization and Automation for Accurate Silicon Photonics Wafer Acceptance Production Tests C. B. Sia, T. L. Yap¹, A. Sasidharan¹, J. H. Tan¹, R. Chen¹, J. Leo¹, S. L. Tan¹, G. C. Man¹ FormFactor Singapore Pte. Ltd, 30 Marsiling Industrial Estate Rd 8, #05-02, Singapore ¹GLOBALFOUNDRIES Singapore, 60 Woodlands Industrial, Park D Street 2, Singapore DOI: 10.1109/ICMTS48187.2020.9107907 ABSTRACT: Implementing energy-efficient optical transceiver modules with silicon photonics (SiPh) and 3DIC technologies will help alleviate the increasing energy consumption for hyperscale data centers. To facilitate effective 3DIC heterogenous integration of these photonics integrated circuits for optical transceivers, high precision, repeatable and reliable SiPh wafer acceptance tests are essential and vital. This paper successfully demonstrated incident angle optimization for optical wafer tests as well as evaluation of a fully automatic SiPh wafer test architecture that is accurate and dependable, achieving excellent test correlations between passive and active devices designed with grating-couplers and edge couplers.	PDF Xplore

By First Author

7.5	Application of Broadband RF Metrology to Integrated Circuit Interconnect Reliability Analyses: Monitoring Copper Interconnect Corrosion in 3D-ICs P. K. Amoah, J. Perez, Y. S. Obeng Nanoscale Device Characterization Division, Physical Measurement Laboratory, National Institute of Standards and Technology, 100 Bureau Drive, Gaithersburg, MD DOI: 10.1109/ICMTS48187.2020.9107926 HOVER FOR ABSTRACT	PDF Xplore
6.3	Microheater isolation characterisation to aid the optimisation of a MEMS Leidenfrost engine A. Buchoux, P. Agrawal¹, G. G. Wells¹, R. Ledesma-Aguilar¹, A. J. Walton, J. G. Terry, G. Mchale¹, K. Sefiane, A. A. Stokes School of Engineering, The University of Edinburgh, Edinburgh, UK ¹Faculty of Engineering & Environment, Northumbria University Newcastle upon Tyne, UK DOI: 10.1109/ICMTS48187.2020.9107902 HOVER FOR ABSTRACT	PDF Xplore
8.2	Comparison of Extraction Methods for Threshold Voltage Shift in NBTI Characterization Y. -H. Cheng, M. Cook, C. Kendrick Corporate Research and Development, N Semiconductor 1900 South County Trail, East Greenwich, RI, USA DOI: 10.1109/ICMTS48187.2020.9107918 HOVER FOR ABSTRACT	PDF Xplore
5.1	Multiscale modeling of CeO2/La2 O3 stacks for material/defect characterization B. Dianat, A. Padovani¹, L. Larcher¹ Department of Sciences and Method for Engineering, University of Modena and Reggio Emilia Via Amendola 2, Reggio Emilia, Italy ¹Applied Materials - MDLx Italy R&D Via Meuccio Ruini 74/L, Reggio Emilia, Italy DOI: 10.1109/ICMTS48187.2020.9107922 HOVER FOR ABSTRACT	PDF Xplore
9.3	Experimental and simulation analysis of carrier lifetimes in GaAs/AlGaAs Avalanche Photo-Diodes F. Driussi, A. Pilotto, D. De Belli, M. Antonelli¹, F. Arfelli², G. Biasiol³, G. Cautero¹, R. H. Menk¹, C. Nichetti¹, L. Selmi⁴, T. Steinhartova², P. Palestri DPIA, Università degli Studi di Udine, Udine, Italy ¹Elettra-Sincrotrone Trieste S.C.p.A, Area Science Park Basovizza, Trieste, Italy ²Department of Physics, Università di Trieste, Trieste, Italy ³IOM CNR, Laboratorio TASC, Area Science Park Basovizza, Trieste, Italy ⁴Department of Medical Imaging, University of Saskatchewan, Saskatoon, Canada DOI: 10.1109/ICMTS48187.2020.9107920 HOVER FOR ABSTRACT	PDF Xplore
2.1	Standardization of Specific Contact Resistivity Measurements using Transmission Line Model (TLM) S. Grover, S. Sahu, P. Zhang¹, K. O. Davis², S. K. Kurinec Rochester Institute of Technology, USA, Rochester, New York ¹Michigan State University, USA, East Lansing, MI ²University of Central Florida, USA, Orlando, FL DOI: 10.1109/ICMTS48187.2020.9107911 HOVER FOR ABSTRACT	PDF Xplore
7.3	Comparison of nMOSFET Structures for Millimeter-Wave Frequencies in 0.18-μm CMOS technology T. Hagiwara, N. Yamaki, K. Takano, Y. Umeda Department of Electrical Engineering, Tokyo University of Science, Yamazaki, Chiba, Japan DOI: 10.1109/ICMTS48187.2020.9107912 HOVER FOR ABSTRACT	PDF Xplore
4.2	Verification and Induction Method for Low Frequency Response Failure Modes in Acoustic MEMS G. Hantos, D. Marc P.Y. School of Engineering & Physical Sciences Research Institute of Sensors, Signals and System, Heriot-Watt University, Edinburgh, Scotland DOI: 10.1109/ICMTS48187.2020.9107925 HOVER FOR ABSTRACT	PDF Xplore
4.3	A Rapid, Reliable and Less-destructive On-chip Mass Measurement for 3D Composite Material Testing Microstructures G. Hwang, C. David¹, A. Paris¹, D. Decanini¹, A. Mizushima², Y. Mita LIMMS-CNRS, Institute of Industrial Science, University of Tokyo, Japan ¹C2N-CNRS, University Paris-Sud, University Paris-Saclay, Palaiseau, France ²VLSI Design and Education Center, The University of Tokyo, 2-11-16, Yayoi, Bunkyo-ku, Tokyo, Japan DOI: 10.1109/ICMTS48187.2020.9107932 HOVER FOR ABSTRACT	PDF Xplore
3.1	Area-Efficient and Bias-Flexible Inline Monitoring Structure for Fast Characterization of RTN and Transistor Local Mismatch in Advanced Technologies A. Jayakumar, N. Chan, L. Pirro, O. Zimmerhackl, M. Otto, T. Kleissner, J. Hoentschel GLOBALFOUNDRIES Fab1 LLC & Co.KG, Wilschdorfer Landstrasse 101, Dresden, Saxony, Germany DOI: 10.1109/ICMTS48187.2020.9107935 HOVER FOR ABSTRACT	PDF Xplore
9.2	Diode design for studying material defect distributions with avalanche-mode light emission M. Krakers, T. Knezevic, K. M. Batenburg, X. Liu, L. K. Nanver MESA+ Institute, Faculty of EEMCS, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS48187.2020.9107933 HOVER FOR ABSTRACT	PDF Xplore
7.4	Investigation of Test Structures for the Characterization of Very Fast Electro Static Discharge Events M. Lauderdale, E. Onyegam, S. Ruth, A. Gerdemann NXP Semiconductors, Austin, Texas, USA DOI: 10.1109/ICMTS48187.2020.9107924 HOVER FOR ABSTRACT	PDF Xplore
6.1	A nondestructive analysis method for the frontside-release process of thermal sensors C. Liu, J. Fu, Y. Hou, R. Liu¹, Q. Zhou, D. Chen Key Laboratory of Microelectronic Device & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China ¹Wuxi Innovation Center for Internet of Things, Jiangsu Wuxi, China DOI: 10.1109/ICMTS48187.2020.9107917 HOVER FOR ABSTRACT	PDF Xplore
5.5	Coaxial Circular Test Structure Applicable to both Ohmic and Schottky Characteristics for ZnO/Si Heterojunctions Assessment N. Miyazawa, N. Usami, H. Wang¹, T. Kubo¹, H. Segawa¹, Y. Mita, A. Higo² Department of Electrical Engineering and Information Systems, The University of Tokyo ¹Research Center for Advanced Science and Technology, The University of Tokyo ²Systems Design Lab, School of Engineering, The University of Tokyo DOI: 10.1109/ICMTS48187.2020.9107928 HOVER FOR ABSTRACT	PDF Xplore
1.1	Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics S. Nishizawa, K. Ito¹ Faculty of Engineering, Fukuoka University, 8-19-1, Nanakuma, Jyonan-Ku, Fukuoka, JAPAN ¹Graduate School of Science and Engineering, Saitama University DOI: 10.1109/ICMTS48187.2020.9107931 HOVER FOR ABSTRACT	PDF Xplore
8.3	Integrated Variability Measurements of 28 nm FDSOI MOSFETs down to 4.2 K for Cryogenic CMOS Applications B. C. Paz, L. L. Guevel, M. Cassé, G. Billiot, G. Pillonnet, A. Jansen¹, S. Haendler², A. Juge², E. Vincent², P. Galy², G. Ghibaudo, M. Vinet, S. d. Franceschi¹, T. Meunier, F. Gaillard MINATEC Campus, CEA-Leti, Université Grenoble Alpes, Grenoble, France ¹CEA-IRIG, Université Grenoble Alpes, Grenoble, France ²STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS48187.2020.9107906 HOVER FOR ABSTRACT	PDF Xplore
9.1	Comparison of cut-back method and optical backscatter reflectometry for wafer level waveguide characterization A. Peczek, C. Mai¹, G. Winzer¹, L. Zimmermann¹ IHP Solutions Gmb, Im Technologiepark 25, Frankfurt Oder, Germany ¹IHP, Im Technologiepark 25, Frankfurt Oder, Germany DOI: 10.1109/ICMTS48187.2020.9107905 HOVER FOR ABSTRACT	PDF Xplore
6.4	Test Structure for Measuring the Selectivity in Vapour Etch Processes M. Rondé, A. J. Walton, J. G. Terry School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, UK DOI: 10.1109/ICMTS48187.2020.9107934 HOVER FOR ABSTRACT	PDF Xplore
5.4	OxRAM BER Scaling Trends on 4 kb Mixed-Diameter Test Vehicle J. Sandrini, C. Cagli, L. Grenouillet, N. Castellani, V. Meli, F. Gaillard CEA-LETI, Minatec Campus, 17 rue des Martyrs, Grenoble Cedex 9, France DOI: 10.1109/ICMTS48187.2020.9107927 HOVER FOR ABSTRACT	PDF Xplore
4.1	Automated Wafer-Level Characterisation of Electrochemical Test Structures for Wafer Scanning I. Schmueser, C. L. Mackay¹, F. Moore, K. Doherty, J. P. Elliott¹, A. R. Mount¹, A. J. Walton, S. Smith, J. G. Terry School of Engineering, The University of Edinburgh, Edinburgh, U.K. ¹School of Chemistry, The University of Edinburgh, Edinburgh, U.K. DOI: 10.1109/ICMTS48187.2020.9107903 HOVER FOR ABSTRACT	PDF Xplore
4.4	Test structure and measurement system for characterising the electrochemical performance of nanoelectrode structures I. Schmueser, E. O. Blair, Z. Isiksacan, Y. Li, D. K. Corrigan¹, A. A. Stokes, J. G. Terry, A. R. Mount¹, A. J. Walton School of Engineering, The University of Edinburgh, Edinburgh, UK ¹School of Chemistry, The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS48187.2020.9107930 HOVER FOR ABSTRACT	PDF Xplore
9.4	Test Setup Optimization and Automation for Accurate Silicon Photonics Wafer Acceptance Production Tests C. B. Sia, T. L. Yap¹, A. Sasidharan¹, J. H. Tan¹, R. Chen¹, J. Leo¹, S. L. Tan¹, G. C. Man¹ FormFactor Singapore Pte. Ltd, 30 Marsiling Industrial Estate Rd 8, #05-02, Singapore ¹GLOBALFOUNDRIES Singapore, 60 Woodlands Industrial, Park D Street 2, Singapore DOI: 10.1109/ICMTS48187.2020.9107907 HOVER FOR ABSTRACT	PDF Xplore
8.1	Anomalous Scaling of Parasitic Capacitance in FETs with a High-K Channel Material A. E. M. Smink, M. J. de Jong, H. Hilgenkamp, W. G. van der Wiel, J. Schmitz MESA + Institute for Nanotechnology, University of Twente, Enschede, AE, The Netherlands DOI: 10.1109/ICMTS48187.2020.9107901 HOVER FOR ABSTRACT	PDF Xplore
1.2	Calibration of CBCM Measurement Hardware B. Smith, E. Onyegam, D. Hall, B. Verzi NXP Semiconductors, Austin, Texas, USA DOI: 10.1109/ICMTS48187.2020.9107913 HOVER FOR ABSTRACT	PDF Xplore
3.2	Test Structures for Noise Reduction of Fully Depleted-Silicon on Insulator p-Type Tunneling FET Using Channel Orientation H. -D. Song, H. -S. Song, S. B. Eadi, H. -W. Choi, G. -W. Lee, H. -D. Lee Department of Electronics Engineering, Chungnam National University, 99 Daehak-ro, Yuseong-gu, Daejeon DOI: 10.1109/ICMTS48187.2020.9107915 HOVER FOR ABSTRACT	PDF Xplore
2.2	Automated Generation, Fabrication and Measurement of Parametric Test Structures for Rapid Prototyping Using Optical Maskless Lithography P. Sullivan, A. Tsiamis, M. Rondé, A. J. Walton, S. Smith, J. G. Terry The School of Engineering, The University of Edinburgh, UK DOI: 10.1109/ICMTS48187.2020.9107929 HOVER FOR ABSTRACT	PDF Xplore
7.1	Novel Statistical Modeling and Parameter Extraction Methodology of Cutoff Frequency for RF-MOSFETs C. Tanaka, Y. Iguchi, A. Sueoka, S. Yoshitomi Memory Division, Kioxia Corporation 2-5-1, Kasama, Sakae-ku, Yokohama, Japan DOI: 10.1109/ICMTS48187.2020.9107914 HOVER FOR ABSTRACT	PDF Xplore
7.2	Influence of series resistance on the experimental extraction of FinFET noise parameters A. Tataridou, G. Ghibaudo, C. Theodorou IMEP-LAHC Univ. Grenoble Alpes, Univ. Savoie Mont Blanc CNRS, Grenoble INP, Institute of Engineering Univ. Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS48187.2020.9107908 HOVER FOR ABSTRACT	PDF Xplore
1	Experimental Set-Up For Novel Energy Efficient Charge-based Resistive RAM (RRAM) Switching P. Trotti, G. Pillonet, G. Molas, S. Oukassi, E. Nowak CEA, LETI, Univ. Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS48187.2020.9107936 HOVER FOR ABSTRACT	PDF Xplore
2.4	Extraction of Ultra-Low Contact Resistivity by End-Resistance Method B. -Y. Tsui, Y. -H. Lee, D. -Y. Wu, Y. -J. Lee¹, M. -Y. Li¹ Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R. O. C. ¹Taiwan Semiconductor Research Institute, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS48187.2020.9107910 HOVER FOR ABSTRACT	PDF Xplore
2.3	Characterization of parametric mismatch attributable to plastic chip encapsulation H. Tuinhout, A. Damian¹, A. Z. -v. Duijnhoven CTO / Modeling, Characterization & SPICE Libraries, Nijmegen NXP Semiconductors, Eindhoven, Netherlands ¹Package Core Technology, Nijmegen NXP Semiconductors, Netherlands DOI: 10.1109/ICMTS48187.2020.9107916 HOVER FOR ABSTRACT	PDF Xplore
3.3	Increased Delay Variability due to Random Telegraph Noise under Dynamic Back-gate Tuning M. Udo, K. Murakami, A. K. M. M. Islam¹, H. Onodera Department of Communications and Computer Engineering, Kyoto University Yoshida-honmachi, Sakyo-ku, Kyoto, JAPAN ¹Department of Electrical Engineering, Kyoto University Kyoto Daigaku Katsura, Nishikyo-ku, Kyoto, JAPAN DOI: 10.1109/ICMTS48187.2020.9107919 HOVER FOR ABSTRACT	PDF Xplore
6.2	Drop-in test structure chip to visualize residual stress of Ru/Cu film grown by atomic layer deposition and supercritical fluid deposition N. Usami, E. Ota¹, A. Higo¹, T. Momose², Y. Mita Department of Electrical Engineering and Information Systems (EEIS), The University of Tokyo ¹Systems Design Lab. (d.lab), School of Engineering, The University of Tokyo ²Department of Materials Engineering, The University of Tokyo DOI: 10.1109/ICMTS48187.2020.9107904 HOVER FOR ABSTRACT	PDF Xplore
5.2	Electrical and optical localisation of leakage current and breakdown point in SiOC:H low-k dielectrics M. Vidal-Dhô, Q. Hubert, P. Gonon¹, B. Pelissier¹, P. Lentrein, P. Ray, J. -M. Moragues, P. Fornara STMicroelectronics, Rousset, France ¹LTM CNRS, Grenoble, France DOI: 10.1109/ICMTS48187.2020.9107909 HOVER FOR ABSTRACT	PDF Xplore