ICMTS 2015 Program

2015 Program Booklet

By Session

Session 1: Reliability and Array Structures

1.1	14nm BEOL TDDB reliability testing and defect analysis T. Kane IBM Systems Technology Group/Microelectronics Division DOI: 10.1109/ICMTS.2015.7106094 ABSTRACT: 14nm BEOL (back end of line) TDDB (time to dielectric defect breakdown) test site structures successfully detect reliability defects but pose significant challenges in defect analysis At these advanced technology nodes, the reduction in copper land cross sectional area is accompanied by increased current density and electromigration failure rates. TDDB reliability test structures must be sensitive to capturing reliability defects. These same TDDB test site structures combined with porous ultra low-k (ULK) dielectric films represent real challenges in localizing and then determining BEOL reliability defects. Defect localization is difficult due to the complexity of these multiple metal layers along with the presence of the porous, low k dielectric films which exhibit shrinkage or void formation when exposed to an e-beam/FIB ion beam > 1 keV. Due to the porosity of these ULK dielectric films, they are especially susceptible to gallium ion implantation. It has been reported elsewhere that suppressing copper diffusion at the copper land/cap interface can be achieved by depositing a thin layer of CoWP and doping the copper seed layer with manganese [15, 16, 17]. However, a method for analytically confirming that these approaches for suppressing the copper diffusion do not affect TDDB performance/electromigration behavior must be demonstrated.	PDF Xplore
1.2	A novel structure of MOSFET array to measure ioff-ion with high accuracy and high density T. Suzuki, A. Anchlia1, V. Cherman2, H. Oishi, S. Mori, J. Ryckaert2, K. Ogawa, G. Van der Plas2, E. Beyne2, Y. Fukuzaki, D. Verkest2, H. Ohnuma Sony Corporation, Kanagawa, Japan 1imec vzw (currently working for XENICS corporation) 2imec vzw, Kapeldreef75, Belgium DOI: 10.1109/ICMTS.2015.7106095 ABSTRACT: We have successfully developed the new design of MOSFET array structure with high accuracy measurement both for Ion excluding IR drop and Ioff without contamination. We propose measurement algorithm “feedback looped biasing” with kelvin probe structure and canceling method for leakage contamination due to array peripherals. This test structure is implemented in scribe line for 28nm technology and beyond. And we get layout dependency of MOSFET characteristics and mismatch characteristics.	PDF Xplore
1.3	Circuit architecture and measurement technique to reduce the leakage current stemming from peripheral circuits with an array structure in examining the resistive element S. Sato, T. Ito, Y. Omura Kansai University, Suita, Osaka, Japan DOI: 10.1109/ICMTS.2015.7106096 ABSTRACT: A circuit architecture and measurement technique are proposed to reduce the leakage current that passes through peripheral circuits when examining arrays of resistive elements. We reveal, with the aid of circuit simulations, that high resolution measurements of resistive elements can be realized with the stacked column-selection array and the addition of a leakage-control terminal.	PDF Xplore

Session 2: Modeling

2.1	SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells S. Martinie, O. Rozeau, M. Tadayoni1, C. Raynaud, E. Nowak, S. Hariharan2, N. Do2 CEA-LETI, Grenoble, Cedex 9, France 1Silicon Storage Technology Inc, Sunnyvale, CA, US 2Silicon Storage Technology Inc., Microchip Technology Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2015.7106102 ABSTRACT: Embedded Flash NVM has become a key component in many applications, such as data processing, industrial electronics, automotive electronics, consumer electronics and wireless communications. SuperFlash® technology is based on the split-gate concept, using source-side electron injection for programming. The aim of this work is to propose, for the first time, a SPICE macro-model of the 2T (Select Gate and Floating Gate) 3rd generation SuperFlash cell [Hidaka], implemented in a 55 nm CMOS technology. A parameter extraction procedure is also proposed, showing a good agreement between the model and measurements.	PDF Xplore
2.2	Compact modeling and parameter extraction strategy of normally-on MOSFET T. Umeda, Y. Hirano, D. Suzuki, A. Tone, T. Inoue, H. Kikuchihara, M. Miura-Mattausch, H. J. Mattausch Graduate School of Advanced Sciences of Matter Hiroshima University 1-3-1 Kagamiyama, Higashi-Hiroshima Hiroshima, Japan DOI: 10.1109/ICMTS.2015.7106103 ABSTRACT: The additional channel-dopant layer of normally-on MOSFETs leads to accumulation-layer current near channel surface and deeper-lying neutral-region current above the p/n junction, which dominate bias conditions above and below flat-band, respectively. The developed compact model accurately captures these currents and exploits their different bias-condition properties for efficient parameter extraction.	PDF Xplore
2.3	Modeling of T-model equivalent circuit for spiral inductors in 90 nm CMOS technology J. -W. Jeong, S. -K. Kwon, J. -N. Yu, S. -Y. Jang, S. -H. Oh, C. -Y. Kim1, G. -w. Lee, H. -D. Lee Department of Electronics Engineering, Chungnam National Univ., Yuseong, Daejeon, Korea 1Department of Electronics Engineering, Chungnam National University, Daejeon, Daejeon, KR DOI: 10.1109/ICMTS.2015.7106104 ABSTRACT: This paper presents a newly proposed T-model of spiral inductors in 90nm radio frequency (RF) CMOS technology. Inductor modeling is one of the most difficult problems facing silicon-based RF integrated circuit designers, and the inclusion of many parameters of the inductor equivalent circuit consumes a lot of time during circuit simulation. In this paper, two models of spiral inductors were simulated to compare their agreement with the measured data from 100MHz to 10GHz. The proposed T-model had less parameters than the conventional double-Ï€ model, and also showed good agreement in the RF performance of the spiral inductors, such as quality factor (Q-factor) and inductance (L). In addition, the proposed T-model had an error rate of less than 5% with the S-parameter of measured data, similar to the double-Ï€ model.	PDF Xplore
2.4	A four-terminal JFET compact model for high-voltage power applications W. Wu, S. Banerjee, K. Joardar Texas Instruments, Dallas, TX DOI: 10.1109/ICMTS.2015.7106105 ABSTRACT: This paper presents a physics-based compact model for four-terminal (4T) JFETs. It is capable of modeling device characteristics when the top and bottom gates are biased independently. The model is formulated using symmetric linearization technique from the CMC (compact model council) standard MOSFET model PSP, which gives simpler model equations than other reported 4T JFET models. It also includes carrier velocity saturation effect which is important for short channel and/or high voltage devices. The model has been verified on several JFETs (including device with blocking voltage rated > 700V). Good agreement has been achieved between silicon data and simulation. The complete model has been implemented into process design kits (PDKs) for high-voltage power management switcher design.	PDF Xplore

Session 3: Process Evaluation

3.1	Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy G. Moore, J. -H. Liao, S. McDade1, B. Verzi1 IBM Microelectronics, NY, USA 1Keysight Technologies, Burlington, VT, USA DOI: 10.1109/ICMTS.2015.7106106 ABSTRACT: This paper will look at both technical and business advantages of parallel vs. serial inline parametric testing, secondary effects of changing test strategies, quantifying return on investment of newer test strategies, and next steps in pushing the envelope of test. Topics such as cost, schedule, macro design and quality will be explored to understand tradeoffs and synergies of test strategies. Examples and metrics of parallel compared to serial testing will be examined.	PDF Xplore
3.2	Employing an on-die test chip for maximizing parametric yields of 28nm parts J. Mueller, S. Jallepalli, R. Mooraka, S. Hector Freescale Semiconductor, Austin, Tx, USA DOI: 10.1109/ICMTS.2015.7106107 ABSTRACT: We show that a well designed suite of process observation structures (POSt) that can be tested on a standard production tester is a valuable asset for achieving high parametric yields. Our ability to tailor test coverage and conditions based on circuit yield signatures has allowed us to obtain the needed learning within a small test time budget.	PDF Xplore
3.3	Robust process capability index tracking for process qualification C. Gu, C. C. McAndrew Freescale Semiconductor, Tempe, AZ DOI: 10.1109/ICMTS.2015.7106108 ABSTRACT: This paper presents a robust process qualification and monitoring procedure based on the recently developed YAT and YWL process capability indices. Combined with appropriate test structures and measurements the procedure enables rapid process maturity evaluation and on-going loop closure of manufacturing to process specifications. The procedure generates interactive web-based reports and data that provide high-level “scoring” and a time-line of process capability, an ability to quickly dive down and identify the root cause of issues, and capability to compare between fabs.	PDF Xplore
3.4	New compact model for performance and process variability assessment in 14nm FDSOI CMOS technology Y. Denis, F. Monsieur, G. Ghibaudo1, J. Mazurier, E. Josse, D. Rideau, C. Charbuillet, C. Tavernier, H. Jaouen STMicroelwknectronics, FR, Crolles 1IMEP-LAHC, Grenoble Cedex DOI: 10.1109/ICMTS.2015.7106109 ABSTRACT: This paper provides a compact model for performance and process variability assessment in 14nm FDSOI CMOS technology. It is used to investigate MOS performance relation with process parameters. Then production device within wafer variability has been modeled using backward propagation of variance (BPV). This application allows spotting the main model parameter contributing to the total MOS transistor resistance (Ron) variability.	PDF Xplore
3.5	Silicon thickness monitoring strategy for FD-SOI 28nm technology A. Cros, F. Monsieur, Y. Carminati, P. Normandon, D. Petit, F. Arnaud, J. Rosa STMicroelectronics, Crolles Site, Crolles, France DOI: 10.1109/ICMTS.2015.7106110 ABSTRACT: The silicon thickness (Tsi) fluctuation monitoring on FD-SOI 28nm technology process is addressed by 2 different electrical characterization techniques. The first, capacitive, is adapted to within wafer variations and lot/wafer variations monitoring. The second, using the Idsat sensitivity to the Tsi in an addressable transistors array, allows to measure the local variations in the range of few tens of microns.	PDF Xplore

Session 4: Discussion

4.1	A test structure for characterizing the cleanliness of glass beads using low-frequency dielectric spectroscopy M. Buehler Decagon Devices, Inc., WA DOI: 10.1109/ICMTS.2015.7106111 ABSTRACT: The cleanliness of glass beads was assessed using a test structure and low-frequency dielectric spectroscopy operating between 10 mHz and 100 kHz. Glass beads were exposed to moisture between 40 and 85% RH. Results indicate that capillary and film water can be used to indicate the state of cleanliness.	PDF Xplore
4.1	A proposal for early warning indicators to detect impending metallization failure of DMOS transistors in cyclic operation M. Ritter, M. Pfost Robert Bosch Center for Power Electronics, Reutlingen University Alteburgstr. 150, Reutlingen, Germany DOI: 10.1109/ICMTS.2015.7106097 ABSTRACT: DMOS transistors in integrated smart power technologies are often subject to cyclic power dissipation with substantial self-heating. This leads to repetitive thermo-mechanical stress, causing fatigue of the on-chip metallization and limiting the lifetime. Hence, most designs use large devices for lower peak temperatures and thus reduced stress to avoid premature failures. However, significantly smaller DMOS transistors are acceptable if the system reverts to a safer operating condition with lower stress when a failure is expected to occur in the near future. Hence, suitable early-warning sensors are required. This paper proposes a floating metal meander embedded between DMOS source and drain to detect an impending metallization failure. Measurement results of several variants will be presented and discussed, investigating their suitability as early warning indicators.	PDF Xplore
4.2	Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via H. Shinkawata, N. Tsuboi, A. Tsuda1, S. Sato2, Y. Yamaguchi Renesas Electronics Corporation, Production and Technology Unit, Hitachinaka-shi, Ibaraki-ken, Japan 1Renesas System Design Corporation, Tokyo, Japan 2Kansai University, Suita, Osaka, Japan DOI: 10.1109/ICMTS.2015.7106112 ABSTRACT: We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting array into Narrow Scribe Line which named as High sensitivity-Screening and Detection-decoder test structure in Scribe line (HSD-S). Abnormally high resistance as a soft failure via was detected and located in a 40nm CMOS technology. We captured a soft failure bit which had a high resistance via exhibiting over 160 times larger one.	PDF Xplore
4.3	The impact of deep trench and well proximity on MOSFET performance H. Sheng, T. Bettinger, J. Bates Freescale Semiconductor Inc., Tempe, AZ, USA DOI: 10.1109/ICMTS.2015.7106113 ABSTRACT: The test structures are developed in order to enable quantification of the effects of deep trench and well proximity on MOSFETs in a 0.13 μm process. Two types of structures are analyzed: with the deep trench and the well edges varied together; and those edges are varied independently. The measurement results show that the deep trench and well proximity effects can influence device performance.	PDF Xplore
4.5	A test structure for reliability analysis of CMOS devices under DC and high frequency AC stress T. Matsuda, K. Ichihashi, H. Iwata, T. Ohzone1 Department of Information Systems Engineering, Toyama Prefectural University 1Dawn Enteprise, Nagoya, Japan DOI: 10.1109/ICMTS.2015.7106114 ABSTRACT: A test structure for reliability analysis of MOSFETs in CMOS inverters under DC and high frequency AC stress has been presented. It has an input pulse generation block with a ring oscillator, monitor inverter blocks and Kelvin connected selector switches. Detailed I - V characteristics of MOSFETs in the monitor inverters were measured and the degradation by HCI and BTI in nMOS and pMOS devices were analyzed. The dominant degradation origins in nMOS and pMOS devices can be attributed to HCI and NBTI, respectively.	PDF Xplore
4.6	Measurement and modeling of IC self-heating including cooling system properties T. Nishimura, H. Tanoue, Y. Oodate, H. J. Mattausch, M. Miura-Mattausch Graduate School of Advanced Science of Matter, Hiroshima University, Higashi-Hiroshima, Japan DOI: 10.1109/ICMTS.2015.7106115 ABSTRACT: Heating and cooling mechanisms under actual IC-operating conditions are investigated experimentally and theoretically. For the investigation different chip packages and cooling-system approaches are studied. Comparison between experimental and theoretical studies concludes that the optimum possible package design is obtained by enhancing both the heat radiation and the air convection at the same time.	PDF Xplore
4.7	Elastic instabilities induced large surface strain sensing structures (EILS) Y. Li, J. G. Terry1, S. Smith1, A. J. Walton1, G. McHale, B. Xu Faculty of Engineering and Environment, Northumbria University, Newcastle upon Tyne, UK 1SMC Institute for Integrated Micro and Nano Systems School of Engineering, The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2015.7106116 ABSTRACT: This paper reports on the sensing of large strain using a mechanically actuated switch gate and a variable resistor surface creasing test structure. Test structures with different gate and interconnect/wiring geometries have been designed, fabricated and characterised. They respond to designed strain values with a reduction in device resistivity of 11 to 12 orders of magnitude. Results from strain measurements ranging from 0.2 to 0.6 are reported for test structures with electrode spaces of 10 to 60 μm.	PDF Xplore
4.8	Cross-correlation of electrical measurements via physics-based device simulations: Linking electrical and structural characteristics A. Padovani, L. Larcher, L. Vandelli, M. Bertocchi1, R. Cavicchioli1, D. Veksler2, G. Bersuker3 MDLab s.r.i., Saint Christophe, Aosta, AO, Italy 1DISMI University of Modena and Reggio Emilia, Reggio Emilia, RE, Italy 2SEMATECH, Albany, NY, USA 3NA DOI: 10.1109/ICMTS.2015.7106117 ABSTRACT: We present a comprehensive simulation framework to interpret electrical characteristics (I-V, C-V, G-V, Charge-Pumping, BTI, CVS, RVS, ...) commonly used for material characterization and reliability analysis of gate dielectric stacks in modern semiconductor devices. By accounting for the physical processes controlling charge transport through the dielectric (e.g. carrier trapping/de-trapping at the defect sites, defect generation, etc.), which is modeled using a novel approach based of material characteristics [1], [2], the simulations provide a unique link between the electrical measurements data and specific atomic defects in the dielectric stack. Within this methodology, the software allows an accurate defect spectroscopy by cross-correlating measurements of pre-stress electrical parameters (IV, CV, BTI). These data are then used to project the stack reliability through the simulations of stress-induced leakage current (SILC) and time-dependent dielectric degradation trends, demonstrating the tool capabilities as a technology characterization/optimization benchmark.	PDF Xplore
4.9	NPN CML ring oscillators for model verification and process monitoring C. Compton MACOM, Newport Beach, CA, USA DOI: 10.1109/ICMTS.2015.7106118 ABSTRACT: A set of NPN CML (Current Mode Logic) oscillators is designed in a 0.18um SiGe BiCMOS process, with the intention to provide model verification and process monitoring capabilities. The main design goals are that the oscillators need to be small and easy to test such that many of them can be placed in the scribe line and be measured by production PCM test equipment.	PDF Xplore

Session 5: Parameter Extraction

5.1	Compact modeling solution of layout dependent effect for FinFET technology D. C. Chen, G. S. Lin, T. H. Lee, R. Lee1, Y. C. Liu, M. F. Wang, Y. C. Cheng, D. Y. Wu Advanced Technology Development Division, United Microelectronics Corporation (UMC), Hsin-Chu City, Taiwan ROC 1Advanced Technology Development Division, United Microelectronics Corporation (UMC) DOI: 10.1109/ICMTS.2015.7106119 ABSTRACT: We successfully developed and verified a complete compact model solution for layout dependent effect (LDE) of FinFET technology. LDE has significant impact on the device performances mainly due to the application of stressors and aggressive device scaling. With LDE, performance degradation may be up to 10% or more. In this work, compact model solution for Length of Oxidation (LOD), Well Proximity Effect (WPE), Neighboring Diffusion Effect (NDE), Metal Boundary Effect (MBE), and Gate Line End Effect (GLE) were delivered. This solution was implemented successfully in BSIM-CMG for efficient circuit simulation.	PDF Xplore
5.2	A simple method for characterization of MOSFET serial resistance asymmetry D. Tomaszewski, G. Głuszko, J. Malesińska, K. Domański, M. Zaborowski, K. Kucharski, D. Szmigiel, A. Sierakowski Instytut Technologii Elektronowej (ITE), Warsaw, Poland DOI: 10.1109/ICMTS.2015.7106120 ABSTRACT: A method for a direct extraction of individual serial resistances of MOSFET source/drain electrodes is presented. It is based on the device I-V characteristics in a saturation range measured for two device configurations inverted with respect to source and drain electrodes. A threshold voltage necessary for the saturation range modeling is determined from the non-saturation range I-V characteristics. Based on the measurement data determined for the SOI MOSFETs fabricated in ITE the proposed method has been compared with other techniques.	PDF Xplore
5.3	Threshold voltage extraction method in field-effect devices with power-law dependence of mobility on carrier density V. Mosser, D. Seron1, Y. Haddab ITRON SAS, Issy Technology Center 1Itron SAS, Malakoff, FR DOI: 10.1109/ICMTS.2015.7106121 ABSTRACT: We propose a new method suited for the extraction of the threshold voltage in 2D Field-Effect-Transistors. It can be applied to various classes of devices where the mobility exhibits a power-law dependence on carrier concentration, μ ∝ nS. The result doesn't depend on contact resistance. The method provides a physically sound value: VG-VT is proportional to the channel carrier density as checked with VG-dependent Hall measurements in companion gated Hall devices.	PDF Xplore
5.4	Measurement of Vth variation due to STI stress and inverse narrow channel effect at ultra-low voltage in a variability-suppressed process Y. Ogasahara, M. Hioki, T. Nakagawa, T. Sekigawa, T. Tsutsumi, H. Koike Industrial Science and Technology(AIST), National Institute of Advanced, Tsukuba, Japan DOI: 10.1109/ICMTS.2015.7106122 ABSTRACT: This paper demonstrates notable impact of Vth shift due to STI-induced dopant redistribution on ultra-low voltage designs. 2.5X Ion change at ultra-low voltages due to STI was measured on a 65nm SOTB CMOS process. Serious 6X Ion change due to inverse narrow channel effects was also observed. We propose ring oscillator based measurement procedure observing Vth shift by exploiting flexible Vth controllability by backgate biasing of SOTB process.	PDF Xplore

Session 6: Capacitance

6.1	Monitoring test structure for plasma process induced charging damage using charge-based capacitance measurement (PID-CBCM) S. Mori, K. Ogawa, H. Oishi, T. Suzuki, M. Tomita, M. Bairo, Y. Fukuzaki, H. Ohnuma Sony Corporation, Kanagawa, Japan DOI: 10.1109/ICMTS.2015.7106123 ABSTRACT: We propose monitoring test structure and measurement technique for plasma process induced charging damage (PID) using charge-based capacitance measurement (CBCM). For evaluating the influence of PID on MOSFET effectively, remarkably small (several tens of fF) gate capacitance of MOSFET can be extracted by eliminating parasitic antenna capacitance. Moreover, we can extract interface trap density from the same CBCM structure using the modified Charge-Pumping measurement.	PDF Xplore
6.2	A novel new gate charge measurement method A. Mikata, H. Kakitani, R. Takeda, A. Wadsworth Keysight Technologies, Hachioji-shi, Tokyo, Japan DOI: 10.1109/ICMTS.2015.7106124 ABSTRACT: The drive for ever-increasing power circuit efficiencies ensures that the measurement of gate charge (Qg) will continue to grow in importance. In this paper, we explain a new Qg measurement method that solves many conventional Qg measurement issues. The outlined method supplies the same Qg curve obtained by traditional one-pass high-power measurement techniques using a new method that combines two Qg curves measured under lower power conditions.	PDF Xplore
6.3	Area and performance study of FinFET with detailed parasitic capacitance analysis in 16nm process node T. Okagaki, K. Shibutani, H. Matsushita, H. Ojiro, M. Morimoto, Y. Tsukamoto, K. Nii, K. Onozawa Renesas Electronics Corp, Tokyo, Japan DOI: 10.1109/ICMTS.2015.7106125 ABSTRACT: An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a delay cell because it is easy to increase delay time with simple layout modification only. Moreover, small number of delay cell can reduce a leakage current in a chip.	PDF Xplore
6.4	In-line monitoring test structure for Charge-Based Capacitance Measurement (CBCM) with a start-stop self-pulsing circuit K. Sawada, G. Van der Plas1, S. Mori, C. Vladimir1, A. Mercha1, V. Diederik1, Y. Fukuzaki, H. Ammo Sony Corporation, Atsugi-shi, Kanagawa, Japan 1IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.2015.7106126 ABSTRACT: CBCM measurements require known clock frequency. We proposed CBCM test structures with an internal start-stop self-pulsing circuit instead of external clock monitoring. The circuit creates 213 pulses in a time-slot defined by SMU pulsed signal, resulting in known clock frequency. We accurately extract MOSFET's gate capacitances of several tens of fF.	PDF Xplore

Session 7: Resistance

7.1	Design and evaluation of an integrated thin film resistor matching test structure H. Tuinhout, N. Wils, P. Huiskamp, E. de Koning NXP Semiconductors - Technology & Operations, Integrated Technology Platforms Eindhoven & Nijmegen, the Netherlands DOI: 10.1109/ICMTS.2015.7106127 ABSTRACT: A test structure is presented that combines two types of full Kelvin matched resistor pairs in a single 12 pad process control compatible test line. Based on these structures, matching results of SiCr resistors in a BiCMOS RF technology are discussed, demonstrating some of the frequently encountered challenges of interpreting subtle parametric mismatch fluctuation effects.	PDF Xplore
7.2	Characterization of recessed Ohmic contacts to AlGaN/GaN M. Hajlasz, J. J. T. M. Donkers1, S. J. Sque1, S. B. S. Heil1, D. J. Gravesteijn1, F. J. R. Rietveld2, J. Schmitz3 Materials innovation institute (M2i), Delft, The Netherlands 1NXP Semiconductors Research, Eindhoven, The Netherlands 2NXP Semiconductors, Nijmezen, The Netherlands 3Universiteit Twente, Enschede, Overijssel, NL DOI: 10.1109/ICMTS.2015.7106133 ABSTRACT: In this work the choice of appropriate test structures and characterization methods for recessed Ohmic contacts to AlGaN/GaN is discussed. It is shown that, in the worst-case scenario, the prevailing assumption of identical sheet resistance between and under the contacts can lead to errors of up to 3000 % in the extracted specific contact resistance.	PDF Xplore
7.3	Novel sheet resistance measurement on AlGaN/GaN HEMT wafer adapted from four-point probe technique J. Lehmann, C. Leroux, G. Reimbold, M. Charles, A. Torres, E. Morvan, Y. Baines, G. Ghibaudo1, E. Bano1 Univcrsité Grenoble Alpes, Grenoble, cedex, France 1IMEP-LAHC, Grenoble cedex 1 DOI: 10.1109/ICMTS.2015.7106134 ABSTRACT: In this paper, we present a new method of sheet resistance measurement on AlGaN/GaN wafers. Such measurements are useful for an easy monitoring of AlGaN/GaN epitaxy. Measurements were obtained by adapting the four-point probe technique to AlGaN/GaN wafers. This method is used today in the 200mm GaN-on-Si fabrication line at the CEA-LETI with a standard deviation of 2% on the sheet resistance measurement.	PDF Xplore
7.4	Sheet resistance measurement for process monitoring of 400 °C PureB deposition on Si L. Qi, L. K. Nanver Delft University of Technology, Delft, The Netherlands DOI: 10.1109/ICMTS.2015.7106135 ABSTRACT: Sheet-resistance test-structures to determine conductance along the interface formed by 400°C pure boron (PureB) deposition on silicon are presented. The structures are straightforward to fabricate and measure for monitoring either directly after deposition or end-of-line. This provides valuable information on the perfection of the deposition and the series resistance of PureB (photo)diodes.	PDF Xplore
7.5	Combined transmission line measurement structures to study thin film resistive sensor fabrication A. Tabasnikov, A. J. Walton, S. Smith Institute for Integrated Micro and Nano Systems, The niversity of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2015.7106136 ABSTRACT: This paper reports the design and application of test structures for extracting the resistance of features formed when fabricating evaporated platinum (Pt) thin film structures on patterned, sputtered tantalum nitride (TaN). The combination of these two layers is used to produce an integrated resistive sensor structure. Two resistive features were considered during the test structure design: firstly the contact resistance between the two metal layers and secondly, the additional resistance introduced in the upper metal layer due to step coverage effects.	PDF Xplore

Session 8: Emerging Technologies

8.1	Test structures for the wafer mapping and correlation of electrical, mechanical and high frequency magnetic properties of electroplated ferromagnetic alloy films E. Sirotkin, S. Smith, R. Walker, J. G. Terry, A. J. Walton Scottish Microelectronics Centre, University of Edinburgh, United Kingdom DOI: 10.1109/ICMTS.2015.7106137 ABSTRACT: This paper presents a method of electrically determining the permeability of patterned electroplated structures and brings together the simultaneous wafer mapping of magnetic permeability, electrical resistivity and mechanical strain of electroplated ferromagnetic films together with the thickness of the films and their composition. The wafer mapping of all these properties is implemented using set of simple automated electrical and optical techniques that facilitates the spatial correlation between different parameters. This enables the uniformity of the electrodeposited conductive ferromagnetic films to be analyzed and supports the optimization of both their properties and the technological processes associated with their deposition.	PDF Xplore
8.2	A fully-automated methodology and system for printed electronics foil characterization F. Vila, J. Pallarès, A. Conde, L. Terés IMB-CNM (CSIC) Cerdanyola del Vallès, Barcelona, Spain DOI: 10.1109/ICMTS.2015.7106138 ABSTRACT: This paper presents a new characterization setup for Printed Electronics. The proposed system allows automatic generation of experiments, optical and electrical characterization, and statistical result analysis of full printed foils. Although its primary objective is the extraction of the needed post-layout corrections, due to its modular design, it can extract other technology information, like Design Rule values or overall printing quality of the whole fabrication process.	PDF Xplore
8.3	A capacitive based piezoelectric AlN film quality test structure N. Jackson, O. Z. Olszewski, L. Keeney, A. Blake, A. Mathewson Tyndall National Institute, University College Cork Lee Maltings, Prospect Row, Cork, Ireland DOI: 10.1109/ICMTS.2015.7106139 ABSTRACT: Aluminum nitride (AlN) is a piezoelectric material that is commonly used in various MEMS applications. However, determining the properties of the thin film typically requires multiple test structures, and there are various methods for obtaining the piezoelectric properties. This paper highlights the development of a capacitive based test structure that is capable of determining the different material properties. In addition this paper compares various test methods used to determine the piezoelectric properties of AlN.	PDF Xplore

Session 9: Circuits

9.1	Silicon measurements of characteristics for passgate/pull-down/pull-up MOSs and search MOS in a 28 nm HKMG TCAM bitcell K. Nii, K. Yamaguchi, M. Yabuuchi, N. Watanabe, T. Hasegawa, S. Yoshida, T. Okagaki, M. Yokota, K. Onozawa Renesas Electronics Corporation, Tokyo, Japan DOI: 10.1109/ICMTS.2015.7106140 ABSTRACT: Test structures for measuring characteristics of MOS components in 28 nm high-k metal-gate (HKMG) Ternary Content-Addressable memory (TCAM) bitcell are implemented. Proposed TCAM bitcell are including pull-down (PD) and pass-gate (PG) NMOSs, pull-up (PU) PMOSs and search NMOSs, which are built up based on standard 6T SRAM bitcell. It can achieve the small area but symmetrical layout could not be implemented. Each MOS characteristic is measured by test structure and observed over 20 mV Vt offset for each PD and PG NMOS pairs due to asymmetrical layout, whereas there is no difference in PU-PMOS pair. From measurement results we estimate the bit error rates on the supply voltage for TCAM array and predict that the TCAM Vmin for read-operation becomes worse by 42 mV at 5.3-sigma condition compared to that of standard SRAM array. Based on measured bitcell characteristics we designed and fabricated 80-Mbit TCAM test chips with appropriate redundancies, achieving below 740 mV Vmin at 250 MHz operation at 25°C and 85°C.	PDF Xplore
9.2	Test circuit for accurate measurement of setup/hold and access time of memories N. Agarwal Physical Design Group ARM Embedded Technologies Pvt. Ltd., Bangalore, India DOI: 10.1109/ICMTS.2015.7106153 ABSTRACT: This paper will examine the latest developments in the field of designing the test circuits for accurate measurement of setup/hold and access time of memory IPs. Measurement across all voltage domain and temperature corners, by way of the architecture discussed, has a fine resolution of just two inverter delay and correlates well with silicon within permissible range.	PDF Xplore
9.3	Reduction of overhead in adaptive body bias technology due to triple-well structure based on measurement and simulation Y. Ogasahara, T. Sekigawa, M. Hioki, T. Nakagawa, T. Tsutsumi, H. Koike National Institute of Advanced Industrial Science and Technology(AIST), Tsukuba, Japan DOI: 10.1109/ICMTS.2015.7106154 ABSTRACT: This paper presents the significant reduction of the area overhead due to triple-well structure for adaptive body bias methods. Triple-well TEGs which include violation of design rules originating from voltage tolerance were implemented on a 65nm process. Reexamining voltage tolerance based on measurement results reduced deep n-wells spacing by 60% on the 65nm process. A new method for further overhead reduction is proposed based on a device simulation which is validated with measurement results.	PDF Xplore
9.4	Sensitivity-independent extraction of Vth variation utilizing log-normal delay distribution A. K. M. Mahfuzul Islam, H. Onodera Graduate School of Informatics, Kyoto University, Sakyo-ku, Kyoto, Japan DOI: 10.1109/ICMTS.2015.7106155 ABSTRACT: We propose an area-efficient and low-cost extraction methodology of Vth variation which utilizes the exponential relationship of gate delay to Vth variation. The exponential relationship is achieved by operating the DUT in the weak inversion region. Utilizing a previously proposed pass-gate based topology-reconfigurable ring oscillator, the weak inversion operation of a specific gate is achieved while maintaining a much higher supply voltage for the overall circuit. Area-efficiency is achieved by altering the individual gate topology and measuring for each topology. Based on a pass-gate inserted inverter delay model, the relationship of delay variation to Vth variation is expressed using the body effect and DIBL coefficients. Thus, the proposed method does not require any sensitivity calculation. Vth variation is then extracted from the measured delay distributions directly. A test chip containing three different sizes of DUTs are fabricated in a 65-nm bulk CMOS process. Vth variation of nMOSFET and pMOSFET for three different DUT sizes are successfully extracted. The methodology is suitable for low-cost, area-efficient and all-digital measurement of Vth variation.	PDF Xplore

Session 10: RF

10.1	Characterization of wideband decoupling power line with extremely low characteristic impedance for millimeter-wave CMOS circuits R. Goda, S. Amakawa, K. Katayama, K. Takano, T. Yoshida, M. Fujishima Graduate School of Advanced Sciences of Matter Hiroshima University 1-3-1 Kagamiyama Higashihiroshima, Japan DOI: 10.1109/ICMTS.2015.7106098 ABSTRACT: A wideband decoupling power line for millimeter-wave circuits can be realized with a transmission line having an extremely low characteristic impedance, Z0 → 0Ω. It is, however, very difficult to characterize such a line with the ordinary two-port S-parameter measurement. This paper presents an alternative measurement technique that uses transmission line stubs. The measurement results confirm that a power line impedance below 1Ω is successfully achieved over a very wide frequency range (> 80 GHz). A measurement-based method of finding the necessary length of such a low-impedance line for realizing good decoupling is also proposed.	PDF Xplore
10.2	Observations on substrate characterisation through Coplanar Transmission Line Impedance measurements L. Floyd, J. Pike, J. Tao, N. Jackson1 Tyndall National Institute, Cork, Ireland 1Tyndall National Institute, Cork, IE DOI: 10.1109/ICMTS.2015.7106099 ABSTRACT: In the course of developing a GaAs Schottky diode membrane technology for millimeter wave applications (viz. THz mixers and multipliers) it was found that subtle changes and variations introduced into the membrane structure can significantly affect the circuit performance. We describe how these effects manifest themselves and, using S-parameter measurements on a variety of substrates, show how they can be explained in terms of conductive or charge layers that are observable through Coplanar Transmission Line Impedance measurements. A modified transmission line model is given.	PDF Xplore
10.3	Systematic calibration procedure of process parameters for electromagnetic field analysis of millimeter-wave CMOS devices K. Takano, K. Katayama, S. Mizukusa, S. Amakawa, T. Yoshida, M. Fujishima Hiroshima University, Graduate School of Advanced Sciences of Matter, Higashihiroshima, Hiroshima, Japan DOI: 10.1109/ICMTS.2015.7106100 ABSTRACT: This work proposed the systematic calibration method of process parameters for electromagnetic analysis of CMOS back-end devices in millimeter-wave and THz frequencies. It uses the propagation constants of transmission lines in all the measurement frequency and the RLGC model parameters in low frequency as the objective variables of the parameter fitting. It was showed that the EM simulation results using calibrated process parameters were in good agreement with the measurement results up to 330 GHz.	PDF Xplore
10.4	Electromagnetic field test structure chip for back end of the line metrology L. You, J. -J. Ahn, E. Hitz, J. Michelson, Y. Obeng, J. Kopanski Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2015.7106101 ABSTRACT: A test chip to produce known and controllable gradients of surface potential and magnetic field at the chip surface and suitable for imaging with various types of scanning probe microscopes is presented. The purpose of the test chip is to evaluate various SPMs as metrology tools to image electro-magnetic fields within nanoelectronic devices and multi-level interconnects, and as metrology tools to detect defects in back end of line (BEOL) metallization and packaging processes. Four different levels of metal are used to create different buried structures that, when biased, will produce varying electric field and magnetic field distributions. Contacts to the chip are made via wire bonds to a printed circuit board (PCB) that allows programed external biases and ground to be applied to specific metal levels while imaging with a SPM. DC and high frequency COMSOL simulations of the test structures were conducted to determine the expected field distributions. Electric field can be imaged via scanning Kelvin force microscopy (SKFM); magnetic field via scanning magnetic force microscopy (MFM); and the capacitance of buried metal lines via scanning microwave microscopy (SMM). The combination of precisely known structures and accurate simulations will allow the spatial resolution and accuracy of various SPMs sensitive to electric field (potential) or magnetic field to be determined and improved.	PDF Xplore

By First Author

9.2	Test circuit for accurate measurement of setup/hold and access time of memories N. Agarwal Physical Design Group ARM Embedded Technologies Pvt. Ltd., Bangalore, India DOI: 10.1109/ICMTS.2015.7106153 HOVER FOR ABSTRACT	PDF Xplore
4.1	A test structure for characterizing the cleanliness of glass beads using low-frequency dielectric spectroscopy M. Buehler Decagon Devices, Inc., WA DOI: 10.1109/ICMTS.2015.7106111 HOVER FOR ABSTRACT	PDF Xplore
5.1	Compact modeling solution of layout dependent effect for FinFET technology D. C. Chen, G. S. Lin, T. H. Lee, R. Lee1, Y. C. Liu, M. F. Wang, Y. C. Cheng, D. Y. Wu Advanced Technology Development Division, United Microelectronics Corporation (UMC), Hsin-Chu City, Taiwan ROC 1Advanced Technology Development Division, United Microelectronics Corporation (UMC) DOI: 10.1109/ICMTS.2015.7106119 HOVER FOR ABSTRACT	PDF Xplore
4.9	NPN CML ring oscillators for model verification and process monitoring C. Compton MACOM, Newport Beach, CA, USA DOI: 10.1109/ICMTS.2015.7106118 HOVER FOR ABSTRACT	PDF Xplore
3.5	Silicon thickness monitoring strategy for FD-SOI 28nm technology A. Cros, F. Monsieur, Y. Carminati, P. Normandon, D. Petit, F. Arnaud, J. Rosa STMicroelectronics, Crolles Site, Crolles, France DOI: 10.1109/ICMTS.2015.7106110 HOVER FOR ABSTRACT	PDF Xplore
3.4	New compact model for performance and process variability assessment in 14nm FDSOI CMOS technology Y. Denis, F. Monsieur, G. Ghibaudo1, J. Mazurier, E. Josse, D. Rideau, C. Charbuillet, C. Tavernier, H. Jaouen STMicroelwknectronics, FR, Crolles 1IMEP-LAHC, Grenoble Cedex DOI: 10.1109/ICMTS.2015.7106109 HOVER FOR ABSTRACT	PDF Xplore
10.2	Observations on substrate characterisation through Coplanar Transmission Line Impedance measurements L. Floyd, J. Pike, J. Tao, N. Jackson1 Tyndall National Institute, Cork, Ireland 1Tyndall National Institute, Cork, IE DOI: 10.1109/ICMTS.2015.7106099 HOVER FOR ABSTRACT	PDF Xplore
10.1	Characterization of wideband decoupling power line with extremely low characteristic impedance for millimeter-wave CMOS circuits R. Goda, S. Amakawa, K. Katayama, K. Takano, T. Yoshida, M. Fujishima Graduate School of Advanced Sciences of Matter Hiroshima University 1-3-1 Kagamiyama Higashihiroshima, Japan DOI: 10.1109/ICMTS.2015.7106098 HOVER FOR ABSTRACT	PDF Xplore
3.3	Robust process capability index tracking for process qualification C. Gu, C. C. McAndrew Freescale Semiconductor, Tempe, AZ DOI: 10.1109/ICMTS.2015.7106108 HOVER FOR ABSTRACT	PDF Xplore
7.2	Characterization of recessed Ohmic contacts to AlGaN/GaN M. Hajlasz, J. J. T. M. Donkers1, S. J. Sque1, S. B. S. Heil1, D. J. Gravesteijn1, F. J. R. Rietveld2, J. Schmitz3 Materials innovation institute (M2i), Delft, The Netherlands 1NXP Semiconductors Research, Eindhoven, The Netherlands 2NXP Semiconductors, Nijmezen, The Netherlands 3Universiteit Twente, Enschede, Overijssel, NL DOI: 10.1109/ICMTS.2015.7106133 HOVER FOR ABSTRACT	PDF Xplore
9.4	Sensitivity-independent extraction of Vth variation utilizing log-normal delay distribution A. K. M. Mahfuzul Islam, H. Onodera Graduate School of Informatics, Kyoto University, Sakyo-ku, Kyoto, Japan DOI: 10.1109/ICMTS.2015.7106155 HOVER FOR ABSTRACT	PDF Xplore
8.3	A capacitive based piezoelectric AlN film quality test structure N. Jackson, O. Z. Olszewski, L. Keeney, A. Blake, A. Mathewson Tyndall National Institute, University College Cork Lee Maltings, Prospect Row, Cork, Ireland DOI: 10.1109/ICMTS.2015.7106139 HOVER FOR ABSTRACT	PDF Xplore
2.3	Modeling of T-model equivalent circuit for spiral inductors in 90 nm CMOS technology J. -W. Jeong, S. -K. Kwon, J. -N. Yu, S. -Y. Jang, S. -H. Oh, C. -Y. Kim1, G. -w. Lee, H. -D. Lee Department of Electronics Engineering, Chungnam National Univ., Yuseong, Daejeon, Korea 1Department of Electronics Engineering, Chungnam National University, Daejeon, Daejeon, KR DOI: 10.1109/ICMTS.2015.7106104 HOVER FOR ABSTRACT	PDF Xplore
1.1	14nm BEOL TDDB reliability testing and defect analysis T. Kane IBM Systems Technology Group/Microelectronics Division DOI: 10.1109/ICMTS.2015.7106094 HOVER FOR ABSTRACT	PDF Xplore
7.3	Novel sheet resistance measurement on AlGaN/GaN HEMT wafer adapted from four-point probe technique J. Lehmann, C. Leroux, G. Reimbold, M. Charles, A. Torres, E. Morvan, Y. Baines, G. Ghibaudo1, E. Bano1 Univcrsité Grenoble Alpes, Grenoble, cedex, France 1IMEP-LAHC, Grenoble cedex 1 DOI: 10.1109/ICMTS.2015.7106134 HOVER FOR ABSTRACT	PDF Xplore
4.7	Elastic instabilities induced large surface strain sensing structures (EILS) Y. Li, J. G. Terry1, S. Smith1, A. J. Walton1, G. McHale, B. Xu Faculty of Engineering and Environment, Northumbria University, Newcastle upon Tyne, UK 1SMC Institute for Integrated Micro and Nano Systems School of Engineering, The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2015.7106116 HOVER FOR ABSTRACT	PDF Xplore
2.1	SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells S. Martinie, O. Rozeau, M. Tadayoni1, C. Raynaud, E. Nowak, S. Hariharan2, N. Do2 CEA-LETI, Grenoble, Cedex 9, France 1Silicon Storage Technology Inc, Sunnyvale, CA, US 2Silicon Storage Technology Inc., Microchip Technology Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2015.7106102 HOVER FOR ABSTRACT	PDF Xplore
4.5	A test structure for reliability analysis of CMOS devices under DC and high frequency AC stress T. Matsuda, K. Ichihashi, H. Iwata, T. Ohzone1 Department of Information Systems Engineering, Toyama Prefectural University 1Dawn Enteprise, Nagoya, Japan DOI: 10.1109/ICMTS.2015.7106114 HOVER FOR ABSTRACT	PDF Xplore
6.2	A novel new gate charge measurement method A. Mikata, H. Kakitani, R. Takeda, A. Wadsworth Keysight Technologies, Hachioji-shi, Tokyo, Japan DOI: 10.1109/ICMTS.2015.7106124 HOVER FOR ABSTRACT	PDF Xplore
3.1	Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy G. Moore, J. -H. Liao, S. McDade1, B. Verzi1 IBM Microelectronics, NY, USA 1Keysight Technologies, Burlington, VT, USA DOI: 10.1109/ICMTS.2015.7106106 HOVER FOR ABSTRACT	PDF Xplore
6.1	Monitoring test structure for plasma process induced charging damage using charge-based capacitance measurement (PID-CBCM) S. Mori, K. Ogawa, H. Oishi, T. Suzuki, M. Tomita, M. Bairo, Y. Fukuzaki, H. Ohnuma Sony Corporation, Kanagawa, Japan DOI: 10.1109/ICMTS.2015.7106123 HOVER FOR ABSTRACT	PDF Xplore
5.3	Threshold voltage extraction method in field-effect devices with power-law dependence of mobility on carrier density V. Mosser, D. Seron1, Y. Haddab ITRON SAS, Issy Technology Center 1Itron SAS, Malakoff, FR DOI: 10.1109/ICMTS.2015.7106121 HOVER FOR ABSTRACT	PDF Xplore
3.2	Employing an on-die test chip for maximizing parametric yields of 28nm parts J. Mueller, S. Jallepalli, R. Mooraka, S. Hector Freescale Semiconductor, Austin, Tx, USA DOI: 10.1109/ICMTS.2015.7106107 HOVER FOR ABSTRACT	PDF Xplore
9.1	Silicon measurements of characteristics for passgate/pull-down/pull-up MOSs and search MOS in a 28 nm HKMG TCAM bitcell K. Nii, K. Yamaguchi, M. Yabuuchi, N. Watanabe, T. Hasegawa, S. Yoshida, T. Okagaki, M. Yokota, K. Onozawa Renesas Electronics Corporation, Tokyo, Japan DOI: 10.1109/ICMTS.2015.7106140 HOVER FOR ABSTRACT	PDF Xplore
4.6	Measurement and modeling of IC self-heating including cooling system properties T. Nishimura, H. Tanoue, Y. Oodate, H. J. Mattausch, M. Miura-Mattausch Graduate School of Advanced Science of Matter, Hiroshima University, Higashi-Hiroshima, Japan DOI: 10.1109/ICMTS.2015.7106115 HOVER FOR ABSTRACT	PDF Xplore
5.4	Measurement of Vth variation due to STI stress and inverse narrow channel effect at ultra-low voltage in a variability-suppressed process Y. Ogasahara, M. Hioki, T. Nakagawa, T. Sekigawa, T. Tsutsumi, H. Koike Industrial Science and Technology(AIST), National Institute of Advanced, Tsukuba, Japan DOI: 10.1109/ICMTS.2015.7106122 HOVER FOR ABSTRACT	PDF Xplore
9.3	Reduction of overhead in adaptive body bias technology due to triple-well structure based on measurement and simulation Y. Ogasahara, T. Sekigawa, M. Hioki, T. Nakagawa, T. Tsutsumi, H. Koike National Institute of Advanced Industrial Science and Technology(AIST), Tsukuba, Japan DOI: 10.1109/ICMTS.2015.7106154 HOVER FOR ABSTRACT	PDF Xplore
6.3	Area and performance study of FinFET with detailed parasitic capacitance analysis in 16nm process node T. Okagaki, K. Shibutani, H. Matsushita, H. Ojiro, M. Morimoto, Y. Tsukamoto, K. Nii, K. Onozawa Renesas Electronics Corp, Tokyo, Japan DOI: 10.1109/ICMTS.2015.7106125 HOVER FOR ABSTRACT	PDF Xplore
4.8	Cross-correlation of electrical measurements via physics-based device simulations: Linking electrical and structural characteristics A. Padovani, L. Larcher, L. Vandelli, M. Bertocchi1, R. Cavicchioli1, D. Veksler2, G. Bersuker3 MDLab s.r.i., Saint Christophe, Aosta, AO, Italy 1DISMI University of Modena and Reggio Emilia, Reggio Emilia, RE, Italy 2SEMATECH, Albany, NY, USA 3NA DOI: 10.1109/ICMTS.2015.7106117 HOVER FOR ABSTRACT	PDF Xplore
7.4	Sheet resistance measurement for process monitoring of 400 °C PureB deposition on Si L. Qi, L. K. Nanver Delft University of Technology, Delft, The Netherlands DOI: 10.1109/ICMTS.2015.7106135 HOVER FOR ABSTRACT	PDF Xplore
4.1	A proposal for early warning indicators to detect impending metallization failure of DMOS transistors in cyclic operation M. Ritter, M. Pfost Robert Bosch Center for Power Electronics, Reutlingen University Alteburgstr. 150, Reutlingen, Germany DOI: 10.1109/ICMTS.2015.7106097 HOVER FOR ABSTRACT	PDF Xplore
1.3	Circuit architecture and measurement technique to reduce the leakage current stemming from peripheral circuits with an array structure in examining the resistive element S. Sato, T. Ito, Y. Omura Kansai University, Suita, Osaka, Japan DOI: 10.1109/ICMTS.2015.7106096 HOVER FOR ABSTRACT	PDF Xplore
6.4	In-line monitoring test structure for Charge-Based Capacitance Measurement (CBCM) with a start-stop self-pulsing circuit K. Sawada, G. Van der Plas1, S. Mori, C. Vladimir1, A. Mercha1, V. Diederik1, Y. Fukuzaki, H. Ammo Sony Corporation, Atsugi-shi, Kanagawa, Japan 1IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.2015.7106126 HOVER FOR ABSTRACT	PDF Xplore
4.3	The impact of deep trench and well proximity on MOSFET performance H. Sheng, T. Bettinger, J. Bates Freescale Semiconductor Inc., Tempe, AZ, USA DOI: 10.1109/ICMTS.2015.7106113 HOVER FOR ABSTRACT	PDF Xplore
4.2	Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via H. Shinkawata, N. Tsuboi, A. Tsuda1, S. Sato2, Y. Yamaguchi Renesas Electronics Corporation, Production and Technology Unit, Hitachinaka-shi, Ibaraki-ken, Japan 1Renesas System Design Corporation, Tokyo, Japan 2Kansai University, Suita, Osaka, Japan DOI: 10.1109/ICMTS.2015.7106112 HOVER FOR ABSTRACT	PDF Xplore
8.1	Test structures for the wafer mapping and correlation of electrical, mechanical and high frequency magnetic properties of electroplated ferromagnetic alloy films E. Sirotkin, S. Smith, R. Walker, J. G. Terry, A. J. Walton Scottish Microelectronics Centre, University of Edinburgh, United Kingdom DOI: 10.1109/ICMTS.2015.7106137 HOVER FOR ABSTRACT	PDF Xplore
1.2	A novel structure of MOSFET array to measure ioff-ion with high accuracy and high density T. Suzuki, A. Anchlia1, V. Cherman2, H. Oishi, S. Mori, J. Ryckaert2, K. Ogawa, G. Van der Plas2, E. Beyne2, Y. Fukuzaki, D. Verkest2, H. Ohnuma Sony Corporation, Kanagawa, Japan 1imec vzw (currently working for XENICS corporation) 2imec vzw, Kapeldreef75, Belgium DOI: 10.1109/ICMTS.2015.7106095 HOVER FOR ABSTRACT	PDF Xplore
7.5	Combined transmission line measurement structures to study thin film resistive sensor fabrication A. Tabasnikov, A. J. Walton, S. Smith Institute for Integrated Micro and Nano Systems, The niversity of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2015.7106136 HOVER FOR ABSTRACT	PDF Xplore
10.3	Systematic calibration procedure of process parameters for electromagnetic field analysis of millimeter-wave CMOS devices K. Takano, K. Katayama, S. Mizukusa, S. Amakawa, T. Yoshida, M. Fujishima Hiroshima University, Graduate School of Advanced Sciences of Matter, Higashihiroshima, Hiroshima, Japan DOI: 10.1109/ICMTS.2015.7106100 HOVER FOR ABSTRACT	PDF Xplore
5.2	A simple method for characterization of MOSFET serial resistance asymmetry D. Tomaszewski, G. Głuszko, J. Malesińska, K. Domański, M. Zaborowski, K. Kucharski, D. Szmigiel, A. Sierakowski Instytut Technologii Elektronowej (ITE), Warsaw, Poland DOI: 10.1109/ICMTS.2015.7106120 HOVER FOR ABSTRACT	PDF Xplore
7.1	Design and evaluation of an integrated thin film resistor matching test structure H. Tuinhout, N. Wils, P. Huiskamp, E. de Koning NXP Semiconductors - Technology & Operations, Integrated Technology Platforms Eindhoven & Nijmegen, the Netherlands DOI: 10.1109/ICMTS.2015.7106127 HOVER FOR ABSTRACT	PDF Xplore
2.2	Compact modeling and parameter extraction strategy of normally-on MOSFET T. Umeda, Y. Hirano, D. Suzuki, A. Tone, T. Inoue, H. Kikuchihara, M. Miura-Mattausch, H. J. Mattausch Graduate School of Advanced Sciences of Matter Hiroshima University 1-3-1 Kagamiyama, Higashi-Hiroshima Hiroshima, Japan DOI: 10.1109/ICMTS.2015.7106103 HOVER FOR ABSTRACT	PDF Xplore
8.2	A fully-automated methodology and system for printed electronics foil characterization F. Vila, J. Pallarès, A. Conde, L. Terés IMB-CNM (CSIC) Cerdanyola del Vallès, Barcelona, Spain DOI: 10.1109/ICMTS.2015.7106138 HOVER FOR ABSTRACT	PDF Xplore
2.4	A four-terminal JFET compact model for high-voltage power applications W. Wu, S. Banerjee, K. Joardar Texas Instruments, Dallas, TX DOI: 10.1109/ICMTS.2015.7106105 HOVER FOR ABSTRACT	PDF Xplore
10.4	Electromagnetic field test structure chip for back end of the line metrology L. You, J. -J. Ahn, E. Hitz, J. Michelson, Y. Obeng, J. Kopanski Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2015.7106101 HOVER FOR ABSTRACT	PDF Xplore