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IEEE International Conference on Microelectronic Test Structures

ICMTS 2010 Program

2010 Program Booklet


By First Author

A test structure for statistical evaluation of pn junction leakage current based on CMOS image sensor technology
K. Abe, T. Fujisawa, H. Suzuki, S. Watabe, R. Kuroda, S. Sugawa, A. Teramoto1, T. Ohmi1
Graduate School of Engineering, University of Tohoku, Japan
1New Industry Creation Hatchery Center, University of Tohoku, Japan
DOI: 10.1109/ICMTS.2010.5466868
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Ring oscillator based embedded structure for decoupling PMOS/NMOS degradation with switching activity replication
F. Ahmed, L. Milor
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
DOI: 10.1109/ICMTS.2010.5466845
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Test circuit for measuring single-event-induced charge sharing in deep-submicron technologies
O. A. Amusan, B. L. Bhuva, M. C. Casey1, M. J. Gadlage, D. McMorrow2, J. S. Melinger2, L. W. Massengill
Electrical Engineering and Computer Science Department, Vanderbilt University, Nashville, TN, USA
1NASA, USA
2Naval Research Laboratory, Inc., Washington D.C., DC, USA
DOI: 10.1109/ICMTS.2010.5466844
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On-chip in-situ measurements of Vth and AC gain of differential pair transistors
Y. Bando, S. Takaya, T. Ohkawa1, T. Takaramoto1, T. Yamada1, M. Souda1, S. Kumashiro1, M. Nagata
Department of Computer Science and Systems Engineering, Kobe University, Japan
1MIRAI-Selete, Japan
DOI: 10.1109/ICMTS.2010.5466809
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Generation, elimination and utilization of harmonics in ring oscillators
M. Bhushan, M. B. Ketchen1
IBM Systems and Technology Group, NY, USA
1T.J. Watson Research Center, IBM Research GmbH, Yorktown Heights, NY, USA
DOI: 10.1109/ICMTS.2010.5466847
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On-wafer inductance and resistance characterization of sub-5pH deep silicon via (DSV)
V. Blaschke, R. Zwingman
TowerJazz Limited, Newport Beach, CA, USA
DOI: 10.1109/ICMTS.2010.5466839
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Combined test structure for systematic and stochastic mosfets and gate resistance process variation assessment
L. Bortesi, L. Vendrame, G. Fontana
Numonyx, Research and Development Technology Development, Agrate-Brianza, Italy
DOI: 10.1109/ICMTS.2010.5466810
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Electrical characterization of novel PMNT thin-films
W. Chen, K. G. McCarthy1, M. Çopuroğlu, S. O'Brien, R. Winfield, A. Mathewson
Tyndall National Institute, University College Cork, Ireland
1Department of Electrical & Electronic Engineering, University College Cork, Ireland
DOI: 10.1109/ICMTS.2010.5466848
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Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device
S. H. Choi, Y. H. Park, C. H. Park, S. H. Lee, M. H. Yoo, G. T. Kim1
CAE, Semiconductor Research and Development Center, Samsung Electronics Company Limited, Hwasung, South Korea
1School of Electrical Engineering, Korea University, South Korea
DOI: 10.1109/ICMTS.2010.5466864
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A universal structure for SRAM cell characterization
X. Deng, T. W. Houston, A. Duong, W. K. Loh
Texas Instruments, Inc., Dallas, TX, USA
DOI: 10.1109/ICMTS.2010.5466815
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Novel test structures for temperature budget determination during wafer processing
E. J. Faber, R. A. M. Wolters1, J. Schmitz
MESA Institute of Nanotechnology, Semiconductor Components Group, University of Twente, Enschede, Netherlands
1NXP Semiconductors, Eindhoven, Netherlands
DOI: 10.1109/ICMTS.2010.5466867
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Fast RF-CV characterization through high-speed 1-port S-parameter measurements
R. W. Herfst, P. G. Steeneken1, M. P. J. Tiggelman, J. Stulemeijer2, J. Schmitz
MESA Institute of Nanotechnology, University of Twente, Enschede, Netherlands
1NXP Semiconductors, Eindhoven, Netherlands
2Surface Acoustic Wave Components Division, EPCOS Netherlands B.V., Nijmegen, Netherlands
DOI: 10.1109/ICMTS.2010.5466829
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An embedded process monitor test chip architecture
S. Idgunji, V. Chandra, C. Pietrzyk, I. Iqbal, R. Aitken, G. Yeric1
Research and Development, ARM, Inc., San Jose, CA, USA
1Research and Development, ARM, Inc., Austin, TX, USA
DOI: 10.1109/ICMTS.2010.5466842
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Investigation on the field leakage current in 0.35μm CMOS technology at high temperature
S. T. Kong, P. S. Ronald, C. Lee
X-FAB Semiconductor Foundries AG, Plymouth, UK
DOI: 10.1109/ICMTS.2010.5466849
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A bulk micromachined vertical nano-gap Pirani wide-range pressure test structure for packaged MEMS performance monitoring
M. Kubota, T. Okada1, Y. Mita1, M. Sugiyama, Y. Nakano2
Institute of Engineering Innovation, Graduate School of Engineering, University of Tokyo, Bunkyo, Tokyo, Japan
1Department of Electrical Engineering and Information Systems, Graduate School of Engineering, University of Tokyo, Bunkyo, Tokyo, Japan
2Research Center of Advanced Science and Technology, University of Tokyo, Bunkyo, Tokyo, Japan
DOI: 10.1109/ICMTS.2010.5466871
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Test structures for characterising the integration of EWOD and SAW technologies for microfluidics
Y. Li, Y. Q. Fu1, B. W. Flynn, W. Parkes, Y. Liu1, S. Brodie1, J. G. Terry, L. I. Haworth, A. S. Bunting, J. T. M. Stevenson, S. Smith, A. J. Walton
Institute of Integrated Micro and Nano Systems (IMNS), [Part of the Institute of Integrated Systems], School of Engineering, University of Edinburgh, UK
1Microsystems Engineering Centre, [Part of the Institute of Integrated Systems], School of Engineering and Physical Sciences, Heriot-Watt University, Edinburgh, UK
DOI: 10.1109/ICMTS.2010.5466861
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A test vehicle and a two step procedure to evaluate a massive number of single-walled carbon nanotube field effect transistors
I. Martin-Fernandez, M. Sansa, F. Perez-Murano, P. Godignon, E. Lora-Tamayo
Instituto de Microelectrónica de Barcelona-Centro Nacional de Microelectrónica-Consejo Superior de Investigaciones Cientä­ficas, Cerdanyola del Valles, Spain
DOI: 10.1109/ICMTS.2010.5466860
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Comprehensive quality assurance methodology for BSIM4.5 corner parameter extraction
H. Masuda, S. Itoh1, H. Koike2, N. Wakita3, R. Inagaki4
Renesas Technology Corporation, Japan
1Seiko-Epson Corporation, Russia
2Semiconductor Technology, Academic Research Center, Japan
3Toshiba Corporation, Japan
4Rohm Company Limited, Thailand
DOI: 10.1109/ICMTS.2010.5466819
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Orientation dependence and asymmetry of subthreshold characteristics in CMOSFETs
T. Matsuda, Y. Matsumura, H. Iwata, T. Ohzone1
Department of Information Systems Engineering, Toyama Prefectural University, Toyama, Japan
1Dawn Enterprise, Nagoya, Japan
DOI: 10.1109/ICMTS.2010.5466854
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Pulsed measurement method for characterizing chemical solutions using nanowire field effect transistors
M. Mescher, B. Marcelis, M. de Wild, J. H. Klootwijk
Micro Systems and Devices, Philips Research Eindhoven, Netherlands
DOI: 10.1109/ICMTS.2010.5466863
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Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design
N. Minas, G. Van der Plas, H. Oprins, Y. Yang1, C. Okoro1, A. Mercha, V. Cherman, C. Torregiani, D. Perry2, M. Cupac, M. Rakowski, P. Marchal
IMEC, Belgium
1Katholieke Universiteit Leuven, Belgium
2Qualcomm CDMA Technologies, Inc., Leuven, Belgium
DOI: 10.1109/ICMTS.2010.5466836
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A Balanced-SeeSaw MEMS swing probe for vertical profilometry of deep micro structures
Y. Mita, J. -B. Pourciel1, M. Kubota1, S. Ma1, S. Morishita1, A. Tixier-Mita1, T. Masuzawa1
University of Tokyo, Japan
1LAAS-CNRS, Université de Toulouse, France
DOI: 10.1109/ICMTS.2010.5466858
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Correlation between Direct Charge Measurement (DCM) and LCR meter on deep submicron CMOS test structure capacitance measurement
Y. Miyake, M. Goto, S. Fujii, H. Nishimura
Agilent Technologies International Japan Limited, Japan
DOI: 10.1109/ICMTS.2010.5466830
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Fully understanding the mechanism of misalignment-induced narrow-transistor failure and carefully evaluating the misalignment-tolerant SRAM-cell layout
S. Nakai, Y. Miyazaki, R. Nakamura, M. Suga, T. Tsuruta, M. Yasuda1, T. Kashiwagi, Y. Maki
Fujitsu Microelectronics Limited, Japan
1Fujitsu VLSI Limited, Japan
DOI: 10.1109/ICMTS.2010.5466834
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An efficient method of calibrating MOSFET capacitances by way of excluding intra- DUT parasitic contributions
Y. Naruta, R. Koh, T. Iizuka
NEC Electronics Corporation Limited, Kawasaki, Japan
DOI: 10.1109/ICMTS.2010.5466828
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Small embedded sensors for accurate temperature measurements in DMOS power transistors
M. Pfost, D. Costachescu, A. Podgaynaya1, M. Stecher2, S. Bychikhin2, D. Pogany2, E. Gornik2
Infineon Technologies Romania, IFRO ATV TM, Bucharest, Romania
1Infineon Technologies AG, ATV PTP TSP, Neubiberg, Germany
2Institute of Solid-State Electronics, University of Technology, Vienna, Vienna, Austria
DOI: 10.1109/ICMTS.2010.5466872
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A test structure for integrated capacitor array matching characterization
W. Posch, G. Promitzer, E. Seebacher
Austria Microsystems AG, Austria
DOI: 10.1109/ICMTS.2010.5466833
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Characterization & modeling of gate-induced-drain-leakage with complete overlap and fringing model
D. Rideau, V. Quenette, D. Garetto1, E. Dornel1, M. Weybright1, J. P. Manceau1, O. Saxod, C. Tavernier, H. Jaouen
STMicroelectronics, Crolles CEDEX, France
1IBM France, Crolles, France
DOI: 10.1109/ICMTS.2010.5466816
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A unique and accurate extraction technique of the asymmetric bottom-pillar resistance for the vertical MOSFET
K. Sakui, T. Endoh
Center of Interdisciplinary Research, JST-CREST, University of Tohoku, Sendai, Japan
DOI: 10.1109/ICMTS.2010.5466812
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On the validity of bisection-based thru-only de-embedding
T. Sekiguchi, S. Amakawa, N. Ishihara, K. Masu
Integrated Research Institute, Tokyo Institute of Technology, Yokohama, Japan
DOI: 10.1109/ICMTS.2010.5466857
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Analysis of the performance of a micromechanical test structure to measure stress in thick electroplated metal films
S. Smith, N. L. Brockie, J. Murray, C. J. Wilson1, A. B. Horsfall2, J. G. Terry, J. T. M. Stevenson, A. R. Mount3, A. J. Walton
Institute of Integrated Micro and Nano Systems (Part of the Joint Research Institute of Integrated Systems), School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK
1IMEC, Leuven, Belgium
2School of Electrical, Electronic and Computer Engineering, Merz Court, University of Newcastle, Newcastle-upon-Tyne, UK
3School of Chemistry, Joseph Black Building, University of Edinburgh, Edinburgh, UK
DOI: 10.1109/ICMTS.2010.5466852
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Fabrication of test structures to monitor stress in SU-8 films used for MEMS applications
S. Smith, N. L. Brockie, J. Murray, C. J. Wilson1, A. B. Horsfall2, J. G. Terry, J. T. M. Stevenson, A. R. Mount3, A. J. Walton
Institute of Integrated Micro and Nano Systems (Part of the Joint Research Institute of Integrated Systems), School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK
1IMEC, Leuven, Belgium
2School of Electrical, Electronic and Computer Engineering, Merz Court, University of Newcastle, Newcastle-upon-Tyne, UK
3School of Chemistry, Joseph Black Building, University of Edinburgh, Edinburgh, UK
DOI: 10.1109/ICMTS.2010.5466870
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Kelvin resistor structures for the investigation of corner serif Proximity Correction
S. Smith, A. Tsiamis, M. McCallum1, A. C. Hourd2, J. T. M. Stevenson, A. J. Walton
Institute of Integrated Micro and Nano Systems (Part of the Joint Research Institute of Integrated Systems), School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, UK
1Nikon Precision Europe GmbH, HoustonSuite, Livingston, UK
2Division of Electronic Engineering & Physics, Harris Building, University of Dundee, Dundee, UK
DOI: 10.1109/ICMTS.2010.5466866
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Test structures for characterization of through silicon vias
M. Stucchi, D. Perry1, G. Katti2, W. Dehaene2
IMEC, Leuven, Belgium
1Qualcomm CDMA Technologies, San Diego, CA, USA
2ESAT Department, Katholieke Universiteit Leuven, Leuven, Belgium
DOI: 10.1109/ICMTS.2010.5466841
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MOSFET-array for extracting parameters expressing SPICE-parameter variation
K. Terada, N. Ekida, K. Tsuji, T. Tsunomura1, A. Nishida1
Faculty of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan
1MIRAI-Selete, Tsukuba, Ibaraki, Japan
DOI: 10.1109/ICMTS.2010.5466855
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New RF intrinsic parameters extraction procedure for advanced MOS transistors
J. C. Tinoco, A. G. Martinez-Lopez1, M. Emam2, J. . -P. Raskin2
Departamento de Ingenierä­a en Telecomunicaciones, División de Ingenierä­a Eléctrica, Facultad de Ingenierä­a, Universidad Nacional Auténoma de México, Mexicali, Mexico
1Col. Jardä­nes de San German, Puerto de Tuxpan s/n entre Puerto Tampico y Chetumal, Universidad Politécnica de la Región Ribereä±a, Tamaulipas, Mexico
2Microwave Laboratory, Université catholique de Louvain, Louvain-la-Neuve, Belgium
DOI: 10.1109/ICMTS.2010.5466853
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Highly automated sequence for Phase Change Memory test structure characterization
A. Toffoli, A. Fantini, G. Betti Beneventi1, L. Perniola, R. Kies, V. Vidal2, J. F. Nodin, V. Sousa, A. Persico, J. Cluzel, C. Jahan, S. Maitrejean, G. Reimbold, B. DeSalvo, F. Boulanger
CEA-LETI Minatec Grenoble, Grenoble, France
1Universita degli Studi di Modena e Reggio Emilia, Reggio Emilia, Italy
2STMicroelectronics, Crolles, France
DOI: 10.1109/ICMTS.2010.5466865
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SIS wide-band model extraction methodology for SOI on-chip inductor
R. O. Topaloglu, J. -S. Goo, A. L. S. Loke1, M. M. Oshima1, S. W. Sim1
Global Foundries, Inc., Sunnyvale, CA, USA
1Advanced Micro Devices, Inc., Sunnyvale, CA, USA
DOI: 10.1109/ICMTS.2010.5466850
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Test structures to quantify contact placement-impacted drain current variations
R. O. Topaloglu, Z. -Y. Wu, A. B. Icel
Global Foundries, Inc., Sunnyvale, CA, USA
DOI: 10.1109/ICMTS.2010.5466822
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Methodology to evaluate long channel matching deterioration and effects of transistor segmentation on MOSFET matching
H. Tuinhout, N. Wils, M. Meijer, P. Andricciola
NXP Semiconductors Central Research and Development/Research, Eindhoven, Netherlands
DOI: 10.1109/ICMTS.2010.5466824
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Direct probing of trapped charge dynamics in SiN by Kelvin Force Microscopy
E. Vianello, E. Nowak1, D. Mariolle1, N. Chevalier1, L. Perniola1, G. Molas1, J. P. Colonna1, F. Driussi, L. Selmi
DIEGM, University of Udine-IUNET, Udine, Italy
1CEA-LETI Minatec Grenoble, Grenoble, France
DOI: 10.1109/ICMTS.2010.5466851
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Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies
N. Wils, H. Tuinhout, M. Meijer
NXP Semiconductors Central Research and Development/Research, Eindhoven, Netherlands
DOI: 10.1109/ICMTS.2010.5466825
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Compact models of parasitic resistance of resistors for analog circuits
K. Yamada
Technology Foundation Dev. Op. Unit, Core Development Division, NEC Electronics Corporation Limited, Kawasaki, Kanagawa, Japan
DOI: 10.1109/ICMTS.2010.5466818
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Global parameter extraction for a multi-gate MOSFETs compact model
S. Yao, T. H. Morshed, D. D. Lu, S. Venugopalan, W. Xiong1, C. R. Cleavelin, A. M. Niknejad, C. Hu
Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, USA
1SiTD, Texas Instruments, Inc., Dallas, TX, USA
DOI: 10.1109/ICMTS.2010.5466821
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