IEEE International Conference on Microelectronic Test Structures
ICMTS 1994 Program
By First Author
| Application of the modified voltage-dividing potentiometer to overlay metrology in a CMOS/bulk process R. A. Allen, M. W. Cresswell, L. W. Linholm, J. C. Owen, C. H. Ellenwood, T. A. Hill1, J. D. Benecke1, S. R. Volk1, H. D. Stewart1 Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Silicon IC Patterning Department, Sandia National Laboratories, Albuquerque, NM, USA DOI: 10.1109/ICMTS.1994.303504 HOVER FOR ABSTRACT | PDF Xplore | |
| Temperature-controlled wafer level Joule-heated constant-current EM tests of W/AlCuSi/W wires Y. Anata, Y. Fujisaki, M. Kawaji, H. Katto, M. Kubo Device Development Center, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1994.303486 HOVER FOR ABSTRACT | PDF Xplore | |
| Accuracy of channel resistance and current gain methods of Leff extraction S. S. Bhattacharya, E. R. Worley, R. A. Williams Digital Communications Division, Rockwell International Corporation, Newport Beach, CA, USA DOI: 10.1109/ICMTS.1994.303477 HOVER FOR ABSTRACT | PDF Xplore | |
| Inverter matrix for the Clementine mission M. G. Buehler, B. R. Blaes, G. Tardio, G. A. Soli Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1994.303476 HOVER FOR ABSTRACT | PDF Xplore | |
| Worst-case MOSFET parameter extraction for a 2 µm CMOS process K. Burke, J. A. Power1, B. Donnellan1, K. Moloney1, W. A. Lane1 Analog Devices B.V., Limerick, Ireland 1NA DOI: 10.1109/ICMTS.1994.303491 HOVER FOR ABSTRACT | PDF Xplore | |
| On-wafer high-frequency measurement improvements J. L. Carbonero, R. Joly, G. Morin, B. Cabon1 Central R&D, SGS-THOMSON Microelectronics, Crolles, France 1LEMO ENSERG LNPG-URA CNRS 833, Grenoble, France DOI: 10.1109/ICMTS.1994.303482 HOVER FOR ABSTRACT | PDF Xplore | |
| An experimental investigation of EEPROM reliability issues using the progressional offset technique A. J. Chester, A. J. Walton, P. Tuohy1 GEC Plessey Semiconductors Limited, Plymouth, UK 1NA DOI: 10.1109/ICMTS.1994.303472 HOVER FOR ABSTRACT | PDF Xplore | |
| Fast and accurate on-wafer extraction of parasitic resistances in GaAs MESFET's P. Debie, L. Martens, D. De Zutter Department of Information Technology, University of Ghent, Ghent, Belgium DOI: 10.1109/ICMTS.1994.303512 HOVER FOR ABSTRACT | PDF Xplore | |
| Sources of error in the extraction of ΔW [MOSFET models] M. Fallon, A. J. Walton Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1994.303507 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for extraction of MOSFET capacitances H. Gaffur, Sukyoon Yoon Fairchild Research Center, National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1994.303511 HOVER FOR ABSTRACT | PDF Xplore | |
| An automated wafermap fast test for bipolar induced breakdown in NMOS transistors G. J. Gaston, B. S. Bold, J. B. Mason GEC Plessey Semiconductors Limited, Plymouth, UK DOI: 10.1109/ICMTS.1994.303508 HOVER FOR ABSTRACT | PDF Xplore | |
| Current and temperature distribution impact on electromigration failure location in SWEAT structure F. Giroux, C. Gounelle, N. Vialle, P. Mortini, G. Ghibaudo1 Central R&D, SGS-Thomson Microelectronics, Crolles, France 1LPCS-ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1994.303473 HOVER FOR ABSTRACT | PDF Xplore | |
| Automatic process monitor generation W. Hansford The MOSIS Service Informtion Science Institute, USC, CA, USA DOI: 10.1109/ICMTS.1994.303481 HOVER FOR ABSTRACT | PDF Xplore | |
| Drop in process control checkerboard test structure for efficient online process characterization and defect problem debugging C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance (Prof. Dr. D. Schmid), University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1994.303485 HOVER FOR ABSTRACT | PDF Xplore | |
| Modeling of test structures for efficient online defect monitoring using a digital tester C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance (Prof. Dr. D. Schmid), University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1994.303493 HOVER FOR ABSTRACT | PDF Xplore | |
| A systematic test methodology for identifying defect-related failure mechanisms in an EEPROM technology D. M. Hoffstetter, M. H. Manley National Semiconductor, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1994.303492 HOVER FOR ABSTRACT | PDF Xplore | |
| A simple test structure for accurately monitoring channel doping variations in a MOSFET K. Joardar Motorola Semiconductor Products Sector, Mesa, AZ, USA DOI: 10.1109/ICMTS.1994.303499 HOVER FOR ABSTRACT | PDF Xplore | |
| A direct method to extract effective geometries and series resistances of MOS transistors P. R. Karlsson, K. O. Jeppson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1994.303479 HOVER FOR ABSTRACT | PDF Xplore | |
| New test structures for on-chip absolute and accurate measurement of capacitances in a CMOS process A. Khalkhal, P. Girard, P. Nouet Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), U. M. R. 9928 Universite Montpellier II/Cnrs, Montpellier, France DOI: 10.1109/ICMTS.1994.303489 HOVER FOR ABSTRACT | PDF Xplore | |
| SRAM-based extraction of defect characteristics J. Khare, W. Maly, S. Griep1, D. Schmitt-Landsiedel1 Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA 1Siemens AG Corporate Research and Development, Munchen, Germany DOI: 10.1109/ICMTS.1994.303494 HOVER FOR ABSTRACT | PDF Xplore | |
| A global optimization of bipolar model parameters using simulated diffusion Moonho Kim, Deokro Yoon, Soongjoon Cha, Joohyun Jin, Soonkwon Lim, Kyuhyun Choi Semiconductor R&D Center, Samsung Electronics Company Limited, Bucheon, Kyunggi, South Korea DOI: 10.1109/ICMTS.1994.303513 HOVER FOR ABSTRACT | PDF Xplore | |
| A test pattern to investigate the effect of capping layers on the hot carrier induced photon spectra of MOSFETs M. Lanzoni, L. Selmi, R. Bez1, M. Manfredi2 DEIS, Università di Bologna, Bologna, Italy 1SGS-Thomson, Italy 2Department of Physics, University of Parma, Parma, Italy DOI: 10.1109/ICMTS.1994.303475 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization of SOI-MOSFET with the channel conductance transient spectroscopy Gyoo-Yeong Lee Semiconductor R&D Laboratories, Hyundai Electronics Industries Company Limited, Kyunggi, South Korea DOI: 10.1109/ICMTS.1994.303506 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement and modeling of size and proximity effects in conductor linewidths U. Lieneweg, N. Zamani Center for Space Microelectronics Technology, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1994.303503 HOVER FOR ABSTRACT | PDF Xplore | |
| Accurate characterization of MOSFET overlap/fringing capacitance for circuit design C. C. McAndrew, G. Zaneski1, P. A. Layman, S. G. Ayyar1 AT&T Bell Labaratories, Allentown, PA, USA 1AT and T Bell Laboratories, Allentown, PA, USA DOI: 10.1109/ICMTS.1994.303510 HOVER FOR ABSTRACT | PDF Xplore | |
| Fault test structures for studying circuit performance M. A. Mitchell, T. Nguyen Solid State Electronics Center, Honeywell, Inc., Plymouth, MN, USA DOI: 10.1109/ICMTS.1994.303495 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure of a MOSFET with Si-implanted gate-SiO2 for EEPROM applications T. Ohzone, T. Hori1 Department of Electronics and Infortmatics, Toyama Prefectural University, Toyama, Japan 1Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1994.303488 HOVER FOR ABSTRACT | PDF Xplore | |
| SOI device parameter investigation and extraction for VLSI radiation hardness modeling with SPICE K. O. Petrosjanc, A. S. Adonin1, I. A. Kharitonov, M. V. Sicheva Moscow University of Electronics and Mathematics, Moscow, Russia 1Scientific Research Institute Sapphire, Moscow, Russia DOI: 10.1109/ICMTS.1994.303490 HOVER FOR ABSTRACT | PDF Xplore | |
| Series resistance and effective gate length extraction on short-channel PMOS devices at liquid nitrogen temperature F. J. Garcia Sanchez, A. Ortiz-Conde1, M. Garcia Nunez2, R. L. Anderson3 Departamento de Electrónica, Universidad Simón Bolävar, Caracas, Venezuela 1Dept. de Electron., Simon Bolivar Univ., Caracas, Venezuela 2Instituto de Ingenieria, Caracas, Venezuela 3Cryoelectronics Laboratory, University of Vermont, Burlington, VT, USA DOI: 10.1109/ICMTS.1994.303478 HOVER FOR ABSTRACT | PDF Xplore | |
| A test chip and an accurate measurement system to characterize hot hole injection in the gate oxide of p-MOSFETs L. Selmi, E. Sangiorgi, R. Bez1, B. Ricco DEIS, University of Bologna, Bologna, Italy 1SGS-Thomson, Italy DOI: 10.1109/ICMTS.1994.303501 HOVER FOR ABSTRACT | PDF Xplore | |
| Novel test structures for process development and monitoring of stack etches for high density FLASH and EPROM memories E. Shacham, G. Wolstenholme1, J. Perry, N. Narahai, A. Bergemont National Semiconductor Corporation, Santa Clara, CA, USA 1Micron Technology, Boise, ID, USA DOI: 10.1109/ICMTS.1994.303496 HOVER FOR ABSTRACT | PDF Xplore | |
 | Self-stressing structures for electromigration testing to 500 MHz E. S. Snyder, D. G. Pierce, D. V. Campbell, S. E. Swanson Sandia National Laboratories, Electronics Quality Reliability Center, Albuquerque, USA DOI: 10.1109/ICMTS.1994.303502 HOVER FOR ABSTRACT | PDF Xplore |
| Methodology of process evaluation with wafer-mapping techniques for statistical process control T. Takeda NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1994.303497 HOVER FOR ABSTRACT | PDF Xplore | |
| Development of the test insert generating expert routine (TIGER) for BiCMOS technologies S. W. Tarasewicz, R. A. Horner1 Northern Telecom Limited, Ottawa, ONT, Canada 1Test Engineering Department, Mitel Corporation, Inc., Kanata, ONT, Canada DOI: 10.1109/ICMTS.1994.303480 HOVER FOR ABSTRACT | PDF Xplore | |
| Design of matching test structures [IC components] H. P. Tuinhout Philips Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1994.303509 HOVER FOR ABSTRACT | PDF Xplore | |
| Automated gated diode measurements for device characterization B. Verzi, P. Aum1 Semiconductor Test Business Unit, Hewlett-Packard U. S. Field Operations, Austin, TX, USA 1Hewlett-Packard SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1994.303487 HOVER FOR ABSTRACT | PDF Xplore | |
| A modified Gaudi structure for the optimisation of the focus of wafer steppers A. J. Walton, M. Fallon, J. T. M. Stevenson, A. W. S. Ross, C. M. Reeves Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1994.303498 HOVER FOR ABSTRACT | PDF Xplore | |
| Error correction in high-frequency "on-wafer" measurements J. Weng School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore DOI: 10.1109/ICMTS.1994.303483 HOVER FOR ABSTRACT | PDF Xplore | |
| Automatic in-line to end-of-line defect correlation using FSRAM test structure for quick killer defect identification D. Wilson, A. J. Walton1 Kelvin Industrial Estate East Kilbride, Motorola Limited, Glasgow, UK 1Department of Electrical Engineering, Edinburgh Microfabrication Facility, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1994.303484 HOVER FOR ABSTRACT | PDF Xplore | |
| Assessment of electro-static discharge robustness based on the monitoring of lattice temperature of silicon K. D. Yoo, G. H. Lim, J. H. Jin, K. H. Choi Samsung Electronics, Semiconductor R&D, Micro Process Development, Kyunggi, South Korea DOI: 10.1109/ICMTS.1994.303474 HOVER FOR ABSTRACT | PDF Xplore | |
| Reliability analysis of gate oxide using bi-Poisson model to evaluate the crystal defect effect J. Yugami, M. Ohkura Central Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan DOI: 10.1109/ICMTS.1994.303500 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for determining design rules for microelectromechanical-based sensors and actuators C. Zincke, M. Gaitan1, M. E. Zaghloul, L. W. Linholm1 School of Engineering and Applied Science, George Washington University, WA, USA 1Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1994.303505 HOVER FOR ABSTRACT | PDF Xplore |
