IEEE International Conference on Microelectronic Test Structures
ICMTS 1993 Program
By First Author
| A methodology for pre-determination of bipolar SPICE model parameters in BiCMOS technology S. Aggarwal, A. Juge SGS-Thomson Microelectronics, Central Research and Development, Device Modeling, Grenoble, France DOI: 10.1109/ICMTS.1993.292900 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure for transferring timing setup between digital IC testers L. Allodi, G. Chiorboli, G. Franco, C. Morandi, F. Venturi Dipartimento di Ingegneria dell' Informazione, Università di Parma, Parma, Italy DOI: 10.1109/ICMTS.1993.292916 HOVER FOR ABSTRACT | PDF Xplore | |
 | Modeling and characterization of MOSFET width dependencies R. A. Ashton, P. A. Layman1, C. C. McAndrew1 AT and T Bell Laboratories, Inc., Orlando, FL, USA 1AT and T Bell Laboratories, Inc., Allentown, PA, USA DOI: 10.1109/ICMTS.1993.292881 HOVER FOR ABSTRACT | PDF Xplore |
| SEU/SRAM as a process monitor B. R. Blaes, M. G. Buehler Jet Propulsion Laboratory, Pasadena, CA, USA DOI: 10.1109/ICMTS.1993.292893 HOVER FOR ABSTRACT | PDF Xplore | |
| A method for modeling the manufacturability of IC designs E. D. Boskin, C. J. Spanos, G. Korsh1 Department of Electrical Engineering & Computer Sciences, University of California, Berkeley, CA, USA 1ATMEL Corporation, San Jose, CA, USA DOI: 10.1109/ICMTS.1993.292912 HOVER FOR ABSTRACT | PDF Xplore | |
| An easy technique for determining diffusion and generation-recombination components of the current of pn junctions for better modelling C. Cane, M. Lozano, I. Gracia1, J. Santander, E. Lora-Tamayo Center Nacional de Microelectgrónica, Universitat Autònoma de Barcelòna, Barcelona, Spain 1Centre Nacional de Microelectron., Univ. Autonoma de Barcelona, Spain DOI: 10.1109/ICMTS.1993.292926 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for the in-plane locations of project features with nanometer-level accuracy traceable to a coordinate measurement system M. W. Cresswell, R. A. Allen, L. W. Linholm, C. H. Ellenwood, W. B. Penzes, E. C. Teague Semiconductor Electronics Division and Precision Engineering Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1993.292910 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation of metallization systems with test structures and yield modeling C. A. DeLoach, H. G. Parks1, S. E. Beck2 Brooktree Corporation, San Diego, CA, USA 1H.G. Parks, ECE Bldg., University of Arizona Tucson, Tucson, AZ, USA 2Air Products and Chemicals, Inc., Allentown, PA, USA DOI: 10.1109/ICMTS.1993.292891 HOVER FOR ABSTRACT | PDF Xplore | |
| The use of low-level pre-tunneling currents to characterize thin oxide wearout and breakdown D. J. Dumin, J. R. Maddux, R. Subramoniam, R. S. Scott, D. . -P. Wong Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA DOI: 10.1109/ICMTS.1993.292922 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement of minimum line widths using Fallon ladders M. Fallon, A. J. Walton1 Department of Electrical Engineering, Napier University, Edinburgh, UK 1Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1993.292909 HOVER FOR ABSTRACT | PDF Xplore | |
| Characterization of SOI MOSFETs by gate capacitance measurements D. Flandre, B. Gentinne Laboratoire de Microélectronique, Louvain-la-Neuve, Belgium DOI: 10.1109/ICMTS.1993.292906 HOVER FOR ABSTRACT | PDF Xplore | |
| Proposal of standard characterization method for dynamic circuit performance M. Fujishima, K. Asada Department of Electronic Engineering, University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.1993.292915 HOVER FOR ABSTRACT | PDF Xplore | |
| Thermal measurements by use of a SBIMOS diode matrix B. Geeraerts, W. Van Petegem, W. Sansen Electrical Engineering ESAT/MICAS, Catholic University of Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1993.292923 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluations of leakage currents and capacitances on elementary CMOS devices P. Girard, P. Nouet, A. Khalkhal, F. M. Roche Laboratoire ÄInformatique, de Robotique et de Microelectronique de Montpellier (U.M.R. C09928 CNRS),Sciences et Techniques du Languedoc, Université de Montpellier II, Montpellier, France DOI: 10.1109/ICMTS.1993.292905 HOVER FOR ABSTRACT | PDF Xplore | |
| Process windows for convenient in-process monitoring of oxide and polysilicon etches K. Golshan, H. Tigelaar, M. Harward1 Regional Technology Center and Semiconductor Process and Design Center, Texas Instruments, Inc., CA, USA 1Texas Instruments Inc., Irvine, CA, USA DOI: 10.1109/ICMTS.1993.292914 HOVER FOR ABSTRACT | PDF Xplore | |
| A testset for automatic characterisation of opamps in the frequency domain C. Van Grieken, W. Sansen Department Elektrotechniek, ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1993.292889 HOVER FOR ABSTRACT | PDF Xplore | |
| Modeling of real defect outlines for defect size distribution and yield prediction C. Hess, A. Strole Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1993.292890 HOVER FOR ABSTRACT | PDF Xplore | |
| Power lateral DMOS transistor test structures S. Hidalgo, J. Fernandez, P. Godignon, J. Rebollo, J. Millan Centro Nacional de Microelectróica, Barcelona, Spain DOI: 10.1109/ICMTS.1993.292897 HOVER FOR ABSTRACT | PDF Xplore | |
| Limitations of electrical test information: a case study with polysilicon emitter contacts M. Johnson, A. J. Strojwas, D. W. Greve, R. A. Reuss1, A. Flowers2 Carnegie Mellon University, Pittsburgh, PA, USA 1Motorola, Inc., Phoenix, AZ, USA 2Texas Instrumenits, Inc., Houston, TX, USA DOI: 10.1109/ICMTS.1993.292913 HOVER FOR ABSTRACT | PDF Xplore | |
| A direct extraction algorithm for a submicron MOS transistor model P. R. Karlsson, K. O. Jeppson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1993.292928 HOVER FOR ABSTRACT | PDF Xplore | |
| A low frequency AC method to measure the doping profile in the channel region of a MOSFET with general extendability to the semiconductor surface J. D. Kendall, J. K. Kolk, A. R. Boothroyd1, D. A. Vincent2 Northern Telecom Limited, Ottawa, ONT, Canada 1Department of Electronics, Carleton University, Ottawa, ONT, Canada 2Northern Telecom Limited DOI: 10.1109/ICMTS.1993.292880 HOVER FOR ABSTRACT | PDF Xplore | |
| An implementation of CMOS design for testability techniques for non stuck-at faults M. Lanzoni, M. Favalli, P. Olivo, B. Ricco DEIS, University of Bologna, Bologna, Italy DOI: 10.1109/ICMTS.1993.292887 HOVER FOR ABSTRACT | PDF Xplore | |
| A moveable shielding box adaptable to commercial automatic wafer probers M. Lozano, C. Cane, J. Santander, I. Gracia1, E. Lora-Tamayo Centre Nacional de Microelectrònica, Universitat Autonoma de Barcelona, Barcelona, Spain 1Centre Nacional de Microelectron., Univ. Auton. de Barcelona, Spain DOI: 10.1109/ICMTS.1993.292917 HOVER FOR ABSTRACT | PDF Xplore | |
| A direct, reliable, measurement-based technique for the extraction of an on-chip HBT dummy structure equivalent circuit K. Lu, P. Perry, T. J. Brazil Department of Electronic and Electrical Engineering, University College Dublin, Dublin, Ireland DOI: 10.1109/ICMTS.1993.292898 HOVER FOR ABSTRACT | PDF Xplore | |
| SPICE DC parameter extraction of MESFETs with diffused and grown channel A. S. Lujan, I. Chueiri, J. W. Swart, F. C. Prince, P. H. Tessari1 DSIF/FEE-Electrical Engineering and LPD/IFGW-Physics Institute,State University of Campinas, State University of Campinas-UNICAMP, Sao Paulo, Brazil 1UNICAMP, State Univ. of Campinas, Sao Paulo, Brazil DOI: 10.1109/ICMTS.1993.292927 HOVER FOR ABSTRACT | PDF Xplore | |
| A test structure for E-beam testing J. Madrenas, J. Cabestany Departament dEnginyeria Electrbnica, UPC, UPC, Barcelona, Spain DOI: 10.1109/ICMTS.1993.292888 HOVER FOR ABSTRACT | PDF Xplore | |
| Direct extraction of SPICE level 3 parameters without using optimization J. . -i. Matsuda LSI Division, Semiconductor Business Headquarters, Sanyo Electric Company Limited, Ora-Gun, Gunma, Japan DOI: 10.1109/ICMTS.1993.292902 HOVER FOR ABSTRACT | PDF Xplore | |
| Junction evaluation by time dependent degradation due to high constant voltage stressing (DRAMs) J. Mitsuhashi, J. Komori, T. Eimori, H. Koyama Evaluation and Analysis Center, LSI Lab, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1993.292883 HOVER FOR ABSTRACT | PDF Xplore | |
| A flexible test structure evaluation system for reliability data analysis M. Mori, Y. Kuriyama, N. Shiono LSI Laboratories, NTT, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1993.292921 HOVER FOR ABSTRACT | PDF Xplore | |
| A test pattern for three-dimensional latch-up analysis I. De Munari, R. Menozzi, M. Davoli, F. Fantini Dipartimento di Ingegneria dell'Informazione, Università di Parma, Parma, Italy DOI: 10.1109/ICMTS.1993.292886 HOVER FOR ABSTRACT | PDF Xplore | |
| A new test device for detecting very low leakage current using DRAM cell array T. Oasa, H. Inada1, M. Fujito, T. Matsumoto Advanced Research Laboratories, Sumitomo Metal Industries Limited, Amagasaki, Hyogo, Japan 1Sumitomo Metal Ind. Ltd., Hyogo, Japan DOI: 10.1109/ICMTS.1993.292879 HOVER FOR ABSTRACT | PDF Xplore | |
| Channel-width measurements of LOCOS- and trench-isolated n-MOSFETs by photoemission T. Ohzone, H. Iwata Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.1993.292908 HOVER FOR ABSTRACT | PDF Xplore | |
| Photoemission characteristics of reverse-breakdown n+-diodes with LOCOS- and trench-isolation T. Ohzone, H. Iwata Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.1993.292924 HOVER FOR ABSTRACT | PDF Xplore | |
| The use of test structures to identify leakage failure mechanisms in CMOS inputs J. H. Orchard-Webb Kanata, ONT, Canada DOI: 10.1109/ICMTS.1993.292884 HOVER FOR ABSTRACT | PDF Xplore | |
| A new method for the experimental determination of the control gate and drain coupling ratios in FLOTOX EEPROM cells C. Papadas, B. Moison, G. Ghibaudo1, P. Mortini, G. Panankakis2 Central R&D, SGS-Thomson Microelectronics, Grenoble, France 1URA CNRS, ENSERG, Laboratories de Physique des Composants ä Semiconducteurs, Grenoble, France 2NA DOI: 10.1109/ICMTS.1993.292904 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure metrology of homogeneous contamination H. G. Parks, R. D. Schrimpf, R. Craigin, R. Jones1, P. Resnick1 Electrical and Computer Engineering Department, University of Arizona Tucson, Tucson, AZ, USA 1Microelectronics Development Laboratory, Sandia National Laboratories, Albuquerque, NM, USA DOI: 10.1109/ICMTS.1993.292919 HOVER FOR ABSTRACT | PDF Xplore | |
| VLSI device parameters extraction for radiation hardness modeling with SPICE K. O. Petrosjanc, I. A. Kharitonov Moscow Institute of Electronic Machine Building, Moscow, Russia DOI: 10.1109/ICMTS.1993.292901 HOVER FOR ABSTRACT | PDF Xplore | |
| An approach for relating model parameter variabilities to process fluctuations J. A. Power, A. Mathewson, W. A. Lane National Microelectronics Research Centre, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.1993.292892 HOVER FOR ABSTRACT | PDF Xplore | |
| The use of test masks in the analysis of device yields S. J. Rhodes, G. C. Day GEC Plessey Semiconductors Limited, Plymouth, UK DOI: 10.1109/ICMTS.1993.292920 HOVER FOR ABSTRACT | PDF Xplore | |
| High-voltage termination-structure design using a test chip and two-dimensional simulation R. D. Schrimpf, S. I. Kosier, B. Salik, K. F. Galloway, C. F. Wheatley1, D. J. Burton2 Electrical and Computer Engineering Department, University of Arizona Tucson, Tucson, AZ, USA 1Consultant, Drums, PA, USA 2Harris Semiconductor Company, Mountaintop, PA, USA DOI: 10.1109/ICMTS.1993.292896 HOVER FOR ABSTRACT | PDF Xplore | |
| Prediction of dark currents in actual devices using new test structure K. Shibusawa, N. Murakami, T. Mori, T. Ajioka LSI Process Technology Center, OKI Electric Industry Company Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.1993.292925 HOVER FOR ABSTRACT | PDF Xplore | |
| Projecting oxide lifetime by a step voltage method using electric field correction (MOS VLSI) T. Shigenobu, H. Uchida, N. Hirashita VLSI Research and Development Center, Oki Electric Industry Company Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.1993.292882 HOVER FOR ABSTRACT | PDF Xplore | |
| An investigation into the nonquasistatic effects in MOS devices with on-wafer S-parameter techniques R. Singh, A. Juge1, R. Joly, G. Mortin1 Central R&D, Device Modeling, SGS-Thomson Microelectronics, Grenoble, France 1SGS-Thomson Microelectron., Grenoble, France DOI: 10.1109/ICMTS.1993.292899 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluating the graft base lateral diffusion depth of high-performance bipolar transistors by using test structures Y. Tamaki, T. Shiba, T. Kure, T. Nakamura Central Research Laboratory, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1993.292894 HOVER FOR ABSTRACT | PDF Xplore | |
| Metrology standards for advanced semiconductor lithography referenced to atomic spacings and geometry E. C. Teague, L. W. Linholm, M. W. Cresswell, W. B. Penzes, J. A. Kramar, F. E. Scire, J. S. Villarrubia1, J. S. Jun Precision Engineering Division and Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1993.292918 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation technique of gate oxide damage Y. Uraoka, K. Eriguchi, T. Tamaki, K. Tsuji Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1993.292878 HOVER FOR ABSTRACT | PDF Xplore | |
| Latch-up test structures for reliability analysis of a floating well based smart power technology M. Puig Vidal, M. Bafleur1, J. Buxo1, G. Sarrabayrouse1 Diagonal 645-647, Universitat de Barcelona, Barcelona, Spain 1Laboratoire d''Automatique et d''Analyse des Systemes du C.N.R.S, Toulouse, France DOI: 10.1109/ICMTS.1993.292885 HOVER FOR ABSTRACT | PDF Xplore | |
| Enhanced gate-controlled-diode current (EGCDC) measurement C. R. Viswanathan, J. . -T. Hsu, P. Aum1, D. Chan1 Electrical Engineering Department, University of California, Los Angeles, CA, USA 1SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1993.292895 HOVER FOR ABSTRACT | PDF Xplore | |
| Design considerations for a test structure which can be used to determine the optimum focus A. J. Walton, M. Fallon, J. T. M. Stevenson, A. W. S. Ross Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1993.292907 HOVER FOR ABSTRACT | PDF Xplore | |
| Generic test chip formats for ASIC-oriented semiconductor process development C. Weber Silicon Process Laboratory (SPL), Hewlett-Packard Corporation, Palo Alto, CA, USA DOI: 10.1109/ICMTS.1993.292911 HOVER FOR ABSTRACT | PDF Xplore |
