IEEE International Conference on Microelectronic Test Structures
ICMTS 1992 Program
By First Author
 | Voltage-dividing potentiometer enhancements for high-precision feature placement metrology R. A. Allen, M. W. Cresswell, C. H. Ellenwood, L. W. Linholm National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1992.185964 HOVER FOR ABSTRACT | PDF Xplore |
| A new latch-up test structure for practical design methodology for internal circuits in the standard cell-based CMOS/BiCMOS LSIs T. Aoki NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1992.185927 HOVER FOR ABSTRACT | PDF Xplore | |
| A modular 0.7 μm CMOS JESSI test chip for multi purpose applications T. Brenner, N. Maene1, S. Lindenkreuz2, J. le Ber3, H. Richter4, E. Janssens5, G. Morin6, J. Hanseler7 Alcatel Sel Research Center, Stuttgart, Germany 1Alcatel Bell, Belgium 2Robert Bosch GmbH, Germany 3Bull S.A., France 4NA 5Mietec, Belgium 6SGS-Thomson, France 7Siemens AG, Germany DOI: 10.1109/ICMTS.1992.185960 HOVER FOR ABSTRACT | PDF Xplore | |
| CMOS-ASIC life-predictions from test-coupon data M. G. Buehler, N. Zamani, J. A. Zoutendyk Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1992.185925 HOVER FOR ABSTRACT | PDF Xplore | |
| Automatic test chip and test program generation: an approach to parametric test computer-aided design T. Ternisien d'Ouville, J. P. Jeanne, J. L. Leclercq, D. Caloud1, L. Zangara1 France Télécom CNET, Meylan, France 1Dolphin Integration, Meylan, France DOI: 10.1109/ICMTS.1992.185957 HOVER FOR ABSTRACT | PDF Xplore | |
| Finite element analysis of a SWEAT structure with a 3-D, nonlinear, coupled thermal-electric model M. J. Dion Sematech Inc., Austin, TX, USA DOI: 10.1109/ICMTS.1992.185926 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel test structure for monitoring technological mismatches in DRAM processes H. Geib, W. Weber, E. Wohlrab, L. Risch Munich, Germany DOI: 10.1109/ICMTS.1992.185929 HOVER FOR ABSTRACT | PDF Xplore | |
| A note on designing a comprehensive scanning electron microscopy test structure (for VLSI) K. Golshan, M. Harward, H. Tigelaar Regional Technology Center and Semiconductor Process and Design Center, Texas Instruments, Inc., Irvine, CA, USA DOI: 10.1109/ICMTS.1992.185962 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures for ISFET chemical sensors I. Gracia, C. Cane, M. Lozano, J. Esteve Centre Nacional de Microelectrònica, Universitat Autònoma Barcelona, Bellaterra, Spain DOI: 10.1109/ICMTS.1992.185959 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures and measurement techniques for the characterization of the dynamic behaviour of CMOS transistors on wafer in the GHz range J. Hanseler, H. Schinagel, H. L. Zapf Semiconductor Group, CAD Department, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1992.185944 HOVER FOR ABSTRACT | PDF Xplore | |
| Critical dimension measurements by electron and optical beams for the establishment of linewidth standards T. Hatsuzawa, K. Toyoda National Research Laboratory of Metrology, M.I.T.I., Tsukuba, Japan DOI: 10.1109/ICMTS.1992.185965 HOVER FOR ABSTRACT | PDF Xplore | |
| An optical measurement method for PN junction depth Yie He, Yafa Shen1 Microelectronics Center, South-East University, Nanjing, China 1Microelectron. Center, Southeast Univ., Nanjing, China DOI: 10.1109/ICMTS.1992.185961 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for the detection, localization and identification of short circuits with a high speed digital tester C. Hess, L. H. Weiland Institut für Rechnerentwurf und Fehlertoleranz, Universitat di Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1992.185956 HOVER FOR ABSTRACT | PDF Xplore | |
| Carrier transport test structure for characterization of poly/monosilicon interfaces B. Hu, N. H. Berger, A. Gauckler, B. Muller Institute of Microelectronics, Technical University Berlin, Berlin, Germany DOI: 10.1109/ICMTS.1992.185952 HOVER FOR ABSTRACT | PDF Xplore | |
| Inverse modeling for doping profile extraction in the presence of interface traps K. Iniewski Department of Electrical Engineering, University of Toronto, Toronto, ONT, Canada DOI: 10.1109/ICMTS.1992.185940 HOVER FOR ABSTRACT | PDF Xplore | |
| An analytical strategy for fast extraction of MOS transistor DC parameters applied to the SPICE M)53 and BSIM models P. R. Karlsson, K. O. Jeppson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1992.185942 HOVER FOR ABSTRACT | PDF Xplore | |
| A high-speed TEG evaluation system integrating parallel/continuous processing software and high-speed hardware K. Kubota, T. Takeda, T. Sakurai NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1992.185958 HOVER FOR ABSTRACT | PDF Xplore | |
| Accurate determination of CMOS capacitance parameters using multilayer structures W. de Lange Advanced Processor Division, Palo Alto, CA, USA DOI: 10.1109/ICMTS.1992.185938 HOVER FOR ABSTRACT | PDF Xplore | |
| A new method and test structure for easy determination of femto-farad on-chip capacitances in a MOS process B. Laquai, H. Richter, B. Hofflinger Institute for Microelectronics, Stuttgart, Stuttgart, Germany DOI: 10.1109/ICMTS.1992.185939 HOVER FOR ABSTRACT | PDF Xplore | |
| Extracting contact misalignment from 4- and 6-terminal contact resistors U. Lieneweg, H. R. Sayah Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1992.185967 HOVER FOR ABSTRACT | PDF Xplore | |
| Yield test structures and their use for process development S. Magdo General Technology Division, IBM, Corporation, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.1992.185935 HOVER FOR ABSTRACT | PDF Xplore | |
| A simple method to measure very low currents to evaluate the effect of damage caused by contact formation near the isolation edges in high-density LSIs J. Matsuda, Y. Oba Semiconductor Business Headquarters Research and Development Center, Sanyo Electric Company Limited, Ora-gun, Gunma, Japan DOI: 10.1109/ICMTS.1992.185930 HOVER FOR ABSTRACT | PDF Xplore | |
| Issues with contact defect test structures M. A. Mitchell, J. Huang, L. Forner1 Solid State Electronics Center, Honeywell, Inc., Plymouth, MN, USA 1Honeywell Inc., Plymouth, MN, USA DOI: 10.1109/ICMTS.1992.185936 HOVER FOR ABSTRACT | PDF Xplore | |
| Effective channel length determination using punchthrough voltage S. Nakanishi, M. Hoijer, Y. Saitoh, Y. Katoh, Y. Kojima, M. Kamiya IC Device 1G Semiconductor division, Seiko Instruments, Inc., Matsudo, Chiba, Japan DOI: 10.1109/ICMTS.1992.185941 HOVER FOR ABSTRACT | PDF Xplore | |
| Three-dimensional effects of latchup turn-on CMOS and forward-biased n+-diode measured by photoemission T. Ohzone, H. Iwata Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.1992.185951 HOVER FOR ABSTRACT | PDF Xplore | |
| Two-dimensional current/voltage measurements of reverse-biased n+-diodes by photoemission T. Ohzone, H. Iwata Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.1992.185931 HOVER FOR ABSTRACT | PDF Xplore | |
| A new and simple test structure for evaluating the sectional photo-sensitivity distribution of pixels in a frame-transfer CCD image sensor M. Okigawa Semiconductor Business Headquarters LSI Division, Sanyo Electric Company Limited, Gifu, Japan DOI: 10.1109/ICMTS.1992.185955 HOVER FOR ABSTRACT | PDF Xplore | |
| Dependence of SPICE Level 3 model parameters with transistor size C. Perello, M. Lozano, C. Cane, E. LoraTamayo1 Centre Nacional de Microelectrónica, Universitat Autònoma Barcelona, Barcelona, Spain 1Centre Nacional de Microelectron., Univ. Au,tonoma de Barcelona, Spain DOI: 10.1109/ICMTS.1992.185943 HOVER FOR ABSTRACT | PDF Xplore | |
| An investigation of MOSFET statistical and temperature effects J. A. Power, R. Clancy, W. A. Wall, A. Mathewson, W. A. Lane National Microelectronics Research Centre, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.1992.185970 HOVER FOR ABSTRACT | PDF Xplore | |
| A study of clustering using microelectronic defect monitors A. V. S. Satya East Fishkill Facility, IBM, Corporation, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.1992.185934 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure and experimental analysis of bipolar hot-carrier degradation including stress field effect H. Shimamoto, M. Tanabe, T. Onai1, K. Washio1, T. Nakamura1 Musashino Office, Hitachi Device Engineering Company Limited, Kokubunji, Tokyo, Japan 1Central Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan DOI: 10.1109/ICMTS.1992.185949 HOVER FOR ABSTRACT | PDF Xplore | |
| The design, fabrication and measurement of asymmetrical LDD transistors R. C. Smith, A. J. Walton Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1992.185948 HOVER FOR ABSTRACT | PDF Xplore | |
| Suppression of measurement errors in effective-MOSFET-channel-length extraction K. Terada Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Japan DOI: 10.1109/ICMTS.1992.185971 HOVER FOR ABSTRACT | PDF Xplore | |
| Life time evaluation of MOSFET in ULSIs using photon emission method N. Tsutsu, Y. Uraoka, T. Morii, K. Tsuji Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1992.185946 HOVER FOR ABSTRACT | PDF Xplore | |
| | New failure analysis technique of ULSIs using photon emission method Y. Uraoka, T. Maeda, I. Miyanaga, K. Tsuji Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1992.185947 HOVER FOR ABSTRACT | PDF Xplore |
| Test structures for analysis and parameter extraction of secondary photon-induced leakage currents in CMOS DRAM technology S. H. Voldman IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1992.185932 HOVER FOR ABSTRACT | PDF Xplore | |
| The use of a digital multiplexer to reduce process control chip pad count D. Ward, A. J. Walton1, W. G. Gammie1, R. J. Holwill1 Philips Semiconductors, Southampton, UK 1Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1992.185954 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement and parameter extraction of submicron VLSI MOSFET test structures C. S. Wen, M. Guldahl, L. P. Sadwick, R. Kent1, H. Gaffur2 Department of Electrical Engineering, University of Utah, Salt Lake, UT, USA 1Intel Corporation, Albuquerque, NM, USA 2National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1992.185969 HOVER FOR ABSTRACT | PDF Xplore | |
| VLSI interconnect linewidth variation: a method to characterize depth of focus and proximity effects P. J. Wright, E. Burke, A. T. Appel Semiconductor Process and Design Center, Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.1992.185966 HOVER FOR ABSTRACT | PDF Xplore | |
| A new method for electrically measuring thin-film thickness of SOI MOSFETs H. Yamazaki, S. Ando, H. Horie, S. Hijiya Fujitsu Laboratories Limited, Atsugi, Japan DOI: 10.1109/ICMTS.1992.185953 HOVER FOR ABSTRACT | PDF Xplore | |
| Capacitor insulator reliability prediction using three-dimensional test chips for submicron DRAMS J. Yugami, T. Mine, S. Iijima, A. Hiraiwa Central Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan DOI: 10.1109/ICMTS.1992.185924 HOVER FOR ABSTRACT | PDF Xplore |
