IEEE International Conference on Microelectronic Test Structures
ICMTS 1990 Program
By First Author
| Measurement of lateral diffusion on technologies with polysilicon doping source with misalignment correction J. Anguita, C. Perello, M. Lozano, C. Cane, E. Lora-Tamayo Centro Nacional de Microelectrónica, Universidad Autónoma de Barcelona, Barcelona, Spain DOI: 10.1109/ICMTS.1990.161735 HOVER FOR ABSTRACT | PDF Xplore | |
| Gate oxide thickness measurement using Fowler-Nordheim tunneling R. A. Ashton AT and T Bell Laboratories, Inc., Allentown, PA, USA DOI: 10.1109/ICMTS.1990.161713 HOVER FOR ABSTRACT | PDF Xplore | |
| The spidermask: a new approach for yield monitoring using product adaptable test structures S. Beckers, C. Hiltrop Mietec NV, Oudenaarde, Belgium DOI: 10.1109/ICMTS.1990.67881 HOVER FOR ABSTRACT | PDF Xplore | |
| Test SRAMs for characterizing alpha particle tracks in CMOS/bulk memories M. G. Buehler, B. R. Blaes, G. A. Soli Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1990.161723 HOVER FOR ABSTRACT | PDF Xplore | |
| A new test structure to characterize the latchup effect C. Cane, M. Lozano, E. Cabruja, E. Lora-Tamayo, F. Serra-Mestres Centre Nacional de Microelectrònica, Campus de Bellaterra, Barcelona, Spain DOI: 10.1109/ICMTS.1990.67878 HOVER FOR ABSTRACT | PDF Xplore | |
| Accelerated current test for fast tunnel oxide evaluation (of EPROMs) P. Cappelletti, P. Ghezzi, F. Pio, C. Riva Central Research and Development, SGS-Thomson Microelectronics, Milan, Italy DOI: 10.1109/ICMTS.1990.161717 HOVER FOR ABSTRACT | PDF Xplore | |
| Latch-up characterization in standard and twin-tub test structures by electrical measurements, 2-D simulations and IR microscopy T. Cavioni, M. Cecchetti1, M. Muschitiello2, G. Spiazzi3, I. Vottre3, E. Zanoni3 SGS Thomson, SGS Thomson Research and Development, Milano, Italy 1SGS Thomson Research and Development, Milano, Italy 2Tecnopolis CSATA, Microelectronics Center, Bari, Italy 3Dipartimento di Elettronica e Informatica, Universita di Padova, Padova, Italy DOI: 10.1109/ICMTS.1990.67877 HOVER FOR ABSTRACT | PDF Xplore | |
| Photoemission identification of emitter resistance for CMOS latch-up hysteresis Ming-Jer Chen, Jeng-Kuo Jeng1, Ping-Nan Tseng2, Nun-Sian Tsai2, Ching-Yuan Wu Institute of Electronics, National Chiao Tung University, Taipei, Taiwan 1Industrial Technology Research Institute (ITRI), Taipei, Taiwan 2Taiwan Semiconductor Manufacturing Company Limited, Taipei, Taiwan DOI: 10.1109/ICMTS.1990.161748 HOVER FOR ABSTRACT | PDF Xplore | |
| A modified sliding wire potentiometer test structure for mapping nanometer-level distances M. W. Cresswell, M. Gaitan, R. A. Allen, L. W. Linholm National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1990.161726 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure data classification using a directed graph approach M. W. Cresswell, D. Khera, L. W. Linholm, C. E. Schuster IC Technology Group, Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1990.67902 HOVER FOR ABSTRACT | PDF Xplore | |
| Analysis of process-induced charges created in MOSFETs and related collection test structures P. Dars, R. Basset, G. Merckel CNS, CNET, Meylan, France DOI: 10.1109/ICMTS.1990.161712 HOVER FOR ABSTRACT | PDF Xplore | |
| Extraction of the interfacial generation velocity in MOSFETs J. Dugas, R. Jerisian, J. Oualid1, D. Labrunye2, J. M. Mirabel3 Laboratolre des Matériaux et Composants Semi-Conducteurs de I'Ecoie Nationale Supérieure de Physique de Marseille, Domine Universitaire de Saint-Jérôme, Marseilles, France 1Laboratoire des Matériaux et Composants Semi-Conducteurs de I'Ecole Nationale Supérieure de Physique de Marseille, Domine Universitaire de Saint-Jérôme, Marseilles, France 2Central Research and Development DAIS, Rousset, France 3Rousset, France DOI: 10.1109/ICMTS.1990.161705 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures to investigate thin insulator dielectric wearout and breakdown D. J. Dumin, N. B. Heilemann, N. Husain Center for Semiconductor Device Reliability Research, Department of Electrical and Computer Engineering, Clemson University, Clemson, SC, USA DOI: 10.1109/ICMTS.1990.161714 HOVER FOR ABSTRACT | PDF Xplore | |
| Examination of LOCOS process parameters and the measurement of effective width M. Fallon, J. M. Robertson, A. J. Walton, R. J. Holwill Edinburgh Micro fabrication Facility Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1990.161731 HOVER FOR ABSTRACT | PDF Xplore | |
| Simple evaluation of very low currents in process characterization P. Girard, P. Nouet, F. M. Roche Laboratoire dE28099Automatique et de Microelectronique de Montpellier (U.R.A. W3710 CNRS), Université de Montpellier II, Montpellier, France DOI: 10.1109/ICMTS.1990.161719 HOVER FOR ABSTRACT | PDF Xplore | |
| Defect size distribution in VLSI chips R. Glang IBM Corp., Manassas, VA, USA DOI: 10.1109/ICMTS.1990.67880 HOVER FOR ABSTRACT | PDF Xplore | |
| Transmission line model test structure with four or more terminals: a novel method to characterize non-ideal planar ohmic contacts in presence of inhomogeneities L. Gutai Philips R&D Center for IC Technology, Sunnyvale, Philips Components-Signetics Company, Sunnyvale, CA, USA DOI: 10.1109/ICMTS.1990.67874 HOVER FOR ABSTRACT | PDF Xplore | |
| Fault chip defect characterization for wafer scale integration D. J. Hannaman, H. R. Sayah, R. A. Allen, M. G. Buehler, M. Yung1 Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA 1Hughes Research Laboratory, Malibu, CA, USA DOI: 10.1109/ICMTS.1990.67882 HOVER FOR ABSTRACT | PDF Xplore | |
| The inverter matrix: a vehicle for assessing process quality through inverter parameter analysis of variance D. J. Hannaman, M. G. Buehler1, J. Chang1, H. R. Sayah1 Silicon Systems, Inc., Tustin, CA, USA 1Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1990.161722 HOVER FOR ABSTRACT | PDF Xplore | |
| A measurement technique for analyzing bitline mode soft errors in half-micron design DRAMs N. Higaki, S. Ando, M. Taguchi Fujitsu Laboratories Limited, Atsugi, Japan DOI: 10.1109/ICMTS.1990.67900 HOVER FOR ABSTRACT | PDF Xplore | |
| A new extraction method for effective channel length on lightly doped drain MOSFET's J. Ida, A. Kita, F. Ichikawa VLSI R&D Center, OKI Electric Industry Company Limited, Hachioji, Japan DOI: 10.1109/ICMTS.1990.67890 HOVER FOR ABSTRACT | PDF Xplore | |
| The vertical test structure for measuring contact resistance between two kinds of metal S. Ido, M. Imai, T. Kumise, M. Satoh, H. Horir1, S. Ando2 Fujitsu Laboratories Limited, Atsugi, Kanagawa, Japan 1Fujitsu Labs. Ltd., Atsugi, Japan 2Submicron Development Center, Fujitsu Laboratories Limited, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161708 HOVER FOR ABSTRACT | PDF Xplore | |
| Test chip for the evaluation of surface-diffusion phenomena in sputtered aluminum planarization processes M. A. Jones, J. A. Roberts, C. H. Ellenwood1, M. W. Cresswell1, R. A. Allen1 Semiconductor Equipment Division, Eaton Corporation, Beverly, MA, USA 1National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1990.161709 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for determining boron diffusion coefficient in tungsten silicide Y. Kataoka, K. Suzuki, H. Horie, Y. Yamashita, N. Nakayama, T. Kitakohji Fujitsu Laboratories Limited, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161736 HOVER FOR ABSTRACT | PDF Xplore | |
| Direct extraction of accurate DC bipolar parameters for the forward active region without using optimization J. Kendall Northern Telecom Electronics Limited, Nepean, ONT, Canada DOI: 10.1109/ICMTS.1990.161740 HOVER FOR ABSTRACT | PDF Xplore | |
| Knowledge verification of machine-learning procedures based on test structure measurements D. Khera, L. W. Linholm, R. A. Allen, M. W. Cresswell, V. C. Tyree1, W. Hansford1, C. Pina1 Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1The MOSIS Service, USC Information Sciences Institute, Marina del Rey, CA, USA DOI: 10.1109/ICMTS.1990.161729 HOVER FOR ABSTRACT | PDF Xplore | |
| Using spatial information to analyze correlations between test structure data J. K. Kibarian, A. J. Strojwas Department of Electrical and Computer Engineering, Camegie Mellon University, Pittsburgh, PA, USA DOI: 10.1109/ICMTS.1990.67901 HOVER FOR ABSTRACT | PDF Xplore | |
| Self-multiplexing force-sense test structures for (MOS) IC applications K. L. M. van der Klauw, J. J. M. Joosten, L. A. Wall1 Device and Process Characterization Group, Philips Research Laboratories, Eindhoven, Netherlands 1National Microelectronics Research Centre, University College, Cork, Ireland DOI: 10.1109/ICMTS.1990.67884 HOVER FOR ABSTRACT | PDF Xplore | |
| A hot carrier parallel testing technique to give a reliable extrapolation N. Koike, M. Ito1, H. Kuriyama2 Kyoto Research Laboratory, Matsushita Electronics Corporation, Kyoto, Japan 1Memory Division, Matsushita Electronics Corporation, Kyoto, Japan 2Kyoto Research Laboratory and Memory Division, Matsushita Electronics Corporation, Kyoto, Japan DOI: 10.1109/ICMTS.1990.161749 HOVER FOR ABSTRACT | PDF Xplore | |
| Novel test structure to study junction leakage current N. Koike, K. Tominaga Kyoto Research Laboratory Yatsushita Electronics Corporation, Japan DOI: 10.1109/ICMTS.1990.67905 HOVER FOR ABSTRACT | PDF Xplore | |
| A fast testing of electromigration immunity using noise measurement technique J. Komori, Y. Takata, J. Mitsuhashi, N. Tsubouchi LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1990.161753 HOVER FOR ABSTRACT | PDF Xplore | |
 | On-chip quasi-static floating-gate capacitance measurement method C. Kortekaas Device and Process Characterization Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1990.67889 HOVER FOR ABSTRACT | PDF Xplore |
| Semiconductor device parameter extraction based on reconfigurable ring oscillator frequency measurements F. Kovacs, G. Hosszu Department of Electronic Devices, Technical University of budapest, Budapest, Hungary DOI: 10.1109/ICMTS.1990.161745 HOVER FOR ABSTRACT | PDF Xplore | |
| A practical method for extracting impurity profiles and effective mobilities of MOSFET's with nonuniform channel doping K. Kubota, Y. Kawashima1, Y. Ohkura2, M. Nagao Semiconductor Design & Development Center, Hitachi and Limited, Tokyo, Japan 1Hitachi Microcomputer Engineering Company Limited, Tokyo, Japan 2TtCentral Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan DOI: 10.1109/ICMTS.1990.67872 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement of lateral diffusion profiles for submicrometer MOSFETs K. Kubota, Y. Kawashima, S. Yoshida, M. Ishida Semiconductor Design & Development Center, Hitachi and Limited, Kodaira, Tokyo, Japan DOI: 10.1109/ICMTS.1990.161734 HOVER FOR ABSTRACT | PDF Xplore | |
| Novel measurement technique for trapped charge centroid in gate insulator (of DRAM) J. Kumagai, S. Sawada, K. Toita Semiconductor Device Engineering Laboratory, Toshiba Corporation, Kawasaki, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161718 HOVER FOR ABSTRACT | PDF Xplore | |
| X-ray exposure mask accuracy evaluation using electrical test structures Y. Kuroki, S. Hasegawa, T. Honda, Y. Iida Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161725 HOVER FOR ABSTRACT | PDF Xplore | |
| Novel test structure for the measurement of electrostatic discharge pulses H. Lendenmann, R. D. Schrimpf, A. D. Bridges1 Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA 1AT&T, Microelectronics, Allentown, PA DOI: 10.1109/ICMTS.1990.67895 HOVER FOR ABSTRACT | PDF Xplore | |
| Flange correction to four-terminal contact resistance measurements U. Lieneweg, D. J. Hannaman Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1990.67875 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for characterization of polycrystalline silicon as a diffusion source for advanced devices B. Lojek, B. Vasquez Advanced Technology Center, Motorola, Inc., Mesa, AZ, USA DOI: 10.1109/ICMTS.1990.67888 HOVER FOR ABSTRACT | PDF Xplore | |
| Improvement of the triangular MOS transistor for misalignment measurement M. Lozano, C. Cane, C. Perello, J. Anguita, E. Lora-Tamayo Centro Nacional de Microelectrónica, Universidad Autónoma de Barcelona, Barcelona, Spain DOI: 10.1109/ICMTS.1990.161724 HOVER FOR ABSTRACT | PDF Xplore | |
| | Investigation of self-heating in VLSI and ULSI MOSFETs P. G. Mautry, J. Trager Semiconductor Group, Technology, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1990.67907 HOVER FOR ABSTRACT | PDF Xplore |
| A new bipolar extraction tool for wide range of device behaviours E. Mazaleyrat, D. Celi, A. Juge, B. Cialdella Central Research and Development, SGS-Thomson Microelectronics, Grenoble, France DOI: 10.1109/ICMTS.1990.161741 HOVER FOR ABSTRACT | PDF Xplore | |
| A new set of electrical test structures for simultaneous single-wafer monitoring of ion implant shadowing, channeling, and dose uniformity A. M. McCarthy, W. Lukaszek Center for Integrated Systems, University of Stanford, Stanford, CA, USA DOI: 10.1109/ICMTS.1990.161733 HOVER FOR ABSTRACT | PDF Xplore | |
| A technique for characterizing AC performance with a DC parametric tester R. Merrill, E. Issaq, E. Gomersall1 National Semiconductor Fairchild Research Center, Santa Clara, CA, USA 1Nat. Semicond. Fairchild Res. Center, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1990.67908 HOVER FOR ABSTRACT | PDF Xplore | |
| A crossbridge for measurement of gate-limited source/drain diffusion M. A. Mitchell, C. Figura, L. Forner Solid State Electronics Center, Honeywell, Inc., Plymouth, MN, USA DOI: 10.1109/ICMTS.1990.67886 HOVER FOR ABSTRACT | PDF Xplore | |
| Novel test structures for the characterization of latch-up tolerance in a bipolar and MOSFET merged device H. Momose, T. Maeda, K. Inoue1, Y. Urakawa, K. Maeguchi Semiconductor Device Engineering Laboratory, Toshiba Corporation, Japan 1Semiconductor Division, Toshiba Corporation, Kawasaki, Japan DOI: 10.1109/ICMTS.1990.161747 HOVER FOR ABSTRACT | PDF Xplore | |
| A new structure for measuring the thermal conductivity of integrated circuit dielectrics J. H. Orchard-Webb Mitel Semiconductor Limited, Kanata, ONT, Canada DOI: 10.1109/ICMTS.1990.161710 HOVER FOR ABSTRACT | PDF Xplore | |
| Electrical characterization of 2-D doping profiles G. J. L. Ouwerling, J. C. Staalenburg1, M. Kleefstra1 Philips Research Laboratories, Eindhoven, Netherlands 1Electrical Materials Laboratory, Delft University of Technnology, Delft, Netherlands DOI: 10.1109/ICMTS.1990.67871 HOVER FOR ABSTRACT | PDF Xplore | |
| Array diagnostic monitor-a DRAM technology development vehicle M. Paggi, E. Sprogis, G. Richard, R. E. Newhart IBM General Technology Division, IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1990.67897 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement of minority carrier transport parameters in heavily doped shallow implanted layers Y. Pan, M. Kleefstra Department of Electrical Engineering, Electrical Materials Laboratory, Delft University of Technnology, Delft, Netherlands DOI: 10.1109/ICMTS.1990.67873 HOVER FOR ABSTRACT | PDF Xplore | |
| Yield modeling from SRAM failure analysis H. G. Parks General Electric Company, Corporate Research and Development, Schenectady, NY, USA DOI: 10.1109/ICMTS.1990.67898 HOVER FOR ABSTRACT | PDF Xplore | |
| Full and automated determination of MOS transistor parameters in the linear region J. L. Pelloie Letyirdi-Commissariat A L'energie Atomique Cenlg-85x, Letyirdi-Commissariat A L'energie Atomique Cenlg-85x, Grenoble, France DOI: 10.1109/ICMTS.1990.67891 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structures and finite element models for chip stress and plastic package reliability R. Pendse, J. Demmin National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1990.67896 HOVER FOR ABSTRACT | PDF Xplore | |
| Enhanced SPICE MOSFET model for analog applications including parameter extraction schemes J. A. Power, W. A. Lane National Microelectronics Research Center, Cork, Ireland DOI: 10.1109/ICMTS.1990.67892 HOVER FOR ABSTRACT | PDF Xplore | |
| MOSFET statistical parameter extraction using multivariate statistics J. A. Power, A. Mathewson, W. A. Lane National Microelectronics Research Centre, Cork, Ireland DOI: 10.1109/ICMTS.1990.161743 HOVER FOR ABSTRACT | PDF Xplore | |
| Novel test structures for the investigation of the efficiency of guard rings used for I/O-latch-up prevention J. Quincke HL CAD 33, Siemens AG, Munchen, Germany DOI: 10.1109/ICMTS.1990.67876 HOVER FOR ABSTRACT | PDF Xplore | |
| Reliability of latchup characterization procedures W. Reczek, F. Bonner, B. Murphy Components Group, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1990.67879 HOVER FOR ABSTRACT | PDF Xplore | |
| A wafer scale fail bit analysis system for VLSI memory yield improvement Y. Sakai, J. Sawada, W. Sakamoto, J. Murato1, H. Kawamoto, K. Sakai2, K. Nakamuta3 Device Development Center, Hitachi and Limited, Ome, Tokyo, Japan 1Hitachi Ltd., Tokyo, Japan 2Hitachi VLSI Engineering Corporation Limited, Tokyo, Japan 3NA DOI: 10.1109/ICMTS.1990.67899 HOVER FOR ABSTRACT | PDF Xplore | |
| Yield measurement tests sites A. V. S. Satya East Fishkill Facility, IBM, Corporation, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.1990.161728 HOVER FOR ABSTRACT | PDF Xplore | |
| Linewidth and step resistance distribution measurements using an addressable array H. Sayah, M. Buehler Jet Propulsion Laboratory, MS 3-329, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1990.67885 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel circular structure for the extraction of the contact resistivity-application to the Pd2Si/n+Si, TiN/Ti/n+Si and TiN/Ti/p+Si interfaces A. Scorzoni, M. Vanzi1, C. Caprile2 CNR Istituto LAMEL, Bologna, Italy 1TELETTRA S.P.A, Bologna, Italy 2STMicroelectronics, Agrate-Brianza, Italy DOI: 10.1109/ICMTS.1990.67909 HOVER FOR ABSTRACT | PDF Xplore | |
| Gate chain structures with on-chip clock generators for realistic high-speed dynamic stress N. Shiono, T. Mizusawa NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161755 HOVER FOR ABSTRACT | PDF Xplore | |
| A technique for measuring threshold mismatch in DRAM sense amplifier devices E. J. Sprogis IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1990.161721 HOVER FOR ABSTRACT | PDF Xplore | |
| Reducing fabrication variability in analog IC technology by the statistical error propagation method using simple test structures S. L. Sundaram, A. C. Carlson1 Motorola Inc., Mesa, AZ, USA 1Analog Integrated Circuits Division, Motorola, Inc., Mesa, AZ, USA DOI: 10.1109/ICMTS.1990.67903 HOVER FOR ABSTRACT | PDF Xplore | |
| A new effective channel length determination method for LDD MOSFETs K. Takeuchi, N. Kasai, K. Terada ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161744 HOVER FOR ABSTRACT | PDF Xplore | |
| An MOS test device with the gate electrode emphasized for dielectric breakdown Y. Tatewaki, K. Matsuda, K. Tanaka, K. Nishizawa, K. Sakiyama Integrated Circuit (Ic) Group Development Department 2, Sharp Corporation, Nara, Japan DOI: 10.1109/ICMTS.1990.161711 HOVER FOR ABSTRACT | PDF Xplore | |
| Sources of error in electrical measurements of dimensional offset and sheet resistance in the near- and sub-micron region J. Trager Semiconductor Group 1Technology, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1990.67887 HOVER FOR ABSTRACT | PDF Xplore | |
| New detection method of hot-carrier degradation using photon spectrum analysis of weak luminescence on CMOS VLSI N. Tsutsu, Y. Uraoka, Y. Nakata, S. Akiyama, H. Esaki VLSI Technology Research Laboratory, Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1990.67894 HOVER FOR ABSTRACT | PDF Xplore | |
| An ovenless electromigration test system environment using test chips with on-chip heating and computer controlled testing V. C. Tyree USC Information Sciences Institute, Marina del Rey, CA, USA DOI: 10.1109/ICMTS.1990.161751 HOVER FOR ABSTRACT | PDF Xplore | |
| Lateral spread of high energy implanted ions studied by electronic test structures T. Ueda, H. Aoki, Y. Kinoshita, S. Wada, H. Miyatake, J. Kudo, T. Ashida1 VLSI Development Laboratories, Sharp Corporation, Tenri, Nara, Japan 1Sharp Corp., Nara, Japan DOI: 10.1109/ICMTS.1990.161737 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation of gate oxide reliability using luminescence method Y. Uraoka, H. Yoshikawa, N. Tsutsu, S. Akiyama Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1990.161715 HOVER FOR ABSTRACT | PDF Xplore | |
| Material and process learning by noncontact characterization of minority carrier lifetime and surface recombination condition A. Usami Department of Electrical and Computer Engineering, Nagoya Institute of Technology, Nagoya, Japan DOI: 10.1109/ICMTS.1990.161704 HOVER FOR ABSTRACT | PDF Xplore | |
| TLM: a trench leakage monitor for a four megabit DRAM technology S. H. Voldman, C. W. Long IBM General Technology Division, IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1990.67910 HOVER FOR ABSTRACT | PDF Xplore | |
| Trench DRAM structures for the analysis of two- and three-dimensional leakage phenomena S. H. Voldman IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1990.161720 HOVER FOR ABSTRACT | PDF Xplore | |
| Dependence of dielectric time to breakdown distributions on test structure area R. . -P. Vollertsen, W. G. Kleppmann Components Group, Semiconductor Division, Reliability Engineering, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1990.161716 HOVER FOR ABSTRACT | PDF Xplore | |
| Study of electromigration at interconnect vias T. Wada, I. Matsuo1, T. Umemoto2 Semiconductor Group, Matsushita Electronics Corporation, Nagaokakyo, Kyoto, Japan 1Quality Laboratory, Kyoto Research Laboratory, Matsushita Electronics Corporation, Nagaokakyo, Kyoto, Japan 2Matsushita Electron. Corp., Kyoto, Japan DOI: 10.1109/ICMTS.1990.161752 HOVER FOR ABSTRACT | PDF Xplore | |
| A parallel measurement system for the extraction of level 3 SPICE parameters A. A. Walker, P. Touhy, A. J. Walton, J. M. Robertson Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1990.67893 HOVER FOR ABSTRACT | PDF Xplore | |
| The application of AI techniques to the control and interpretation of C-V measurements J. A. Walls, A. J. Walton, J. M. Robertson Department of Electrical Engineering, Edinburgh Microfabrication Facility, Edinburgh, UK DOI: 10.1109/ICMTS.1990.67904 HOVER FOR ABSTRACT | PDF Xplore | |
| A methodology for evaluating the area of contacts to improve the accuracy of contact resistance measurements A. J. Walton, M. Fallon, J. T. M. Stevenson, A. Ross, R. J. Holwill Department of Electrical Engineering, Edinburgh Micro fabrication Facility, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1990.161707 HOVER FOR ABSTRACT | PDF Xplore | |
| A novel approach for reducing the area occupied by contact pads on process control chips A. J. Walton, W. Gammie, D. Morrow, J. T. M. Stevenson, R. J. Holwill Edinburgh Micro fabrication Facility Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1990.67883 HOVER FOR ABSTRACT | PDF Xplore | |
| A new method to determine effective channel widths of MOS transistors for VLSI device design C. . -P. Wan, H. Yang, B. J. Sheu Department of Electrical Engineenng/Electrophysics, University of Southern California, Los Angeles, CA, USA DOI: 10.1109/ICMTS.1990.67906 HOVER FOR ABSTRACT | PDF Xplore | |
| Standardization of test structure design C. Weber Circuit Technology Research and Development (CT Research and Development), Hewlett Packard Company, Palo Alto, CA, USA DOI: 10.1109/ICMTS.1990.161730 HOVER FOR ABSTRACT | PDF Xplore | |
| Progress on model building and statistical analysis methodology of IC characteristics with process He Yie, Yao Jiannan Microelectronics Center, South-East University, Nanjing, Jiangsu, China DOI: 10.1109/ICMTS.1990.161739 HOVER FOR ABSTRACT | PDF Xplore | |
| Fully-automated line-width measurement system and its applications M. Yoshizawa, K. Wada NTT LSI Laboratories, Japan DOI: 10.1109/ICMTS.1990.161727 HOVER FOR ABSTRACT | PDF Xplore | |
| Edge effect prediction in real MOS insulator using test chips J. Yugami, A. Hiraiwa Central Research Laboratory, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1990.161706 HOVER FOR ABSTRACT | PDF Xplore |
