IEEE International Conference on Microelectronic Test Structures
ICMTS 1989 Program
By First Author
| Enhanced MOS parameter extraction and SPICE modelling for mixed analogue and digital circuit simulation B. Ankele, W. Holzl, P. O'Leary Schloss Premstätten, Austria Microsystems International Gmbh, Unterpremstatten, Austria DOI: 10.1109/ICMTS.1989.39285 HOVER FOR ABSTRACT | PDF Xplore | |
| Electrical characterization of minority carrier transport parameters in n-type heavily doped silicon S. Bellone, G. Busatto1, C. M. Ransom2 Electronic Department, University of Naples, Naples, Italy 1CNR, I. R. E. C. E., Naples, Italy 2Thomas J. Watson Research Center, IBM, Corporation, Yorktown Heights, NY, USA DOI: 10.1109/ICMTS.1989.39302 HOVER FOR ABSTRACT | PDF Xplore | |
| Subtleties of SPICE MOSFET parameter extraction P. Bendix Semiconductor Optimization and Simulation, Inc., Redwood, CA, USA DOI: 10.1109/ICMTS.1989.39283 HOVER FOR ABSTRACT | PDF Xplore | |
 | Inverter propagation delay measurements using timing sampler circuits B. R. Blaes, M. G. Buehler Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1989.39314 HOVER FOR ABSTRACT | PDF Xplore |
| Statistical worst-case MOS parameter extraction M. J. B. Bolt, A. Trip, H. J. Verhagen Device and Process Characterisation Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1989.39311 HOVER FOR ABSTRACT | PDF Xplore | |
| Contact electromigration: a method to characterize test structures for reliability parameter estimation C. Caprile, G. Specchiulli1 STMicroelectronics, Agrate-Brianza, Italy 1TELETTRA S.P.A, Vimercate, Italy DOI: 10.1109/ICMTS.1989.39294 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for evaluation of 1/f noise in CMOS technologies Z. Y. Chang, W. Sansen Department Elektrotechniek, ESAT-MICAS, KU Leuvęn, Heverlee, Belgium DOI: 10.1109/ICMTS.1989.39299 HOVER FOR ABSTRACT | PDF Xplore | |
| The INMOS integrated parametric test and analysis system D. Cheung, A. Clark, R. Starr INMOS Limited, Newport, Gwent, UK DOI: 10.1109/ICMTS.1989.39279 HOVER FOR ABSTRACT | PDF Xplore | |
| Off-line photolithographic parameter extraction using electrical test structures C. M. Cork INMOS Limited, Newport, Gwent, UK DOI: 10.1109/ICMTS.1989.39272 HOVER FOR ABSTRACT | PDF Xplore | |
| Drain and bulk symmetry factor: a statistical tool to improve device reliability P. Dars, T. T. d'ouville, G. Merckel, H. Mingam CNS, CNET, Meylan, France DOI: 10.1109/ICMTS.1989.39320 HOVER FOR ABSTRACT | PDF Xplore | |
| An experimental measurement technique of interconnection RC delay for integrated circuits using the step voltage response S. G. dos Santos F., J. W. Swart1 Sao Paulo Univ., Brazil 1FEEC Unicamp, Sao Paulo, Brazil DOI: 10.1109/ICMTS.1989.39315 HOVER FOR ABSTRACT | PDF Xplore | |
| Parameter extraction for a SPICE II VDMOS model J. Fernandez, S. Hidalgo1, F. Berta1, J. Paredes1, J. Rebollo1, J. Millan1, F. Serra-Mestres1 CSIC-UAB, Barcelona, Spain 1Centro Nacional de Microelectrónica, CSIC-UAB, Barcelona, Spain DOI: 10.1109/ICMTS.1989.39277 HOVER FOR ABSTRACT | PDF Xplore | |
| Area-periphery partitioning of currents in self-aligned silicon bipolar transistors J. Fertsch, J. Weng, M. Miura-Mattausch Central Research and Development, Siemens AG, Munchen, Germany DOI: 10.1109/ICMTS.1989.39286 HOVER FOR ABSTRACT | PDF Xplore | |
| The effect of contact geometry on the value of contact resistivity extracted from Kelvin structures K. W. J. Findlay, W. J. C. Alexander, A. J. Walton Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1989.39297 HOVER FOR ABSTRACT | PDF Xplore | |
| Gate dimension characterization using the inversion layer G. Freeman, W. Lukaszek Center of Integrated Systems, University of Stanford, Stanford, CA, USA DOI: 10.1109/ICMTS.1989.39271 HOVER FOR ABSTRACT | PDF Xplore | |
| Analysis of intra-level isolation test structure data by multiple regression facilitate rule identification for diagnostic expert systems C. B. Freidhoff, M. W. Cresswell, L. R. Lowry, K. B. Irani1 Westinghouse Research and Development Center, Pittsburgh, PA, USA 1Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA DOI: 10.1109/ICMTS.1989.39312 HOVER FOR ABSTRACT | PDF Xplore | |
| An expert system for process diagnosis (MOS product testing) A. Hamilton, R. Schofield INMOS Limited, Newport, Gwent, UK DOI: 10.1109/ICMTS.1989.39281 HOVER FOR ABSTRACT | PDF Xplore | |
| Test structure for measurement of conductive film thickness M. H. Hanes, M. W. Cresswell, D. N. Schmidt, R. J. Fiedor Westinghouse Research and Development Center, Pittsburgh, PA, USA DOI: 10.1109/ICMTS.1989.39300 HOVER FOR ABSTRACT | PDF Xplore | |
| MOSFET interface state densities of different technologies F. Hofmann, W. Krautschneider Corporate Research & Development, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1989.39293 HOVER FOR ABSTRACT | PDF Xplore | |
| A floating gate method for MOS transistor gate capacitance and Leff measurements and its implementation in a parametric test R. Kazerounian, A. Singh1, B. Eltan1 Waferscale Integration, Inc., Fremont, CA, USA 1WaferScale Integration Inc., Fremont, CA, USA DOI: 10.1109/ICMTS.1989.39275 HOVER FOR ABSTRACT | PDF Xplore | |
| A neural network approach for classifying test structure results D. Khera, M. E. Zaghoul1, L. W. Linholm, C. L. Wilson Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Nat. Inst. of Standards & Technol., Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1989.39309 HOVER FOR ABSTRACT | PDF Xplore | |
| Novel test structure to study location of breakdown for trench capacitor K. Kishi, T. Yoshida1, T. Watanabe, T. Tanaka, S. Shinozaki Semiconductor Device Engineering Laboratory, Toshiba Corporation, Kawasaki, Japan 1Integrated Circuit Corporation, Toshiba Corporation, Kawasaki, Japan DOI: 10.1109/ICMTS.1989.39317 HOVER FOR ABSTRACT | PDF Xplore | |
| A programmable-load CMOS ring oscillator/inverter chain for propagation-delay measurements K. Lippe, H. Kerkhoff, G. Kloppers, N. Morskieft IC-Technology and Electronics Group, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS.1989.39313 HOVER FOR ABSTRACT | PDF Xplore | |
| Measurement of misalignment using a triangular MOS transistor M. Lozano, C. Cane, E. Cabruja, I. Gracia, E. Lora-Tamayo, F. Serra-Mestres Centro Nacional de Microelectónica, Universided Autónoma de Barcelona, Barcelona, Spain DOI: 10.1109/ICMTS.1989.39298 HOVER FOR ABSTRACT | PDF Xplore | |
| A new wafer surface charge monitor (CHARM) A. M. McCarthy, W. Lukaszek Integrated Circuits Laboratory, University of Stanford, Stanford, CA, USA DOI: 10.1109/ICMTS.1989.39301 HOVER FOR ABSTRACT | PDF Xplore | |
| Standard error in die yield projections from defect test structures M. A. Mitchell, J. Sullwold, C. Figura, L. Forner Solid State Electronics Division, Honeywell, Inc., Plymouth, MN, USA DOI: 10.1109/ICMTS.1989.39307 HOVER FOR ABSTRACT | PDF Xplore | |
| High speed measurement of FET Vth at low Id H. Norimatsu Yokogawa-Hewlett-Packard Company, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.1989.39276 HOVER FOR ABSTRACT | PDF Xplore | |
| A simple test structure for measuring substrate resistivity J. H. Orchard-Webb, R. Cloutier1 Mitel Semicond., Bromont, Que., Canada 1Mitel Semiconductor Limited, Bromont, QUE, Canada DOI: 10.1109/ICMTS.1989.39304 HOVER FOR ABSTRACT | PDF Xplore | |
| Design and implementation of channel mobility measurement modules G. J. L. Ouwerling, J. C. Staalenburg1 Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands 1Philips Components, Business Unit, Nijmegen, Netherlands DOI: 10.1109/ICMTS.1989.39303 HOVER FOR ABSTRACT | PDF Xplore | |
| Full characterization of MOS transistors in CMOS technologies J. L. Pelloie LETI-IRDI-Commissariat à l''Energie Atomique CEN/G-85X, Grenoble, France DOI: 10.1109/ICMTS.1989.39284 HOVER FOR ABSTRACT | PDF Xplore | |
| Automatic parameter extraction system with process failure diagnostics for CMOS process J. Pieczynski, H. Vogt Fraunhofer Institute of Microelectronic Circuits and System, Duisburg, Germany DOI: 10.1109/ICMTS.1989.39310 HOVER FOR ABSTRACT | PDF Xplore | |
| Test masks for micromachining silicon B. Puers, W. Sansen Dept. of Electron., Catholic Univ. of Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1989.39280 HOVER FOR ABSTRACT | PDF Xplore | |
| Critical charge model for transient latch-up in VLSI CMOS circuits W. Reczek, J. Winnerl1, W. Pribyl Components Group, Siemens AG, Munich, Germany 1Corporate Research & Development, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1989.39318 HOVER FOR ABSTRACT | PDF Xplore | |
| An opamp as a tool for testing W. Sansen, F. Op't Eynde, G. Gielen Department Elektrotechniek, ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1989.39316 HOVER FOR ABSTRACT | PDF Xplore | |
| Thermal conductivity measurements of thin-film silicon dioxide H. A. Schafft, J. S. Suehle, P. G. A. Mirel Semiconductor Electronics Division, National Bureau of Standards, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1989.39295 HOVER FOR ABSTRACT | PDF Xplore | |
| A new test structure for in-depth lifetime profiling of thin Si epitaxial layers P. Spirito, S. Bellone, C. M. Ransom1, G. Busatto2, G. Cocorullo2 Electronic Department, University of Naples, Naples, Italy 1IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA 2I. R. E. C. E.-CNR, Naples, Italy DOI: 10.1109/ICMTS.1989.39305 HOVER FOR ABSTRACT | PDF Xplore | |
| An overlay vernier and process bias monitor measured by voltage contrast SEM E. J. Sprogis IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1989.39296 HOVER FOR ABSTRACT | PDF Xplore | |
| Fault simulation for fault-tolerant multi-Mbit RAMs C. H. Stapper Department A23 General Technology Division, IBM, Corporation, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1989.39288 HOVER FOR ABSTRACT | PDF Xplore | |
| Analysis of the determination of the dimensional offset of conducting layers and MOS transistors S. Swaving, K. L. M. van der Klauw, J. J. M. Joosten Device and Process Characterization Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1989.39274 HOVER FOR ABSTRACT | PDF Xplore | |
| Electrostatic discharge test structures for CMOS circuits H. Terletzki, L. Risch Corporate Research and Development, SIEMENS AG, Munich, Germany DOI: 10.1109/ICMTS.1989.39319 HOVER FOR ABSTRACT | PDF Xplore | |
| MOSFET effective dimensions determination for VLSI process evaluation H. P. Tuinhout Device and Process Characterisation Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1989.39282 HOVER FOR ABSTRACT | PDF Xplore | |
| Effects of interface traps and bulk traps in SiO2 on hot-carrier-induced degradation H. Uchida, S. Inomata, T. Ajioka VLSI Research and Development Laboratory, OKI Electric Industry Company Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.1989.39292 HOVER FOR ABSTRACT | PDF Xplore | |
| Evaluation technique of gate oxide reliability with electrical and optical measurements Y. Uraoka, N. Tsutsu, T. Morii, Y. Nakata, H. Esaki Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1989.39289 HOVER FOR ABSTRACT | PDF Xplore | |
| A fast measurement technique for the determination of small signal parameters of the bipolar transistor P. Vandeloo IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.1989.39287 HOVER FOR ABSTRACT | PDF Xplore | |
| Automating and sequencing C-V measurements for process fault diagnosis using a pattern-recognition approach (MOS test structure) J. A. Walls, A. J. Walton, J. M. Robertson, T. M. Crawford1 Edinburgh Microfabrication Facility, Edinburgh, UK 1NA DOI: 10.1109/ICMTS.1989.39308 HOVER FOR ABSTRACT | PDF Xplore | |
| Standardization of CMOS unit process development C. Weber Circuit Technology Research and Development (Research and Development), Hewlett Packard Corporation, Palo Alto, CA, USA DOI: 10.1109/ICMTS.1989.39278 HOVER FOR ABSTRACT | PDF Xplore | |
| CMOS process uniformity evaluation through the characterisation of parasitic transistors D. Wilson, A. J. Walton, J. M. Robertson, R. J. Holwill Edinburgh Microfabrication Facility, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1989.39306 HOVER FOR ABSTRACT | PDF Xplore |
