IEEE International Conference on Microelectronic Test Structures

ICMTS 2025 Tutorials

08:00		Registration Desk Opens
09:00		Tutorials Welcome Kejun Xia (Tutorials Chair) TSMC
09:10	T1	Test Structure Design and Test Brad Smith Retired+Natcast Contractor This talk will cover the basics of test structure design and test, emphasizing how they interact. Often, there are no 'right' answers in test structure design, only trade-offs. Methods for how to make those decisions will be covered. Will discuss basic devices (resistors, caps, FETs) and simple circuits (ring oscillators, CBCM, arrays).
10:00		Break
10:30	T2	Parasitic PNPs and NPNs in ESD and latchup over different time domains Slavica Malobabic Cirrus Logic
11:20		Break
11:30	T3	Novel Nanoelectronics for Emerging Memory Technology Sourav Dutta University of Texas at Dallas
12:20		Break
13:40	T4	Atomically-thin Resistive Switching Materials, Devices, and Application Deji Akinwande University of Texas at Austin Atomically-thin resistive switching materials are reshaping the landscape of electronic devices, merging quantum-scale phenomena with advanced engineering applications. This tutorial presentation delves into the unique properties of 2D materials, such as graphene and transition metal dichalcogenides, which exhibit unparalleled scalability, high-energy efficiency, and defect-driven mechanisms pivotal for resistive switching. These materials, with their ultrathin architecture, enable advances in neuromorphic computing, offering high-density, low-energy memory systems and non-volatile RF switches operable up to 500 GHz. Key highlights include advancements in monolayer memory (atomristors), where atomic vacancies and metal diffusion drive enhanced switching behaviors, enabling applications in zero-power devices and next-generation data storage. Testing and characterization of the resistive switching devices will be elucidated including advanced material studies and device performance.
14:30		Break
14:40	T5	Cryogenic Device Physics, Characterization and Modeling with Application to Electronics Development Guofu Niu Auburn University Cryogenic electronics are essential for quantum computing, high-performance data center computing, and space exploration applications. This tutorial examines fundamental physical changes at low temperatures affecting carrier concentration, mobility, saturation velocity, impact ionization, and band-tail states occupation, with emphasis on their effects on SiGe heterojunction bipolar and CMOS transistors, including LDMOS devices. We address compact modeling extensions to account for these phenomena, focusing on carrier freezeout effects and the challenges of device characterization, including test structure design for probe deformation compensation. The tutorial concludes with an example of cryogenic process design kit development and practical circuit design for operation across a 4 K to 400 K temperature range, along with associated testing methodologies.
15:30		Break
16:00	T6	Device test structures and tests focusing on layout-dependent effects (LDE) and multiphysics Chuan Xu Analog Devices Devices on integrated circuits suffer shift in characteristicsunder different layout proximity, due to mechanical stress, doping concentration, optical proximity correction (OPC), etc.Shift in device characteristics may also be measured through applying mechanical stress directly. Device characteristics may also be shifted due to self-heating and/or heating from other nearby devices. This tutorial covers the device test structures and tests focusing on layout-dependent effects (LDE) and how we use multiphysics tools to correlate the physics of device characteristics shift. We first briefly go through the various LDE effects in modern semiconductor devices. Then we illustrate anexample of mechanical simulation on length of diffusion (LOD)effect on maximum linear transconductance (Gmmax). We also illustrate an example of mechanical simulation on Gmmax shift of PMOS in X- versus Y- orientations, due to mechanical stress from test key pads. As for applying direct mechanical stress on devices, we focus on the cantilever test. We illustrate an example of Vbe shift due to cantilever stress in vertical NPN and PNP. Finally, we illustrate devices with built-in temperature sensor to monitor self-heating effect and how it helps us in device modeling. The self-heating effect is also well correlated in thermal simulation.
16:50		Close of Tutorials
17:30		Welcome Reception for All ICMTS Attendees