IEEE International Conference on Microelectronic Test Structures

ICMTS 2025 Program

08:00		Registration Desk Opens
09:00		Opening Remarks C. Young (General Chair), D. Pretti (Technical Program Chair)¹ University of Texas at Dallas, Dallas, TX USA ¹Micron Technology, Inc
Session 1: Applications
09:10	1.1	Power switch improvement for RO array characterization in 18nm FD-SOI technology platform validation C. Cagli STMicroelectronics ABSTRACT: To validate advanced technology, a very large number of standard cells must be characterized. A practical way to achieve this is to use ring oscillators. Arrays of ring oscillators are therefore used to characterize cell’s leakage and dynamic consumption. Ring oscillators are selected thanks to power switches. We present a first switch design pointing out the limitations and showing the need to improve it. We propose an improved version showing that its leakage is largely reduced and the measurement range improved.
09:30	1.2	Comparative study of switching dynamics in Ferroelectric based capacitors with different design options F. Driussi DPIA, Universit`a degli Studi di Udine ABSTRACT: Switching dynamics of ferroelectric based devices not only depend on the ferroelectric (FE) material but also on the design options of the materials stack. Here, we report a comprehensive characterization of Ferroelectric Tunnel Junctions based on Metal-Ferroelectric-Dielectric-Metal (MFDM) stacks and a full benchmark of the extracted parameters with those of simpler Metal-Ferroelectric-Metal capacitors. Extracted remnant polarization is lower in MFDM than in MFM. Furthermore, MFDM devices show an intrinsic dependence of coercive voltages on signal frequency that is not observed in MFM stacks, suggesting that the traps play a fundamental role in device switching.
10:10	1.3	Enhancement of Synaptic Properties using Ta2O5/ZnO/Ta2O5 Tri-layer Device Chae-Min Yeom Chungnam National University ABSTRACT: This paper analyzes the electrical characteristics of Ta₂O₅-based synaptic devices by designing and fabricating a device incorporating a ZnO layer, based on parameters critical for learning in Neural Network based algorithms. A comparative analysis was conducted with single-layer and double-layer-based synaptic devices. The results show that introducing ZnO into the Ta₂O₅-based synaptic device reduced the SET/RESET voltages. Furthermore, the triple-layer device demonstrated improvements in yield, switching behavior uniformity, and conductance change uniformity in response to pulse inputs. These findings indicate that the triple-layer structure offers advantages in consistently forming oxygen vacancy-based conductive filaments (CFs) and allows for more controlled movement of oxygen ions from a structural perspective.
10:30		Break
Session 2: Reliability
11:00	2.1	The Hot Carrier Injection Induced Degradation in MOS Transistors with Subthreshold Hump and the Corelated Impacts on Low Frequence Noise for Low Power Analog Designs Wuxia Li NXP Semiconductors ABSTRACT: In low-power circuit design, transistors are often biased in the subthreshold region, where they may exhibit a hump that significantly increases current levels. This phenomenon is caused by the Shallow Trench Isolation (STI) structure, which is widely used in modern CMOS processes. The steep slope of the silicon sidewall adjacent to the STI structure can lead to the formation of a corner divot, creating an edge device alongside the core device. The edge device has a thinner oxide compared to the core device, making it more susceptible to degradation during stress. This paper presents a comparative study of hot carrier injection (HCI) effects on the degradation of low-voltage MOS transistors with a subthreshold hump in a mature 130nm process. DC performance was measured at the device level before and after HCI stress, along with different baking durations to understand the degradation trends of the parasitic edge device versus the intrinsic one. Additionally, 1/f noise was measured to investigate the underlying mechanisms. Our findings confirm that the edge MOS degrades more rapidly than the intrinsic MOS, offering insights for low-power designs.
11:20	2.2	On-Wafer Characterization of HCI/BTI-induced Threshold Voltage Degradation based Measured Frequency Shift of Ring-Oscillator Circuits Chika Tanaka Kioxia Corporation ABSTRACT: We propose a simple and reliable on-wafer characterization method of transistor threshold voltage degradation due to HCI/BTI using measured Ring-Oscillator frequency shift. Our proposed method enabled to estimate the threshold voltage shift of each transistor in the gate under AC stress as in an actual operation, while eliminating transistor variability.
11:40	2.3	SiC DMOSFET Real Wafer Level HTRB and HTGB Evaluation Ng Hong Seng X-FAB ABSTRACT: Reliability evaluation of SiC devices with conventional packaged-level approach is suffering from certain constraints. This paper presents Wafer-Level HTGB and HTRB results of SiC DMOSFET with in-situ threshold voltage monitoring. The full wafer map data showed 500 sites measured directly on wafer-level with probe pins is capable to detect wafer edge process deviation signature. Abstract
12:00	2.4	Design-Based Care Area Implementation for Electron Beam Inspection (EBI) Buried Defect Signal Enhancement – DRAM Bit-Line Metal Open Po Jen Mo Micron Technology ABSTRACT: This work introduced a design-based care area in electron beam inspection (EBI) for detecting buried defects in DRAM Bit-Lines (BLs). The design-based recipe significantly reduced nuisance defects from Bit-line contacts (BLCs) by approximately 98%. The Cohen's d value of -1.32 indicated improved data discriminability between good and bad dies due to design-based care area implementation.
12:20	2.5	Constant Current Charge-to-Breakdown Characterization in BCD Technology Yu-Hsing Cheng Onsemi ABSTRACT: Charge-to-breakdown (QBD) characterization from constant current density was used to evaluate oxide integrity of two process conditions in a 65 nm BCD technology. In addition, QBD characterization for 30 nm oxide thickness in 0.25 μm BCD process was performed for structures with different areas. This characterization method could be used to evaluate gate dielectric reliability and the impact on gate oxide integrity from different process recipes in technology development and process monitoring.
12:40		Lunch
14:00		Invited Talk 1 Greg Yeric CHIPS National Semiconductor Technology Center Program
15:00		Exhibitor Presentations
15:40		Break
Session 3: Device Characterization
16:10	3.1	An accurate methodology for fast oxide and carrier mobility characterization in simplified transistors with high access resistance Elhadji Alhousseyni Diallo CEA, Leti ABSTRACT: In this work, a new methodology for accurate extraction of the carrier mobility in a simplified FDSOI test device is presented. The method was shown to be effective and it allowed to correct the loss of mobility induced by high access resistance and capacitance in the test devices.
16:30	3.2	D-Mode GaN/AlGaN/GaN MOS-HEMT Test Structures for Evaluating Gate Dielectric Impact on Device Performance A.S. Aguirre-Sanchez The University of Texas at Dallas ABSTRACT: This work presents the development of standardized test structures for evaluating the impact of different gate dielectrics on the performance of D-mode GaN/AlGaN/GaN MOS-HEMTs. HfO₂, Al₂O₃, and SiNx gate dielectrics were deposited using ALD for HfO₂ (7.25 nm) and Al₂O₃ (9.26 nm), and PECVD for SiNx (8.70 nm). Electrical characterization revealed variations in device performance, with threshold voltages of -7.61 V (SiNx), -5.52 V (Al₂O₃), and -4.15 V (HfO₂). Subthreshold swing values were 109 mV/dec (HfO₂), 105 mV/dec (Al₂O₃), and 157 mV/dec (SiNx), while maximum drain currents (ID, max) ranged from 422 mA/mm (SiNx) to 282 mA/mm (HfO₂).These results and methodologies underscore the importance of test structures in exploring the interplay between gate dielectric properties, processing conditions, and device performance, paving the way for future optimization of GaN MOS-HEMT technologies.
16:50	3.3	TACHI: Tests as a Chip Identifier Ryosuke Sada Kyoto University ABSTRACT: This paper presents a method for identifying individual integrated circuits by leveraging pre-shipment test measurements. Criterion vectors based on test result variations achieved 99.32% accuracy in identifying 21,974 chips from wafer test data without requiring dedicated circuitry.
17:10	3.4	Reducing Short-Circuit current of CMOS Inverter circuits with “PN-Body Tied SOI-FET” Kazuki Nakahashi Kanazawa Institute of Technology ABSTRACT: The reduction of the short-circuit current by the steep slope device was confirmed, for the first time, with real TEG measurements, using our newly proposed device of PN-Body Tied SOI-FET. It was also confirmed that the short-circuit current can be very small when the points of steep slope are not overlapped. It is the worthful pre-confirmation because this indicates the possibility of nearly zero short-circuit currents when the steep slope device will be realized.
17:30		End of Day 1

Day 2: Wednesday, Mar 26

08:00		Registration Desk Opens
Session 4: Design & Layout
09:00	4.1	Layout experiments and test structures to characterize Local Layout Effects due to mechanical stress in FinFET transistors Angelo Rossoni PDF Solutions Inc ABSTRACT: The paper demonstrates a comprehensive set of test structures to explore, characterize, and monitor stress-related Local Layout Effects in FinFET transistors. We present the results from 7nm FinFET technology and quantify the impact of stress modulation due to the design style and the neighborhood layout.
09:20	4.2	Estimating Verticality Parameters in Deep Reactive Ion Etching using MEMS Oscillators Shun Yasunaga University of Tokyo ABSTRACT: In view of characterizing a vertical profile of deep reactive ion etching (DRIE) without making a cross section, we propose a method to estimate representative parameters, namely, the underetched cross-section area and the second moment of area. The test structure consists of a series of MEMS oscillators, the resonance frequency of which was plotted for varied spring stiffness and fitted to a physical model derived from geometry. The estimation from oscillation measurement was compared to the actual profile parameters obtained from visual observation, showing correlation R2=0.556 and 0.913 for the area and the second moment of area, respectively.
09:40	4.3	Non-uniformities in MOSFET-array characteristics caused by probe-induced mechanical stress Pablo Saraza-Canflanca IMEC ABSTRACT: We show the detailed distribution of the impact of probe-induced mechanical stress on MOSFET characteristics when the transistors are placed under the contact pads. This effect is already observable with a probe trip overtravel of a few tens of μm, even if the sample has a BEOL of 10 metal layers and ~10 μm.
10:00	4.4	Methodology and Test Structures for Studying ?-Ga2O3 Dielectric and Contact Interfaces A. A. Gruszecki The University of Texas at Dallas ABSTRACT: An outline of versatile device structures and test methodologies is provided to streamline the fabrication and characterization processes of β-Ga2O3 and other novel semiconductor materials for the purpose of investigating gate oxide and metal contact interfaces. β-Ga2O3/Al2O3 MOSCAPs and β-Ga2O3/Ti/Au TLM structures are fabricated for preliminary investigation of dielectric trapping and ohmic contact properties as a function of processing. Precursory I-V and C-V device characterization provides insight into subsequent studies incorporating more advanced physical characterization and device modeling.
10:20		Break
Session 5: RF & Power
10:50	5.1	A new test structure for charge pumping current measurement in vertical Si power device T. Ohguro Toshiba Electronic Devices & Storage Corporation ABSTRACT: We propose a novel test structure for charge pumping current (Icp) measurement to estimate the interface state density at gate insulator/Si substrate in vertical Si power MOSFET. In this structure, the source and base of that are separated by modifying the layout of implantation and trench contact, without requiring additional process steps.
11:10	5.2	A Novel Separated Source Electrodes Kelvin (SSEK) Structure for Extracting Channel Mobility in the 4H-SiC VDMOSFET Wen-Shu Chen Institute of Electronics National Yang Ming Chiao Tung University ABSTRACT: A novel Separated Source Electrodes Kelvin (SSEK) structure that can effectively eliminate most of the series resistance of a VDMOSFET is proposed for extracting channel mobility. We are able to separately measure the resistance of the left and right channels, thereby allowing for a more accurate extraction of the channel mobility.
11:30	5.3	Modified Angelov Model with Improved Accuracy for RF GaN-on-Si HEMTs David Chen Wavetek Microelectronics Corporation (WTK) ABSTRACT: Modified Angelov model of RF GaN-on-Si HEMTs with improved accuracy is proposed. Simulation results of one set of this proposed model parameters are in excellent agreement with the measurement data of DC, S-parameter, and large-signal. Verification with dual-gate RF switch of GaN-on-Si HEMT is provided. Corresponding model/PDK is released for design and manufacturing.
11:50	5.4	Passive and Causal Modeling of 300-GHz-Band IC Capacitors Using Rational Polynomial Approximation Shun Beppu Tokyo University of Science ABSTRACT: This research presents a method to model MOM capacitors for 300-GHz band applications using rational polynomial approximation (RPA). While initial approximations often lead to negative element values due to measurement errors, the model is refined by re-fitting with restrictions to ensure passivity and causality. This approach produces accurate equivalent circuits suitable for high-frequency simulations. The method was validated with measurement with test structure chip fabricated by 0.13 μm SiGe BiCMOS process.
12:00		Lunch
13:20		Invited Talk 2
Session 6: Cryogenic Measurements
14:20	6.1	Oscillation in Cryogenic DC Measurements of High Power LDMOS Devices and Solution Yili Wang Auburn University ABSTRACT: Cryogenic DC measurements of high-power LDMOS devices encounter unique oscillations at low temperatures, disappearing above 200 K. These oscillations are correlated with negative differential resistance (NDR) due to self-heating. We eliminate the oscillation by adding a resistor between the drain and source terminals. This method, combined with DC de-embedding, ensures accurate device characterization across temperatures.
14:40	6.2	Measurement of Subthreshold Current Variability at 1.5 K Using Addressable MOSFET Array Tomoko Mizutani University of Tokyo ABSTRACT: Variability of 65 nm bulk MOSFETs in subthreshold region were measured at 300 K and 1.5 K using addressable transistor arrays. It was confirmed that variability of current onset voltage (COV) significantly increases at 1.5 K. It is shown that the cut-off performance of the FETs at 1.5 K is governed by variability of subthreshold current including COV, rather than steep minimum subthreshold slope.
15:00	6.3	Hysteresis-Induced Neuromorphic Behavior in 180nm Bulk PMOS Devices at 3K Fiheon Imroze James Watt School of Engineering University of Glasgow ABSTRACT: This work investigates the neuromorphic behavior of TSMC 180nm bulk PMOS devices at 3K, focusing on hysteresis and synaptic characteristics. Gated pulsed measurements reveal potentiation and depression behavior, with conductance changes due to pulse amplitude and width variations. These findings contribute to the early stage development of cryogenic neuromorphic quantum computing systems.
15:20		Break
15:50		ICMTS 2025 Presentation Yoshio Mita University of Tokyo ABSTRACT: Presenting the Hosts for ICMTS 2026 in Japan
Session 7: Process Characterization
16:00	7.1	A Test Structure for Analyzing Self-Heating Induced Distortion in On-Chip Current Sensing Resistors Heng Ma Delft University of Technology, Delft ABSTRACT: This paper presents a test structure for a 27mΩ diffusion current sensing resistor to analyze distortion caused by self-heating. A parallel Kelvin connection minimizes parasitic effects from metals and vias. Additionally, a diode array is used to characterize self-heating, providing insights into distortion mechanisms.
16:20	7.2	Novel Test Structures for 3D NAND Array Plasma Damage Monitoring Keerti Kalia Micron Technology ABSTRACT: This study explores the possibility of introducing a new test structure to monitor and signal, plasma damage induced by the memory array process steps. The experimental data shows a clear relationship with the array process, proving the validity of the idea. NHV and NLV devices were used as sense monitors to capture the impact from the plasma damage, presenting a proof of concept to detect changes in electrical characteristics caused by the plasma interactions.
16:40	7.3	Advantage and Challenge of Electrical Critical Dimension Test Structures for Electroplated High Aspect Ratio Nano Structures (HARNS) on Insulating Materials Yoshio Mita University of Tokyo ABSTRACT: Electrical Critical Dimension Test Structures (ECD-TS) have been applied for development of new technology: Metallic High Aspect Ratio Nano Structures (Metal-HARNS). The HARNS refers to electro mechanical structures scaled down to submicron (>260nm confirmed) while keeping its thickness (<1500nm confirmed). Two major advantage and challenge have been confirmed through measurement: (1) insulating material showed critical advantage on ECD over Scanning Electron Microscope CD assessment and (2) seed conductive layer affected the measurement as leakage path.
17:00	7.4	Fabrication of NbO2 based IMT Selector Devices via 300mm Based Memory Test Vehicle K. Beckmann NY CREATES ABSTRACT: Nanoscale NbO2 based Insulator-Metal Transition devices were fabricated on a 300mm memory test vehicle with device sizes as low as 120 nm. Metastable NbO2 was deposited through sputter deposition in an oxygen-controlled environment. Endurance of up to 2.5x107 cycles was achieved with an Roff/Ron ratio above 100 and an extrapolation towards >2000 with further device scaling.
17:20		End of Day 2
18:30		Banquet

Day 3: Thursday, Mar 27

Session 8: Test Optimization
09:00	8.1	Smart Diagnostics for 3D CFET: A Machine Learning Approach to Failure Analysis Jerome Mitard Compute Technology Device Department, IMEC ABSTRACT: This work introduces a novel Convolutional Neural Network for classifying transfer characteristics in emerging Gate-All-Around MOSFET. Trained on vast experimental dataset, the algorithm successfully identifies distinct failure modes across wafers with complex processing variations. The automated analysis enables faster yield enhancement and process optimization for next-generation 3D MOSFET technologies.
09:20	8.2	Automatic PSP MOSFET model card extraction powered by deep learning Alba Ordonez Rodriguez STMicroelectronics ABSTRACT: The semiconductor industry’s need for efficient model card extraction is addressed by a Deep-Learning-powered tool that automates this process for PSP MOSFETs. 59 parameters are predicted with an average 2.06% error, reducing extraction time from weeks to one day, enabling statistical analysis and improving workflow efficiency.
09:40	8.3	Active Sampling of Electrical Characterization Parameters for Efficient Measurement Husnu Murat Kocak Compute Technology Device Department, IMEC ABSTRACT: Time constraints make performing electrical characterization for all fabricated devices nearly impossible. We propose a new machine learning approach to dynamically select a small number key gate voltages and artificially reconstruct a complete Id − Vg curve. As demonstrated on a diverse dataset, our proposed approach offers the potential to significantly reduce the time required for characterization. Specifically, it requires 3 to 7 times fewer measurements per device, thus average time cost is reduced by 62.75% per device while maintaining a threshold voltage error of 19 mV and a subthreshold slope error of 6 mV.
10:00	8.4	Test Accuracy Improvement of Ensemble Gaussian Process-based IC Outlier Detection Using Temporal Similarity among Wafers Daisuke Goeda Kyoto Institute of Technology ABSTRACT: We enhance the test accuracy of an ensemble Gaussian process-based outlier detection by utilizing the advantage of wafers in the same lot having similar characteristics. Evaluation using industrial integrated circuit test data demonstrates that our method improves fault detection rate by 27.9% compared to conventional method.
10:20	8.5	Evaluation of Rapid Vt testing of Wafer-Level MOSFETs. Michael H Herman Advantest Corporation ABSTRACT: We evaluate single Ids spot Vt tests for wafer-level CMOS MOSFETs. We compare results of full Vgs sweep to Rapid Vt method for Vt and channel doping calculations, for both NMOS and PMOS transistors. We discuss reference data requirements vs Vds and Body biases, and W/L sizes with respect to Vt error.
10:40		Break
Session 9: MEMS & Sensors
11:10	9.1	Microheater integration in gate dielectric functionalized IGZO thin film transistors for methanol sensing M. Calderon-Gonzalez Department of Sensors and Actuators (SAT), imec ABSTRACT: We present an IGZO thin-film transistor suitable for methanol sensing, achieved through gate dielectric functionalization. By successfully integrating the device onto a flexible microheater we facilitated zeroing the sensor through gas desorption. More importantly, we enabled thermally induced baseline drift correction, effectively addressing a key issue in FET-based gas sensors.
11:30	9.2	Heterogeneous PEALD Al2O3/TiO2 Nanolaminate Capacitive Energy Storage Devices Z. Mousavi Karimi Department of ECE, Georgia Institute of Technology ABSTRACT: This work combines precise nanofabrication methods with quasi-electrostatic finite element method (FEM) simulations to investigate the parallel component of polarizability along the interfacial planes of multilayer Al2O3/TiO2 nanolaminates. Preliminary electrical measurements from high-density in-plane interdigitated electrode (IDE) structures with Al2O3/TiO2 nanolaminate that are grown using Plasma Enhanced Atomic Layer Deposition (PEALD) and electromagnetic simulations reveal that the average relative permittivity in the vicinity of these heterogeneous interfaces at a frequency of 1 kHz is extracted to be kAl2O3/TiO2 ~ 6615.
11:50	9.3	Planar FDSOI Reconfigurable Schottky Barrier FETs for Gas Sensing Andreas Kramer Integrated Electronic Systems Lab TU Darmstadt ABSTRACT: We present a gas sensitive thin channel planar Schottky barrier FET based on a thin palladium front-gate manufactured using a fully depleted SIMOX SOI with a back-gate. The drain current is sensitive to ambient air and different ammonia concentrations into a vacuum with adjustable sensitivity via the back-gate voltage.
12:10		Best Paper Award, Closing
12:20		Lunch for Excursion Attendees
14:00		Excursion

Session 1: Applications

Session 2: Reliability

Session 3: Device Characterization

Session 4: Design & Layout

Session 5: RF & Power

Session 6: Cryogenic Measurements

Session 7: Process Characterization

Session 8: Test Optimization

Session 9: MEMS & Sensors