08:00 | Registration Desk Opens | ||
Session 4: Design & Layout | |||
09:00 | 4.1 | Layout experiments and test structures to characterize Local Layout Effects due to mechanical stress in FinFET transistors Angelo Rossoni, Tomasz Brozek1, Sharad Saxena2, Rajesh Khamankar2, Christopher Hess1, Jurcy Huang3, Yuchen Teng3, Zsolt Kovacs-Vajna4, Michele Quarantelli PDF Solutions, Inc., Brescia, Italy 1PDF Solutions, Inc., Santa Clara, CA, USA 2PDF Solutions, Inc., Dallas, TX, USA 3PDF Solutions, Inc., Hsinchu, Taiwan 4Dept. of Information Engineering, University of Brescia, Brescia, Italy ABSTRACT: The paper demonstrates a comprehensive set of test structures to explore, characterize, and monitor stress-related Local Layout Effects in FinFET transistors. We present the results from 7nm FinFET technology and quantify the impact of stress modulation due to the design style and the neighborhood layout. | |
09:20 | 4.2 | Estimating Verticality Parameters in Deep Reactive Ion Etching using MEMS Oscillators Shun Yasunaga, Yoshio Mita The University of Tokyo, Tokyo, Japan ABSTRACT: In view of characterizing a vertical profile of deep reactive ion etching (DRIE) without making a cross section, we propose a method to estimate representative parameters, namely, the underetched cross-section area and the second moment of area. The test structure consists of a series of MEMS oscillators, the resonance frequency of which was plotted for varied spring stiffness and fitted to a physical model derived from geometry. The estimation from oscillation measurement was compared to the actual profile parameters obtained from visual observation, showing correlation R2=0.556 and 0.913 for the area and the second moment of area, respectively. | |
09:40 | 4.3 | Non-uniformities in MOSFET-array characteristics caused by probe-induced mechanical stress Pablo Sarazá-Canflanca, Xue Fan1, Simon Van Beek, Erik Bury, Ben Kaczer imec, Leuven, Belgium 1Chengdu Technological University, Sichuan, China ABSTRACT: We show the detailed distribution of the impact of probe-induced mechanical stress on MOSFET characteristics when the transistors are placed under the contact pads. This effect is already observable with a probe trip overtravel of a few tens of μm, even if the sample has a BEOL of 10 metal layers and ~10 μm. | |
10:00 | 4.4 | Methodology and Test Structures for Studying β-Ga2O3 Dielectric and Contact Interfaces A. A. Gruszecki, J. Roy, K. S. Agrawal1, P. La Torraca1, K. Cherkaoui1, P. K. Hurley1, R. M. Wallace, C. D. Young Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX, USA 1Tyndall National Institute, University College Cork, Cork, Ireland ABSTRACT: An outline of versatile device structures and test methodologies is provided to streamline the fabrication and characterization processes of β-Ga2O3 and other novel semiconductor materials for the purpose of investigating gate oxide and metal contact interfaces. β-Ga2O3/Al2O3 MOSCAPs and β-Ga2O3/Ti/Au TLM structures are fabricated for preliminary investigation of dielectric trapping and ohmic contact properties as a function of processing. Precursory I-V and C-V device characterization provides insight into subsequent studies incorporating more advanced physical characterization and device modeling. | |
10:20 | Break | ||
Session 5: RF & Power | |||
10:50 | 5.1 | A new test structure for charge pumping current measurement in vertical Si power device Tatsuya Ohguro, Kohei Oasa, Takuya Yasutake, Takuma Hara, Tatsuya Nishiwaki, Kenya Kobayashi, Hiroaki Kato Advanced Semiconductor Device Development Center, Toshiba Electronic Devices & Storage Corporation ABSTRACT: We propose a novel test structure for charge pumping current (Icp) measurement to estimate the interface state density at gate insulator/Si substrate in vertical Si power MOSFET. In this structure, the source and base of that are separated by modifying the layout of implantation and trench contact, without requiring additional process steps. | |
11:10 | 5.2 | A Novel Separated Source Electrodes Kelvin (SSEK) Structure for Extracting Channel Mobility in the 4H-SiC VDMOSFET Wen-Shu Chen, An-Ching Li, Chia-Lung Hung1, Yi-Kai Hsiao1, Bing-Yue Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C. 1Semiconductor Research Center, Hon Hai Research Institute, Hsinchu, Taiwan, R.O.C. ABSTRACT: A novel Separated Source Electrodes Kelvin (SSEK) structure that can effectively eliminate most of the series resistance of a VDMOSFET is proposed for extracting channel mobility. We are able to separately measure the resistance of the left and right channels, thereby allowing for a more accurate extraction of the channel mobility. | |
11:30 | 5.3 | Modified Angelov Model with Improved Accuracy for RF GaN-on-Si HEMTs David C. Chen, Min Li Chou, Kerwin Lin, Mike Hsieh, Perry Lin, Heng Ching Lin, Kevin Lee, Alex Hou, Barry Lin, M. C. Lai Wavetek Microelectronics Corporation (WTK), HsinChu, Taiwan ABSTRACT: Modified Angelov model of RF GaN-on-Si HEMTs with improved accuracy is proposed. Simulation results of one set of this proposed model parameters are in excellent agreement with the measurement data of DC, S-parameter, and large-signal. Verification with dual-gate RF switch of GaN-on-Si HEMT is provided. Corresponding model/PDK is released for design and manufacturing. | |
11:50 | 5.4 | Passive and Causal Modeling of 300-GHz-Band IC Capacitors Using Rational Polynomial Approximation Shun Beppu, Yuto Hirayama, Shinsuke Hara1, Akifumi Kasamatsu1, Yoshio Mita2, Kyoya Tkano Department of Electrical Engineering, Tokyo University of Science, Chiba, Japan 1National Institute of Information and Communications Technology, Tokyo, Japan 2Department of Electrical Engineering, Tokyo University of Science, Tokyo, Japan ABSTRACT: This research presents a method to model MOM capacitors for 300-GHz band applications using rational polynomial approximation (RPA). While initial approximations often lead to negative element values due to measurement errors, the model is refined by re-fitting with restrictions to ensure passivity and causality. This approach produces accurate equivalent circuits suitable for high-frequency simulations. The method was validated with measurement with test structure chip fabricated by 0.13 μm SiGe BiCMOS process. | |
12:00 | Lunch | ||
13:20 | Invited Talk 2 Shuhei Amakawa Hiroshima University ABSTRACT: This talk will discuss a couple of topics in on-chip transmission line measurements. The first topic will be the characteristic impedance measurement, which is significantly more challenging than the measurement of the other parameter, the propagation constant. The second topic will be the measurement of differential transmission lines. Specifically, how to establish 50-ohm-referenced S-parameter measurement reference planes on coupled transmission lines will be discussed. | ||
Session 6: Cryogenic Measurements | |||
14:20 | 6.1 | Oscillation in Cryogenic DC Measurements of High Power LDMOS Devices and Solution Yili Wang, Kejun Xia1, Guofu Niu, Michael Hamilton, Xu Cheng2 Alabama Micro/Nanoelectronics Science and Technology Center, Auburn University, Auburn, AL, USA 1TSMC, Taiwan, R.O.C. 2NXP Semiconductors, Arizona, USA ABSTRACT: Cryogenic DC measurements of high-power LDMOS devices encounter unique oscillations at low temperatures, disappearing above 200 K. These oscillations are correlated with negative differential resistance (NDR) due to self-heating. We eliminate the oscillation by adding a resistor between the drain and source terminals. This method, combined with DC de-embedding, ensures accurate device characterization across temperatures. | |
14:40 | 6.2 | Measurement of Subthreshold Current Variability at 1.5 K Using Addressable MOSFET Array Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hiroshi Oka1, Takahiro Mori1, Masaharu Kobayashi2, Toshiro Hiramoro Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 1National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan 2Systems Design Lab (d.lab), The University of Tokyo, Tokyo, Japan ABSTRACT: Variability of 65 nm bulk MOSFETs in subthreshold region were measured at 300 K and 1.5 K using addressable transistor arrays. It was confirmed that variability of current onset voltage (COV) significantly increases at 1.5 K. It is shown that the cut-off performance of the FETs at 1.5 K is governed by variability of subthreshold current including COV, rather than steep minimum subthreshold slope. | |
15:00 | 6.3 | Hysteresis-Induced Neuromorphic Behavior in 180nm Bulk PMOS Devices at 3K Fiheon Imroze, Bhavani Yalagala, Meraj Ahmad, Mostafa Elsayed, Robert Graham, Giuseppe Colletta, Hadi Heidari, Martin Weides James Watt School of Engineering, University of Glasgow, Glasgow, United Kingdom ABSTRACT: This work investigates the neuromorphic behavior of TSMC 180nm bulk PMOS devices at 3K, focusing on hysteresis and synaptic characteristics. Gated pulsed measurements reveal potentiation and depression behavior, with conductance changes due to pulse amplitude and width variations. These findings contribute to the early stage development of cryogenic neuromorphic quantum computing systems. | |
15:20 | Break | ||
15:50 | ICMTS 2025 Presentation Yuzo Fukuzaki Rapidus, Inc. | ||
Session 7: Process Characterization | |||
16:00 | 7.1 | A Test Structure for Analyzing Self-Heating Induced Distortion in On-Chip Current Sensing Resistors Heng Ma, Shoubhik Karmakar, Huajun Zhang, Yuyan Liu, Haidong Guo1, Marco Berkhout2, Qinwen Fan Delft University of Technology, Delft, The Netherlands 1ams OSRAM, Plano, TX, USA 2Monolithic Power Systems, Enschede, The Netherlands ABSTRACT: This paper presents a test structure for a 27mΩ diffusion current sensing resistor to analyze distortion caused by self-heating. A parallel Kelvin connection minimizes parasitic effects from metals and vias. Additionally, a diode array is used to characterize self-heating, providing insights into distortion mechanisms. | |
16:20 | 7.2 | Novel Test Structures for 3D NAND Array Plasma Damage Monitoring Keerti Kalia, Roberta Rita Bottini1, Ken Marr, Allen Mcteer, Cheah Zhin Mow2, James Davis Micron Technology, Inc., Boise, ID, USA 1Micron Technology, Inc., Vimercate, Italy 2Micron Technology, Inc., Singapore ABSTRACT: This study explores the possibility of introducing a new test structure to monitor and signal, plasma damage induced by the memory array process steps. The experimental data shows a clear relationship with the array process, proving the validity of the idea. NHV and NLV devices were used as sense monitors to capture the impact from the plasma damage, presenting a proof of concept to detect changes in electrical characteristics caused by the plasma interactions. | |
16:40 | 7.3 | Advantage and Challenge of Electrical Critical Dimension Test Structures for Electroplated High Aspect Ratio Nano Structures (HARNS) on Insulating Materials Yoshio Mita, Ayako Mizushima, Noriko Kawai1, Tsuboi Shinji1, Yurie Inoue1, Etsuko Ohta1, Shun Yasunaga, Ryosho Nakane1, David Bourrier2, Amel Beghersa2, Hugues Granier2, Akio Higo1 Department of Electrical Engineering and Information Systems, the University of Tokyo, Tokyo, Japan 1Systems Design Lab (d.lab), School of Engineering, the University of Tokyo, Tokyo, Japan 2LAAS-CNRS, Toulouse, France ABSTRACT: Electrical Critical Dimension Test Structures (ECD-TS) have been applied for development of new technology: Metallic High Aspect Ratio Nano Structures (Metal-HARNS). The HARNS refers to electro mechanical structures scaled down to submicron (>260nm confirmed) while keeping its thickness (<1500nm confirmed). Two major advantage and challenge have been confirmed through measurement: (1) insulating material showed critical advantage on ECD over Scanning Electron Microscope CD assessment and (2) seed conductive layer affected the measurement as leakage path. | |
17:00 | 7.4 | Fabrication of NbO2 based IMT Selector Devices via 300mm Based Memory Test Vehicle Karsten Beckmann, Martin Rodgers, Theodore Wallach1, Ross Paries1, Nathaniel Cady1 NY CREATES, Albany, NY, USA 1College of Nanotechnology, Science, and Engineering, University at Albany, Albany, NY, USA ABSTRACT: Nanoscale NbO2 based Insulator-Metal Transition devices were fabricated on a 300mm memory test vehicle with device sizes as low as 120 nm. Metastable NbO2 was deposited through sputter deposition in an oxygen-controlled environment. Endurance of up to 2.5x107 cycles was achieved with an Roff/Ron ratio above 100 and an extrapolation towards >2000 with further device scaling. | |
17:20 | End of Day 2 | ||
18:30 | Banquet |