IEEE International Conference on Microelectronic Test Structures
ICMTS Papers
| 2024 | 9.3 | Test Structure to Assess Bump Shape Influence on Hybrid Bonding A. Mizushima, K. Misumi, S. Yasunaga, A. Higo, R. Nakane, K. Tsumura1, K. Higashi1, Y. Ochiai, Y. Mita Graduate School of Engineering, The University of Tokyo, Tokyo, Japan 1Toshiba Corporation, Kawasaki, Japan DOI: 10.1109/ICMTS59902.2024.10520685 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 9.2 | Electrical behavior of ALD-molybdenum films in the thin-film limit K. van der Zouw, S. D. Dulfer, A. A. I. Aarnink, A. Y. Kovalgin MESA+ Institute for Nanotechnology, University of Twente, AE Enschede, The Netherlands DOI: 10.1109/ICMTS59902.2024.10520676 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 9.1 | An Add-in Test Structure Chip to Unitedly Assess PVD Material Properties in University Open Nanotechnology Platform S. Yasunaga, K. Misumi, A. Mizushima, A. Toyokura, E. Ota, Y. Inoue, M. Fujiwara, N. Kawai, M. Yoda, S. Tsuboi, T. Sawamura, A. Higo, R. Nakane, Y. Ochiai, Y. Mita Department of Electrical Engineering, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS59902.2024.10520699 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 8.4 | Use of DC Probes for Multi-MHz Measurements of Crosstalk and Substrate Coupling in Gallium Nitride Power Integrated Circuits M. Cui, S. Lam Department of Electrical and Electronic Engineering, Xi’an Jiaotong-Liverpool University, Suzhou, China DOI: 10.1109/ICMTS59902.2024.10520677 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 8.3 | A Neural Network-based Manufacturing Variability Modeling of GaN HEMTs F. Chavez, D. Bavi, N. C. Miller1, S. Khandelwal School of Engineering, Macquarie University, Australia 1Department of Electrical and Computer Engineering, Michigan State University, USA DOI: 10.1109/ICMTS59902.2024.10520695 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 8.2 | Method for Suppressing Trap-Related Memory Effects in IV Characterizations of GaN HEMTs J. Bremer, N. Rorsman, M. Thorsell Microwave Electronics Laboratory, Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS59902.2024.10520686 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 8.1 | Test Structures to Investigate ESD Robustness of Integrated GaN Devices W. -C. Wang, M. -D. Ker Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520680 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 7.3 | Evaluation of Lab-based Lithium Niobate Surface Acoustic Wave Test Structure Using Efficient Maskless Lithography and SMA Connection Approach for Microfluidic Applications M. S. Parvez, S. Hussain, M. Goeckner, C. D. Young, J. -B. J. Lee1 The University of Texas at Dallas, Richardson, TX, USA 1Baylor University, Waco, TX DOI: 10.1109/ICMTS59902.2024.10520693 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 7.2 | Modified Bisection Thru-Only Deembedding Algorithm for Long Test Fixtures A. Quint, L. Valenziano, J. Hebeler, T. Zwick, A. Bhutani Institute of Radio Frequency Engineering and Electronics, Karlsruhe Institute of Technology, Karlsruhe, Germany DOI: 10.1109/ICMTS59902.2024.10520703 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 7.1 | Understanding the Substrate Effect on De-embedding Structures Fabricated on SOI Wafers Using Electromagnetic Simulation B. N. Wesling, M. Deng1, C. Mukherjee1, T. Mikolajick, J. Trommer, C. Maneux1 NaMLab gGmbH, Dresden, Germany 1IMS, Talence Cedex, France DOI: 10.1109/ICMTS59902.2024.10520694 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 6.4 | Making Accurate and Consistent Wafer Measurements with Next Generation Guarded True-Kelvin MEMS DC Probes C. B. Sia, Y. Funatoko, I. Kunioka, M. Watanabe, P. Andrews, K. Dawson, M. Sameshima, T. Saeki, J. Yang, J. Li, X. Li, S. Guo, L. Fan, W. M. Lim, E. Wilcox, A. Lord, S. Lastella, N. Kawamata, J. Klattenhoff, J. Kister, M. Losey, M. Slessor FormFactor Inc., Singapore DOI: 10.1109/ICMTS59902.2024.10520687 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 6.3 | Statistical investigation of SnOx RRAM memories for switching characteristics A. Panca, A. Serb, S. Stathopoulos, T. Prodromakis Institute for Integrated Micro and Nano Systems, University of Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520675 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 6.2 | Rapid MOSFET threshold voltage testing for high throughput semiconductor process monitoring M. H. Herman, T. T. Nguyen, K. Wong, J. Johnson, B. Morris Parametric Test Group, Advantest America, San Jose, United States DOI: 10.1109/ICMTS59902.2024.10520252 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 6.1  | Efficient Characterization Methodology for Low-Frequency Noise Monitoring L. Pirro, T. Chohan, P. Liebscher, M. Juettner, F. Holzmueller, R. Jain, Y. Raffel1, K. Seidel1, R. R. Olivo1, A. Zaka, J. Hoentschel GlobalFoundries Fab1 LLC & Co.KG, Dresden, Saxony, Germany 1Fraunhofer-IPMS, Dresden, Saxony, Germany DOI: 10.1109/ICMTS59902.2024.10520698 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 5.4 | Parametric Optimization of RF MEMS Variable Capacitor with High Linearity for C-Band Applications S. Shaheen, P. Lomax, T. Arslan Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS59902.2024.10520682 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 5.3 | Analysis methodology of Deep Trench Isolation Field-Effect Passivation techniques for Image Sensors through dedicated test structures S. Tlemsani, S. Ricq, O. Marcelot1, P. Magnan1 STMicroelectronics, Crolles, France 1Institut Supérieur de l'Aéronautique et de l'Espace (ISAE), Toulouse, France DOI: 10.1109/ICMTS59902.2024.10520689 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 5.2 | Droplet Impact Sensing with Low Noise Coplanar Reverse-Electrowetting Test Structures A. Moyo, M. W. Shahzad, S. Smith1, J. Terry1, Y. Mita2, J. Lewis, Y. Li Department of Mechanical and Construction Engineering, Faculty of Engineering and Environment, Northumbria University, Newcastle Upon Tyne, UK 1Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, Edinburgh, UK 2Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS59902.2024.10520253 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 5.1 | Test structure for chemiluminescence measurement in aqueous solutions: initial design A. A. Moreno-Guerrero, C. Dunare, A. J. Walton, P. Lomax, J. G. Terry, I. Underwood School of Engineering, The University of Edinburgh, United Kingdom DOI: 10.1109/ICMTS59902.2024.10520697 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 4.3 | Compact expression to model the effects of dielectric absorption on analog-to-digital converters S. Saro, P. Palestri1, E. Caruso2, P. Toniutti2, R. Calabro2, S. Terokhin2, F. Driussi DPIA, University of Udine, Italy 1University of Modena and Reggio, Emilia, Italy 2Infineon Technologies Austria, Villach, Austria DOI: 10.1109/ICMTS59902.2024.10520681 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 4.2 | Impedance Measurement Platform for Statistical Capacitance and Current Characteristic Measurements of Arrayed Cells with Atto-order Precision K. Saito, T. Suzuki, H. Mitsuda, T. Nozaki, T. Mawaki, R. Kuroda Graduate School of Engineering, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS59902.2024.10520692 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 4.1 | Analysis and Compensation of the Series Resistance Effects on the Characteristics of Ferroelectric Capacitors M. Massarotto, F. Driussi, M. Bucovaz, A. Affanni, S. Lancaster1, S. Slesazeck1, T. Mikolajick1, D. Esseni DPIA, University of Udine, Udine, Italy 1NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS59902.2024.10520684 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 3.3 | A Testbed for Cryogenic On-wafer Noise Measurement Using Cold Source Method with Temperature-Dependent Loss Correction G. -W. Huang, B. -Y. Chen, Y. -S. Shiao, C. -W. Chuang, L. -C. Shen, K. -M. Chen, C. -S. Chiu Taiwan Semiconductor Research Institute, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS59902.2024.10520691 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 3.2 | Gaussian process-based device model toward a unified current model across room to cryogenic temperatures M. Shintani, T. Iwasaki, T. Sato1 Graduate School of Science and Technology, Kyoto Institute of Technology Matsugasaki, Sakyo-ku, Kyoto, Japan 1Graduate School of Informatics, Kyoto University Yoshida-Hon-Machi, Sakyo-ku, Kyoto, Japan DOI: 10.1109/ICMTS59902.2024.10520702 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 3.1 | Transistor Matrix Array for Measuring Variability and Random Telegraph Noise at Cryogenic Temperatures T. Mizutani, K. Takeuchi, T. Saraya, H. Oka1, T. Mori1, M. Kobayashi, T. Hiramoro Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 1National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan DOI: 10.1109/ICMTS59902.2024.10520700 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 2.3 | A 4H-SiC Trench MOS Capacitor Structure for Sidewall Oxide Characteristics Measurement H. -L. Huang, L. -T. Hsuesh, Y. -C. Tu, B. -Y. Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS59902.2024.10520701 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 2.2 | Test Structures of Cross-Domain Interface Circuits with Deep N-Well Layout to Improve CDM ESD Robustness H. -M. Huang, M. -D. Ker Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS59902.2024.10520690 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 2.1 | A novel test structure with two active areas for eNVM reliability studies K. Alkema, F. Melul, V. D. Marca1, M. Bocquet1, M. Akbal, A. Regnier, S. Niel2, F. La-Rosa STMicroelectronics Rousset, France 1CNRS, IM2NP UMR 7334, Aix-Marseille University, Marseille, France 2STMicroelectronics Crolles, France DOI: 10.1109/ICMTS59902.2024.10520674 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 1.3 | A Step-by-Step Layout Transformation Approach to Differentiate How Multiple Layout Dependent Effects Modify Device and Circuit Performance L. Lu, K. Xia1, R. van Langevelde, C. C. McAndrew, W. Li Front End Innovation, NXP Semiconductors 1Power Management Business Development, TSMC DOI: 10.1109/ICMTS59902.2024.10520696 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 1.2 | Test Structures for studying the impact of the backend contact metallization on the performance and stress sensitivity of SiGe HBTs O. Dieball, H. Tuinhout, J. Zaal1 Modeling, NXP Semiconductors, Eindhoven, The Netherlands 1Package Innovation, NXP Semiconductors, Nijmegen, The Netherlands DOI: 10.1109/ICMTS59902.2024.10520678 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | 1.1 | Layout Dependent Effects Of Passive Devices And Their Impact On Analog Integrated Circuits A. Jayakumar, M. van Dort, M. Vertregt, G. D. J. Smit, R. Lander, I. Liu, P. Volf NXP Semiconductors B.V, Nijmegen, Netherlands DOI: 10.1109/ICMTS59902.2024.10520688 HOVER FOR ABSTRACT | PDF Xplore |
| 2024 | B1 | How to write excellent papers C. Cagli STMicroelectronics, Crolles, France HOVER FOR ABSTRACT | |
| 2023 | 9.3 | Identifying nano-Schottky diode currents in silicon diodes with 2D interfacial layers T. Knežević, L. K. Nanver1 Ruđer Bošković Institute, Zagreb, Croatia 1MESA+ Institute of Nanotechnology, University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS55420.2023.10094164 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 9.2 | Demonstration of frequency doubler application using ZnO-DNTT anti-ambipolar switch device Y. Lee, H. J. Hwang, B. H. Lee Department of Electrical Engineering, Center for Semiconductor Technology Convergence, Pohang University of Science and Technology, Pohang, Gyeongbuk, Republic of Korea DOI: 10.1109/ICMTS55420.2023.10094079 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 9.1 | Bridging Large-Signal and Small-Signal Responses of Hafnium-Based Ferroelectric Tunnel Junctions M. Massarotto, M. Segatto, F. Driussi, A. Affanni, S. Lancaster1, S. Slesazeck1, T. Mikolajick1, D. Esseni DPIA, University of Udine Udine, Italy 1NaMLab gGmbH, Dresden, Germany DOI: 10.1109/ICMTS55420.2023.10094178 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 8.3 | Technology-Dependent Modeling of MOSFET Parasitic Capacitances for Circuit Simulation D. Navarro, C. Tanaka, K. Adachi1, T. Naito, K. Tada, A. Hokazono Memory Division, KIOXIA Corporation, Yokohama, Japan 1KIOXIA Corporation, Institute of Memory Technology Research and Development, Yokohama, Japan DOI: 10.1109/ICMTS55420.2023.10094071 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 8.2 | Introducing Transfer Learning Framework on Device Modeling by Machine Learning K. Niiyama, H. Awano, T. Sato Graduate School of Informatics, Kyoto University Yoshida-hommachi, Kyoto, Sakyo, Japan DOI: 10.1109/ICMTS55420.2023.10094067 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 8.1 | Accurate Gate Charge Modeling of HV LDMOS Transistors for Power Circuit Applications X. Jie, R. v. Langevelde, K. Xia1, L. Chao, C. C. McAndrew, Q. Zhang, M. Bacchi2, W. Li NXP Semiconductors, Front End Innovation 1TSMC, Special Technology Product Engineering 2NXP Semiconductors, Business Line Advanced Analog DOI: 10.1109/ICMTS55420.2023.10094091 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 7.5 | Solderable Multisided Metal Patterns Enables 3D Integrable Direct Laser Written Polymer MEMS L. Ivy, A. Lal The SonicMEMS Laboratory, School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA DOI: 10.1109/ICMTS55420.2023.10094101 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 7.4 | Improving Performance of FBARs by Advanced Low-Temperature High-Pressure Technology Y. -F. Tu, T. -C. Chang1, K. -J. Zhou1, W. -C. Hung1, T. -T. Kuo2, C. -H. Lien Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan 1Department of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan 2Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS55420.2023.10094148 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 7.3 | Damage Assessment Structure of Thermal-Annealing Post-Processing on CMOS LSIs Y. Okamoto, N. Makimoto, K. Misumi1, T. Kobayashi, Y. Mita1, M. Ichiki Sensing System Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan 1School of Electrical Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS55420.2023.10094159 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 7.2 | Test Structures for Studying Coplanar Reverse- Electrowetting for Vibration Sensing and Energy Harvesting A. Moyo, M. W. Shahzad, J. G. Terry1, S. Smith1, Y. Mita2, Y. Li Department of Mechanical and Construction Engineering, Faculty of Engineering and Environment, Northumbria University, Newcastle upon Tyne, UK 1School of Engineering,Institute for Integrated Micro and Nano Systems,The University of Edinburgh, Edinburgh, UK 2Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS55420.2023.10094057 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 7.1 | Application of Greek cross structures for process development of electrochemical sensors M. Zhang, S. Zhang, C. Dunare, J. R. K. Marland, J. G. Terry, S. Smith School of Engineering, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS55420.2023.10094096 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 6.4 | Wafer Level Reliability Monitoring of NBTI Using Polysilicon Heater Structures for Production Measurements Y. -H. Cheng Central Engineering, onsemi, East Greenwich, 1900 South County Trail, USA DOI: 10.1109/ICMTS55420.2023.10094064 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 6.3 | An Electrical Inline-Testable Structure to Monitor Gate-Source/Drain Short Defect Caused by Imperfect Fin-Cut Patterning in FinFET Technology H. Zhu, K. Onishi, S. Wu, A. Yang, B. -W. Jeong1, S. -J. Lim1, N. Jing, C. -H. Lee, D. Conrady, D. Chidambarrao IBM Infrastructure, IBM Corp, 2070 Rt 52, B300A, Hopewell Junction, NY, USA 1Samsung Electronics Co. Ltd., San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, Republic of Korea DOI: 10.1109/ICMTS55420.2023.10094149 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 6.2 | Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation V. Vidya, N. Zamdmer, T. Mechler, K. Onishi, D. Chidambarrao, B. W. Jeong1, Y. G. Ko1, C. H. Lee, J. Sim, M. Angyal, E. Crabbe IBM Systems, IBM Corp, 2070 Route 52, B300-A, Hopewell Junction, NY, USA 1Samsung Electronics Co. Ltd, San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, Republic of Korea DOI: 10.1109/ICMTS55420.2023.10094206 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 6.1 | Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications H. -C. Hong, L. -Y. Lin, B. -C. Chen1 Institute of Electrical and Computer Engineering 1Institute of Electrical and Control Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS55420.2023.10094078 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 5.4 | Effect of Quadruple Size Transistor on SRAM Physically Unclonable Function Stabilized by Hot Carrier Injection S. Xu, K. Liu1, Y. Tang, R. Zhang, H. Shinohara1 Information, Production and Systems Research Center, Waseda University, Kitakyushu, Japan 1Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan DOI: 10.1109/ICMTS55420.2023.10094187 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 5.3 | Variability Evaluation of MOS-gated PNPN Diode for Hardware Spiking Neural Network T. Takada, T. Mori, J. Ida Division of Electrical Engineering, Kanazawa Institute of Technology, Ishikawa, Japan DOI: 10.1109/ICMTS55420.2023.10094054 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 5.2 | Variability of MOSFET Series Resistance Extracted from Individual Devices: Is Direct Variability Measurement Possible? K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS55420.2023.10094106 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 5.1 | Measurement of Temperature Effect on Comparator Offset Voltage Variation Y. Iwata, T. Kitamura, M. Islam Department of Electrical Engineering, Graduate School of Engineering, Kyoto University Kyoto Daigaku Katsura, Nishikyo-ku, Kyoto, JAPAN DOI: 10.1109/ICMTS55420.2023.10094194 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 4.4 | Test Bench for Biopotential Instrumentation Amplifier using Single-Ended to Differential Amplifiers S. Thanapitak, P. Sedtheetorn, P. Chanyagorn, T. Chulajata, S. Bhatranand, P. Phattanasri Department of Electrical Engineering, Faculty of Engineering, Mahidol University, Nakhon Pathom, Thailand DOI: 10.1109/ICMTS55420.2023.10094130 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 4.3 | Test Structure for Evaluation of Pad Size for Wafer Probing B. Smith, D. Hall, G. Tranquillo1 NXP Semiconductors, Austin, TX, USA 1Celadon Systems, Inc., Burnsville, MN, USA DOI: 10.1109/ICMTS55420.2023.10094145 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 4.2 | A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact Y. -L. Chen, S. -H. Lai, J. -H. Lin, B. -Y. Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS55420.2023.10094097 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 4.1 | The Pressing Probe Needle Technique for Characterizing Mechanical Stress Sensitivity of Semiconductor Devices H. Tuinhout, O. Dieball NXP Semiconductors, Eindhoven, The Netherlands DOI: 10.1109/ICMTS55420.2023.10094063 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 3.5 | Comparative study on characteristics of GaN-based MIS-HEMTs with Al2O3 and Si3N4 gate insulators under Hot Carrier Degradation P. -Y. Wu, X. -Y. Tsai1, T. -C. Chang2, T. -M. Tsai, S. M. Sze1 Pei-Yu Wu and Tsung-Ming Tsai are with the Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung, Taiwan 1Xin-Ying Tsai and Simon M. Sze are with the Department of Electronics Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan. 2Ting-Chang Chang is with Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS55420.2023.10094072 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 3.4 | On-Resistance Measurements of Low Voltage MOSFET at wafer level K. Oasa, T. Nishiwaki, T. Ohguro1, Y. Saito, Y. Kawaguchi1 Toshiba Electronic Devices & Storage Corporation, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan 1Toshiba Electronic Devices & Storage Corporation, Iwauchi-Machi, Nomi, Ishikawa, 1-1, Japan DOI: 10.1109/ICMTS55420.2023.10094127 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 3.3 | New Extraction Method for Intrinsic Qrr of Power MOSFETs T. Hara, S. Nakajima, T. Ohguro, K. Miyashita Advanced Semiconductor Device Development Center, Toshiba Electronic Devices & Storage Corporation DOI: 10.1109/ICMTS55420.2023.10094069 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 3.2 | Measuring of parasitic resistance of stacked chip of Si power device T. Ohguro, H. Kojima, T. Hara, T. Nishiwaki1, K. Kobayashi Toshiba Electronic Devices & Storage Corporation, 1-1, Iwauchi-Machi, Nomi, Ishikawa, Japan 1Toshiba Electronic Devices & Storage Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan DOI: 10.1109/ICMTS55420.2023.10094137 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 3.1 | Distributed field plate effects in split-gate trench MOSFETs R. Tambone, A. Ferrara, F. Magrini1, A. Hoffmann1, A. Wood, G. Noebauer, E. Gondro1, R. J. E. Hueting2 Infineon Technologies Austria AG, Siemenstrasse 2, Villach, Austria 1Infineon Technologies AG, Am Campeon 1, Neubiberg, Germany 2University of Twente, Drienerlolaan 5, NB Enschede, The Netherlands DOI: 10.1109/ICMTS55420.2023.10094167 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 2.3 | VSS-Bias-Based Measurement of Random Telegraph Noise in Hybrid SRAM PUF after Hot Carrier Injection Burn-in K. Liu, Y. Tang, S. Xu, H. Shinohara Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan DOI: 10.1109/ICMTS55420.2023.10094138 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 2.2 | An Extended Method to Analyze Boron Diffusion Defects in 16 nm Node High-Voltage FinFETs T. -T. Kuo, Y. -C. Chen, T. -C. Chang1, F. -M. Ciou2, C. -H. Yeh3, P. -H. Chen4, S. M. Sze5 Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan 1Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, Taiwan 2Department of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan 3Department of Photonics, National Sun Yat-sen University, Kaohsiung, Taiwan. 4Department of Applied Science, R. O. C. Naval Academy, Kaohsiung, Taiwan 5National Yang Ming Chiao Tung University, Hsinchu, Taiwan DOI: 10.1109/ICMTS55420.2023.10094125 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 2.1 | Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure O. Gauthier, S. Haendler, R. Beucher, P. Scheer, Q. Rafhay1, C. Theodorou1 STMicroelectronics, Crolles, France 1Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP, IMEP-LAHC, Grenoble, France DOI: 10.1109/ICMTS55420.2023.10094087 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 1.5 | Analysis of Critical Schottky Distance Effect and Distributed Set Voltage in HfO2-based 1T-1R Device S. -K. Lin, T. -C. Chang1, W. -C. Huang1, Y. -F. Tan2, C. -H. Lien Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan 1Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan 2Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung, Taiwan DOI: 10.1109/ICMTS55420.2023.10094175 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 1.4 | Automated RRAM measurements using a semi-automated probe station and ArC ONE interface A. G. Panca, A. Serb, S. Stathopoulos, S. K. Garlapati1, T. Prodromakis Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh, UK 1Materials Science And Metallurgical Engineering, Indian Institute of Technology Hyderabad, Telangana, India DOI: 10.1109/ICMTS55420.2023.10094156 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 1.3 | Real-time electrical measurements during laser attack on STT-MRAM N. Yazigy, J. Postel-Pellerin, V. D. Marca, R. C. Sousa1, A. -L. Ribotta2, G. D. Pendina1, P. Canet IM2NP, CNRS, UMR 7334, 5 rue Enrico Fermi, Aix-Marseille Université, Marseille, France 1CNRS, CEA, SPINTEC, SPINTEC, University Grenoble Alpes, Grenoble, France 2Mines Saint-Etienne, CEA, Leti, Centre CMP, Gardanne, France DOI: 10.1109/ICMTS55420.2023.10094166 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 1.2 | Test Methodology Development for Investigating CeRAM at Elevated Temperatures A. A. Gruszecki, R. Prasad, S. V. Suryavanshi1, G. Yeric1, C. D. Young Electrical and Computer Engineering Department, The University of Texas at Dallas, Richardson, Texas, USA 1Cerfe Labs, Austin, Texas, USA DOI: 10.1109/ICMTS55420.2023.10094065 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | 1.1 | Discrete current limiting circuit for emerging memory programming L. Laborie, P. Trotti, K. Veyret, C. Cagli1 Univ. Grenoble Alpes,CEA, Leti, Grenoble, France 1STMicroelectronics, Grenoble, France DOI: 10.1109/ICMTS55420.2023.10094099 HOVER FOR ABSTRACT | PDF Xplore |
| 2023 | B2 | Making Good Presentations B. Smith NXP Semiconductors HOVER FOR ABSTRACT | |
| 2023 | B1 | How to Make a Better Abstract Y. Mita The University of Tokyo, Tokyo, Japan HOVER FOR ABSTRACT | |
| 2022 | 10.4 | Introduction of a Reset MOSFET to Mitigate the Influence of Ionic Movement in Perovskite MOSFET Photodetector Measurements J. Liu, R. Haroldson1, G. Verkhogliadov2, D. Lin3, Q. Gu3, A. A. Zakhidov4, W. Hu5, C. D. Young6 Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson 75080, USA 1Department of Physics, The University of Texas at Dallas, Richardson 75080, USA 2The School of Physics and Engineering, ITMO University, St. Petersburg 197101, Russia 3Department of Electrical and Computer Engineering, North Carolina State Univeristy, Raleigh 27695, USA 4Department of Physics, The University of Texas at Dallas, Richardson, USA 5Department of Laboratory Medicine, Sichuan University, Chengdu 610041, China 6Department of Materials Science and Engineering, Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson 75080, USA DOI: 10.1109/ICMTS50340.2022.9898238 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 10.3 | On-Chip Nano Pulse Test Element Group for Analysis of Synaptic Devices T. -G. Ryu, S. -H. Kim, K. -W. Song, H. -J. Shin, Y. -J. An, S. -B. Eadi, H. -M. Kwon1, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejoen, Korea 1Department of Semiconductor Processing Equipment, Semiconductor Convergence Campus of Korea Polytechnics College, Ansung, Korea DOI: 10.1109/ICMTS50340.2022.9898163 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 10.2 | A two-step parameter extraction methodology for graphene field-effect transistors K. Jeppson Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS50340.2022.9898249 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 10.1 | Test Structure of Bi-stable Spring towards TopoMEMS Ising Machine Y. Mita, M. Ezawa, K. Tsuji, E. Lebrasseur, T. Sawamura, S. Tsuboi, A. Mizushima, Y. Ochiai, A. Higo Graduate School of Engineering, The University of Tokyo (UTokyo), Tokyo, Japan DOI: 10.1109/ICMTS50340.2022.9898227 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 9.3 | Characterization and Monitoring Platform for Single-Photon Avalanche Diodes in the Development of a Photon-to-Digital Converter Technology S. Parent, F. Vachon, V. Gauthier, A. Paquette, J. Deschamps, T. Rossignol, P. Arsenault, C. Paulin, J. Lemay, N. Roy, M. Côté, D. Dupont, S. Martel, H. Dautet, S. A. Charlebois, J. -F. Pratte Institut Interdisciplinaire d'Innovation Technologique, Université de Sherbrooke, Sherbrooke, Canada DOI: 10.1109/ICMTS50340.2022.9898180 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 9.2 | Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers J. van Zoeren, L. K. Nanver Faculty of EEMCS, University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS50340.2022.9898239 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 9.1 | dGPLVM: A Nonparametric Device Model for Statistical Circuit Simulation K. Shimozato, T. Sato Graduate School of Informatics, Kyoto University, Yoshida-hon-machi, Sakyo, Kyoto 606-8501, Japan DOI: 10.1109/ICMTS50340.2022.9898216 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 8.2 | Procedure for Controlling Pad Scrub During High-Temperature Wafer Probing D. Hall, B. Smith, D. Pechonis, M. Nelson, G. Tranquillo1 NXP Semiconductors, Austin, TX, USA 78750 1Celadon Systems, Inc., Burnsville, MN, USA 55337 DOI: 10.1109/ICMTS50340.2022.9898166 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 8.1 | Issues and advances in rapid Quasi-Static CV for high throughput semiconductor process monitoring M. H. Herman, D. Jang, M. Nagel, B. Morris Parametric Test Group, Advantest America, San Jose, United States DOI: 10.1109/ICMTS50340.2022.9898273 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 7.2 | Contact Fail Monitoring with an Epi Resistance Test Structure for 7nm FinFET Product C. H. Lee, B. W. Jeong1, S. Wu, M. Kim1, X. Chen, K. Onishi, C. Manya, L. Anastos, J. Sim, M. Angyal Fabless Foundry Interaction, Processor Product Engineering, IBM Systems, NY 12533-6683 1Samsung Electronics Co. Ltd., Hwasung-City, Gyeonggi-Do, 445-701, Republic of Korea DOI: 10.1109/ICMTS50340.2022.9898262 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 7.1 | DFI Filler Cells -- New Embedded Type of Test Structures for Non-Contact Detection of Electrical Defects on Product Wafers S. Lam, C. Hess, L. Weiland, M. Moe, X. W. Shen, J. Chen, I. De, M. Strojwas, T. Brozek PDF Solutions, Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS50340.2022.9898254 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 6.3 | Test Measurements for Charge Trapping in Different Polarization Ferroelectric FETs S. Deng, K. Ni, S. K. Kurinec Department of Electrical & Microelectronic Engineering, Rochester Institute of Technology, Rochester, New York 14623, USA DOI: 10.1109/ICMTS50340.2022.9898271 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 6.2 | Application of a Test Structure for Minimising Seed Layer Thickness of Electroplated Ferromagnetic Films A. W. S. Ross, C. M. Dover, S. Smith1, J. G. Terry, A. R. Mount2, A. J. Walton School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, Edinburgh, Scotland, UK 1School of Engineering, Institute for Bioengineering, The University of Edinburgh, Edinburgh, Scotland, UK 2School of Chemistry, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS50340.2022.9898250 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 6.1 | An Evaluation for Quality Inspection of Epitaxial Layer and Heavily-doped 4H-SiC Substrate by Simple Schottky Barrier Diode and MOS Capacitor K. -W. Chu, C. -W. Tseng1, B. -Y. Tsui1, Y. -C. S. Wu, C. -J. Yang2, C. Hsu2 Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C 1Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C 2Innovation Technology Research Center, GlobalWafers Co., Ltd., Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS50340.2022.9898247 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 5.4 | CMOS Platform TEG for Development of High Performance Synaptic Devices Y. -J. An, S. -H. Kim, K. -W. Song, H. -J. Shin, T. -G. Ryu, S. -B. Eadi, H. -M. Kwon1, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejoen, Korea 1Department of Semiconductor Processing Equipment, Semiconductor Convergence Campus of Korea Polytechnics College, Ansung, Korea DOI: 10.1109/ICMTS50340.2022.9898228 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 5.3 | SuperCAST: a full free addressable memory array V. D. Marca, J. Guilleau-Tavernier, P. Laine, F. Melul, M. Bocquet, T. Kempf1, L. Welter1, J. -M. Moragues1, A. Regnier1, J. -M. Portal Aix-Marseille Université, 13397 Marseille, France 1STMicroelectronics, 13106 Rousset, France DOI: 10.1109/ICMTS50340.2022.9898189 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 5.2 | Statistical Modeling of SRAM PUF Cell Mismatch Shift Distribution After Hot Carrier Injection Burn-In K. Liu, K. Takeuchi1, H. Shinohara2 Information, Production and Systems, Research Center, Waseda University, Kitakyushu, Japan 1Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 2Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan DOI: 10.1109/ICMTS50340.2022.9898258 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 5.1 | Embedded measurement of the SET switching time of RRAM memory cells F. Jebali, E. Muhr, M. Alayan, M. C. Faye, D. Querlioz1, F. Andrieu2, E. Vianello2, G. Molas2, M. Bocquet, J. M. Portal Aix-Marseille Univ., Marseille, France 1Université Paris-Saclay, 91120 Palaiseau, France 2CEA, LETI, Grenoble, France DOI: 10.1109/ICMTS50340.2022.9898162 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 4.3 | Single Device MOSFET Series Resistance Extraction Methods: Comparison Between Newer and Older K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, JAPAN DOI: 10.1109/ICMTS50340.2022.9898270 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 4.2 | Temperature Characterizations of Multi-Unit and Multi-finger Dependencies on AlGaN/GaN Ridge HEMTs H. Aoki, N. Kuroda1, A. Yamaguchi1, K. Nakahara R&D Center, ROHM Co., Ltd, Kyoto 615-8585, Japan 1Core Technology R&D Division, R&D Center, ROHM Co., Ltd, Kyoto 615-8585, Japan DOI: 10.1109/ICMTS50340.2022.9898230 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 4.1 | Layout-Dependent Vertical and In-Plane Leakage Current Reduction of Organic Thin-Film Transistors by Layer Contact Restriction K. Oshima, K. Kuribara1, T. Sato Graduate School of Informatics, Kyoto University, Yoshida-hon-machi, Sakyo, Kyoto 606-8501, Japan 1National Institute of Advanced Industrial Science and Technology (AIST) DOI: 10.1109/ICMTS50340.2022.9898196 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 3.3 | Utilization of Poly Heater Test Structures in the Characterization of Bias Temperature Instability Y. -H. Cheng, M. Cook, D. Allman Corporate Research and Development, East Greenwich, RI 02818, USA DOI: 10.1109/ICMTS50340.2022.9898183 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 3.2 | Characterizing Aging Degradation of Integrated Circuits with a Versatile Custom Array of Reliability Test Structures A. Santana-Andreo, P. Martin-Lloret, E. Roca, R. Castro-Lopez, F. V. Fernandez IMSE, CSIC-Universidad de Sevilla, Seville, Spain DOI: 10.1109/ICMTS50340.2022.9898256 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 3.1 | Two-pads per electrode in-situ test structure for micron-scale flip-chip bonding reliability of chip-on-chip device Y. Ebihara, A. Mizushima, T. Yoda1, K. Hirakawa1, M. Iwase1, M. Ogasawara1, A. Higo, Y. Ochiai, Y. Mita School of Engineering, The University of Tokyo, Japan 1Laboratory for Future Interdisciplinary Research of Science and Technology, Tokyo Institute of Technology, Japan DOI: 10.1109/ICMTS50340.2022.9898248 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 2.4 | Optimal Test Structures for the Characterization of Integrated Transformers at mm-wave frequencies using the Open/Thru De-embedding Technique M. Lauritano, P. Baumgartner Intel Germany, Neubiberg, Germany DOI: 10.1109/ICMTS50340.2022.9898235 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 2.3 | Modeling and Verificaion of Millimeter-Wave nMOSFET up to 50 GHz in 180 nm CMOS Technology K. Sekine, K. Takano, Y. Umeda Department of Electrical Engineering, Tokyo University of Science, Chiba, Japan DOI: 10.1109/ICMTS50340.2022.9898222 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 2.2 | 300-GHz Back-Radiation On-Chip-Antenna Measurement with Electromagnetic-Wave-Absorption Sheet S. Lee, K. Katayama1, K. Takano1, M. Fujita2, M. Toyoda2, S. Hara3, I. Watanabe3, A. Kasamatsu3, S. Amakawa1, T. Yoshida1, M. Fujishima1 Inst. of Innovative Research, Tokyo Inst. of Technol., Yokohama, Japan 1Grad. School of Advanced Sci. and Eng., Hiroshima Univ., Higashihiroshima, Japan 2New Business Produce Div., Maxell, Ltd., Otokuni, Japan 3Advanced ICT Research Inst., Nat’l. Inst. of Info. and Comms. Technol., Koganei, Japan DOI: 10.1109/ICMTS50340.2022.9898229 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 2.1 | S-Parameter Measurement and EM Simulation of Electronic Devices towards THz frequency range C. Yadav, S. Fregonese1, M. Cabbia1, M. Deng1, M. De Matos1, T. Zimmer1 National Institute of Technology Calicut, Kozhikode, Kerala, India 1IMS Laboratory, University of Bordeaux, France DOI: 10.1109/ICMTS50340.2022.9898233 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 1.4 | Combined Machine Learning Techniques For Characteristics Classification and Threshold Voltage Extraction of Transistors H. M. Koçak, J. Mitard1, A. T. Naskali Department of Computer Engineering, Galatasaray University, Istanbul, Turkey 1Compute and Memory Department, IMEC, Leuven, Belgium DOI: 10.1109/ICMTS50340.2022.9898251 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 1.3 | Design of Low-Cost Test Structures for Measuring Within-Die Process Skew Variations A. Majumdar, N. Chong AMD Inc., San Jose, CA 95124 DOI: 10.1109/ICMTS50340.2022.9898217 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 1.2 | Test Structures for Characterising the Fabrication of Miniature Reference Electrodes C. Dunare, S. Zhang, J. R. K. Marland, A. Tsiamis, P. Sullivan, I. Underwood, J. G. Terry, A. J. Walton, S. Smith1 School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, Edinburgh, Scotland, UK 1School of Engineering, Institute for Bioengineering, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS50340.2022.9898104 HOVER FOR ABSTRACT | PDF Xplore |
| 2022 | 1.1 | Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization M. Udo, M. Islam1, H. Onodera2 Graduate School of Informatics, Kyoto University, Yoshida-honmachi, Sakyo-ku, Kyoto 606-8501, JAPAN 1Graduate School of Engineering, Kyoto University, Kyoto Daigaku Katsura, Nishikyo-ku, Kyoto 615-8510, JAPAN 2Faculty of Informatics, Osaka Gakuin University, 2-36-1 Kishibe-Minami, Suita 564-8511, JAPAN DOI: 10.1109/ICMTS50340.2022.9898111 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 9.4 | Test Setup Optimization and Automation for Accurate Silicon Photonics Wafer Acceptance Production Tests C. B. Sia, T. L. Yap1, A. Sasidharan1, J. H. Tan1, R. Chen1, J. Leo1, S. L. Tan1, G. C. Man1 FormFactor Singapore Pte. Ltd, 30 Marsiling Industrial Estate Rd 8, #05-02, Singapore 1GLOBALFOUNDRIES Singapore, 60 Woodlands Industrial, Park D Street 2, Singapore DOI: 10.1109/ICMTS48187.2020.9107907 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 9.3 | Experimental and simulation analysis of carrier lifetimes in GaAs/AlGaAs Avalanche Photo-Diodes F. Driussi, A. Pilotto, D. De Belli, M. Antonelli1, F. Arfelli2, G. Biasiol3, G. Cautero1, R. H. Menk1, C. Nichetti1, L. Selmi4, T. Steinhartova2, P. Palestri DPIA, Università degli Studi di Udine, Udine, Italy 1Elettra-Sincrotrone Trieste S.C.p.A, Area Science Park Basovizza, Trieste, Italy 2Department of Physics, Università di Trieste, Trieste, Italy 3IOM CNR, Laboratorio TASC, Area Science Park Basovizza, Trieste, Italy 4Department of Medical Imaging, University of Saskatchewan, Saskatoon, Canada DOI: 10.1109/ICMTS48187.2020.9107920 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 9.2 | Diode design for studying material defect distributions with avalanche-mode light emission M. Krakers, T. Knezevic, K. M. Batenburg, X. Liu, L. K. Nanver MESA+ Institute, Faculty of EEMCS, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS48187.2020.9107933 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 9.1 | Comparison of cut-back method and optical backscatter reflectometry for wafer level waveguide characterization A. Peczek, C. Mai1, G. Winzer1, L. Zimmermann1 IHP Solutions Gmb, Im Technologiepark 25, Frankfurt Oder, Germany 1IHP, Im Technologiepark 25, Frankfurt Oder, Germany DOI: 10.1109/ICMTS48187.2020.9107905 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 8.3 | Integrated Variability Measurements of 28 nm FDSOI MOSFETs down to 4.2 K for Cryogenic CMOS Applications B. C. Paz, L. L. Guevel, M. Cassé, G. Billiot, G. Pillonnet, A. Jansen1, S. Haendler2, A. Juge2, E. Vincent2, P. Galy2, G. Ghibaudo, M. Vinet, S. d. Franceschi1, T. Meunier, F. Gaillard MINATEC Campus, CEA-Leti, Université Grenoble Alpes, Grenoble, France 1CEA-IRIG, Université Grenoble Alpes, Grenoble, France 2STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS48187.2020.9107906 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 8.2 | Comparison of Extraction Methods for Threshold Voltage Shift in NBTI Characterization Y. -H. Cheng, M. Cook, C. Kendrick Corporate Research and Development, N Semiconductor 1900 South County Trail, East Greenwich, RI, USA DOI: 10.1109/ICMTS48187.2020.9107918 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 8.1 | Anomalous Scaling of Parasitic Capacitance in FETs with a High-K Channel Material A. E. M. Smink, M. J. de Jong, H. Hilgenkamp, W. G. van der Wiel, J. Schmitz MESA + Institute for Nanotechnology, University of Twente, Enschede, AE, The Netherlands DOI: 10.1109/ICMTS48187.2020.9107901 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 7.5 | Application of Broadband RF Metrology to Integrated Circuit Interconnect Reliability Analyses: Monitoring Copper Interconnect Corrosion in 3D-ICs P. K. Amoah, J. Perez, Y. S. Obeng Nanoscale Device Characterization Division, Physical Measurement Laboratory, National Institute of Standards and Technology, 100 Bureau Drive, Gaithersburg, MD DOI: 10.1109/ICMTS48187.2020.9107926 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 7.4 | Investigation of Test Structures for the Characterization of Very Fast Electro Static Discharge Events M. Lauderdale, E. Onyegam, S. Ruth, A. Gerdemann NXP Semiconductors, Austin, Texas, USA DOI: 10.1109/ICMTS48187.2020.9107924 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 7.3 | Comparison of nMOSFET Structures for Millimeter-Wave Frequencies in 0.18-μm CMOS technology T. Hagiwara, N. Yamaki, K. Takano, Y. Umeda Department of Electrical Engineering, Tokyo University of Science, Yamazaki, Chiba, Japan DOI: 10.1109/ICMTS48187.2020.9107912 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 7.2 | Influence of series resistance on the experimental extraction of FinFET noise parameters A. Tataridou, G. Ghibaudo, C. Theodorou IMEP-LAHC Univ. Grenoble Alpes, Univ. Savoie Mont Blanc CNRS, Grenoble INP, Institute of Engineering Univ. Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS48187.2020.9107908 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 7.1 | Novel Statistical Modeling and Parameter Extraction Methodology of Cutoff Frequency for RF-MOSFETs C. Tanaka, Y. Iguchi, A. Sueoka, S. Yoshitomi Memory Division, Kioxia Corporation 2-5-1, Kasama, Sakae-ku, Yokohama, Japan DOI: 10.1109/ICMTS48187.2020.9107914 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 6.4 | Test Structure for Measuring the Selectivity in Vapour Etch Processes M. Rondé, A. J. Walton, J. G. Terry School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, UK DOI: 10.1109/ICMTS48187.2020.9107934 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 6.3 | Microheater isolation characterisation to aid the optimisation of a MEMS Leidenfrost engine A. Buchoux, P. Agrawal1, G. G. Wells1, R. Ledesma-Aguilar1, A. J. Walton, J. G. Terry, G. Mchale1, K. Sefiane, A. A. Stokes School of Engineering, The University of Edinburgh, Edinburgh, UK 1Faculty of Engineering & Environment, Northumbria University Newcastle upon Tyne, UK DOI: 10.1109/ICMTS48187.2020.9107902 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 6.2 | Drop-in test structure chip to visualize residual stress of Ru/Cu film grown by atomic layer deposition and supercritical fluid deposition N. Usami, E. Ota1, A. Higo1, T. Momose2, Y. Mita Department of Electrical Engineering and Information Systems (EEIS), The University of Tokyo 1Systems Design Lab. (d.lab), School of Engineering, The University of Tokyo 2Department of Materials Engineering, The University of Tokyo DOI: 10.1109/ICMTS48187.2020.9107904 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 6.1 | A nondestructive analysis method for the frontside-release process of thermal sensors C. Liu, J. Fu, Y. Hou, R. Liu1, Q. Zhou, D. Chen Key Laboratory of Microelectronic Device & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China 1Wuxi Innovation Center for Internet of Things, Jiangsu Wuxi, China DOI: 10.1109/ICMTS48187.2020.9107917 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 5.5 | Coaxial Circular Test Structure Applicable to both Ohmic and Schottky Characteristics for ZnO/Si Heterojunctions Assessment N. Miyazawa, N. Usami, H. Wang1, T. Kubo1, H. Segawa1, Y. Mita, A. Higo2 Department of Electrical Engineering and Information Systems, The University of Tokyo 1Research Center for Advanced Science and Technology, The University of Tokyo 2Systems Design Lab, School of Engineering, The University of Tokyo DOI: 10.1109/ICMTS48187.2020.9107928 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 5.4 | OxRAM BER Scaling Trends on 4 kb Mixed-Diameter Test Vehicle J. Sandrini, C. Cagli, L. Grenouillet, N. Castellani, V. Meli, F. Gaillard CEA-LETI, Minatec Campus, 17 rue des Martyrs, Grenoble Cedex 9, France DOI: 10.1109/ICMTS48187.2020.9107927 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 5.2 | Electrical and optical localisation of leakage current and breakdown point in SiOC:H low-k dielectrics M. Vidal-Dhô, Q. Hubert, P. Gonon1, B. Pelissier1, P. Lentrein, P. Ray, J. -M. Moragues, P. Fornara STMicroelectronics, Rousset, France 1LTM CNRS, Grenoble, France DOI: 10.1109/ICMTS48187.2020.9107909 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 5.1 | Multiscale modeling of CeO2/La2 O3 stacks for material/defect characterization B. Dianat, A. Padovani1, L. Larcher1 Department of Sciences and Method for Engineering, University of Modena and Reggio Emilia Via Amendola 2, Reggio Emilia, Italy 1Applied Materials - MDLx Italy R&D Via Meuccio Ruini 74/L, Reggio Emilia, Italy DOI: 10.1109/ICMTS48187.2020.9107922 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 4.4 | Test structure and measurement system for characterising the electrochemical performance of nanoelectrode structures I. Schmueser, E. O. Blair, Z. Isiksacan, Y. Li, D. K. Corrigan1, A. A. Stokes, J. G. Terry, A. R. Mount1, A. J. Walton School of Engineering, The University of Edinburgh, Edinburgh, UK 1School of Chemistry, The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS48187.2020.9107930 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 4.3 | A Rapid, Reliable and Less-destructive On-chip Mass Measurement for 3D Composite Material Testing Microstructures G. Hwang, C. David1, A. Paris1, D. Decanini1, A. Mizushima2, Y. Mita LIMMS-CNRS, Institute of Industrial Science, University of Tokyo, Japan 1C2N-CNRS, University Paris-Sud, University Paris-Saclay, Palaiseau, France 2VLSI Design and Education Center, The University of Tokyo, 2-11-16, Yayoi, Bunkyo-ku, Tokyo, Japan DOI: 10.1109/ICMTS48187.2020.9107932 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 4.2 | Verification and Induction Method for Low Frequency Response Failure Modes in Acoustic MEMS G. Hantos, D. Marc P.Y. School of Engineering & Physical Sciences Research Institute of Sensors, Signals and System, Heriot-Watt University, Edinburgh, Scotland DOI: 10.1109/ICMTS48187.2020.9107925 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 4.1 | Automated Wafer-Level Characterisation of Electrochemical Test Structures for Wafer Scanning I. Schmueser, C. L. Mackay1, F. Moore, K. Doherty, J. P. Elliott1, A. R. Mount1, A. J. Walton, S. Smith, J. G. Terry School of Engineering, The University of Edinburgh, Edinburgh, U.K. 1School of Chemistry, The University of Edinburgh, Edinburgh, U.K. DOI: 10.1109/ICMTS48187.2020.9107903 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 3.3 | Increased Delay Variability due to Random Telegraph Noise under Dynamic Back-gate Tuning M. Udo, K. Murakami, A. K. M. M. Islam1, H. Onodera Department of Communications and Computer Engineering, Kyoto University Yoshida-honmachi, Sakyo-ku, Kyoto, JAPAN 1Department of Electrical Engineering, Kyoto University Kyoto Daigaku Katsura, Nishikyo-ku, Kyoto, JAPAN DOI: 10.1109/ICMTS48187.2020.9107919 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 3.2 | Test Structures for Noise Reduction of Fully Depleted-Silicon on Insulator p-Type Tunneling FET Using Channel Orientation H. -D. Song, H. -S. Song, S. B. Eadi, H. -W. Choi, G. -W. Lee, H. -D. Lee Department of Electronics Engineering, Chungnam National University, 99 Daehak-ro, Yuseong-gu, Daejeon DOI: 10.1109/ICMTS48187.2020.9107915 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 3.1 | Area-Efficient and Bias-Flexible Inline Monitoring Structure for Fast Characterization of RTN and Transistor Local Mismatch in Advanced Technologies A. Jayakumar, N. Chan, L. Pirro, O. Zimmerhackl, M. Otto, T. Kleissner, J. Hoentschel GLOBALFOUNDRIES Fab1 LLC & Co.KG, Wilschdorfer Landstrasse 101, Dresden, Saxony, Germany DOI: 10.1109/ICMTS48187.2020.9107935 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 2.4 | Extraction of Ultra-Low Contact Resistivity by End-Resistance Method B. -Y. Tsui, Y. -H. Lee, D. -Y. Wu, Y. -J. Lee1, M. -Y. Li1 Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R. O. C. 1Taiwan Semiconductor Research Institute, Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS48187.2020.9107910 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 2.3 | Characterization of parametric mismatch attributable to plastic chip encapsulation H. Tuinhout, A. Damian1, A. Z. -v. Duijnhoven CTO / Modeling, Characterization & SPICE Libraries, Nijmegen NXP Semiconductors, Eindhoven, Netherlands 1Package Core Technology, Nijmegen NXP Semiconductors, Netherlands DOI: 10.1109/ICMTS48187.2020.9107916 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 2.2 | Automated Generation, Fabrication and Measurement of Parametric Test Structures for Rapid Prototyping Using Optical Maskless Lithography P. Sullivan, A. Tsiamis, M. Rondé, A. J. Walton, S. Smith, J. G. Terry The School of Engineering, The University of Edinburgh, UK DOI: 10.1109/ICMTS48187.2020.9107929 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 2.1 | Standardization of Specific Contact Resistivity Measurements using Transmission Line Model (TLM) S. Grover, S. Sahu, P. Zhang1, K. O. Davis2, S. K. Kurinec Rochester Institute of Technology, USA, Rochester, New York 1Michigan State University, USA, East Lansing, MI 2University of Central Florida, USA, Orlando, FL DOI: 10.1109/ICMTS48187.2020.9107911 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 1.2 | Calibration of CBCM Measurement Hardware B. Smith, E. Onyegam, D. Hall, B. Verzi NXP Semiconductors, Austin, Texas, USA DOI: 10.1109/ICMTS48187.2020.9107913 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 1.1 | Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics S. Nishizawa, K. Ito1 Faculty of Engineering, Fukuoka University, 8-19-1, Nanakuma, Jyonan-Ku, Fukuoka, JAPAN 1Graduate School of Science and Engineering, Saitama University DOI: 10.1109/ICMTS48187.2020.9107931 HOVER FOR ABSTRACT | PDF Xplore |
| 2020 | 1 | Experimental Set-Up For Novel Energy Efficient Charge-based Resistive RAM (RRAM) Switching P. Trotti, G. Pillonet, G. Molas, S. Oukassi, E. Nowak CEA, LETI, Univ. Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS48187.2020.9107936 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 10.2 | A compact model of I -V characteristic degradation for organic thin film transistors M. Saito, M. Shintani1, K. Kuribara2, Y. Ogasahara2, T. Sato Graduate School of Informatics, Kyoto University, Kyoto, Japan 1Graduate School of Science and Technology, Nara Institute of Science and Technology, Nara, Japan 2National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2019.8730987 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 10.1 | Understanding the Effects of Low-Temperature Passivation and Annealing on ZnO TFTs Test Structures R. A. Rodriguez-Davila, P. Bolshakov, C. D. Young, M. Quevedo-Lopez Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX, USA DOI: 10.1109/ICMTS.2019.8730965 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 9.3 | Damage Assessment Structure of Test-Pad Post-Processing on CMOS LSIs Y. Okamoto, A. Mizushima1, N. Usami, J. Kinoshita2, A. Higo1, Y. Mita School of Electrical Engineering, The University of Tokyo, Tokyo, Japan 1VLSI Design & Education Center (VDEC), The University of Tokyo, Tokyo, Japan 2NEXTY Electronics Corporation, Tokyo, Japan DOI: 10.1109/ICMTS.2019.8730991 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 9.2 | Characterization of Micro-Bumps for 3DIC Wafer Acceptance Tests C. B. Sia FormFactor Inc., Singapore DOI: 10.1109/ICMTS.2019.8730921 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 9.1 | Probing impact on pad moisture tightness: A challenge for pad size reduction M. Vidal-Dho, Q. Hubert1, P. Gonon, P. Delorme1, J. Jacquot1, M. Marchetti1, L. Beauvisage1, J. -M. Moragues1, P. Potard2, P. Fornara1, J. -P. Escales1, P. Sallagoity1, O. Pizzuto1, D. Maury1, J. -M. Mirabel1 LTM CNRS, Grenoble, France 1STMicroclcctronics Rousset, Rousset, France 2STMicroelectronics, Crolles, FR DOI: 10.1109/ICMTS.2019.8730990 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 8.3 | A Method to Determine the Electret Charge Potential of MEMS Vibrational Energy Harvester using Pure White Noise H. Mitsuya, H. Ashizawa, H. Homma1, G. Hashiguchi2, H. Toshiyoshi1 Saginomiya Seisakusho, Inc., Saitama, Japan 1Institute of Industrial Science, The university of Tokyo, Tokyo, Japan 2Shizuoka University, Shizuoka, Japan DOI: 10.1109/ICMTS.2019.8730995 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 8.2 | Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation A. K. M. M. Islam, R. Shimizu1, H. Onodera1 Graduate School of Engineering, Kyoto University, Kyoto, JAPAN 1Graduate School of Informatics, Kyoto University, Kyoto, JAPAN DOI: 10.1109/ICMTS.2019.8730976 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 8.1 | Experimental Extraction of Body Bias Dependence of Low Frequency Noise in sub-micron MOSFETs from Subthreshold to Moderate Inversion Regime C. Tanaka, K. Adachi1, A. Nakayama, Y. Iguchi, S. Yoshitomi Design Technology Innovation Division 1Device Technology Research & Development Center, Toshiba Memory Corporation DOI: 10.1109/ICMTS.2019.8730953 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 7.7 | A Study of Test Throughput Analysis on Capacitance Measurement of Parallel Test Structures Using LCR and Direct Charge based Instruments V. Katragadda, N. Deshmukh, A. Gasasira, C. -M. Lee1, A. Cusick PDYE Test & Char, GlobalFoundries, Malta, NY, USA 1Semiconductor Test, Keysight Technologies, USA DOI: 10.1109/ICMTS.2019.8730979 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 7.5 | Physical, small-signal and pulsed thermal impedance characterization of multi-finger SiGe HBTs close to the SOA edges M. Couret, G. Fischer1, S. Frégonése, T. Zimmer, C. Maneux IMS Laboratory, University of Bordeaux, Talence, France 1IHP - Leibniz-Insitut for innovative Mikroelektronik, Frankfurt (Oder), Germany DOI: 10.1109/ICMTS.2019.8730964 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 7.4 | Characterization and Modeling of Zener Diode Breakdown Voltage Mismatch M. Yang, C. C. McAndrew1, L. Chao, K. Xia NXP Semiconductors, Beijing, PRC 1NXP Semiconductors, Chandler, AZ DOI: 10.1109/ICMTS.2019.8730968 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 7.2 | Fast Tera-Ohm Measurement Approach Using V93k AVI64 DC Scale Card J. Stolle, R. Poirier1, M. Froehle2, H. Weindl2, M. Naiman, V. Kriegerstein2 Advantest Europe GmbH, Boeblingen, Germany 1Innova-test, Bordeaux, France 2GLOBALFOUNDRIES, Dresden, Germany DOI: 10.1109/ICMTS.2019.8730977 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 7.1 | A Study of Power Supply Stability in Ring Oscillator Structures B. Smith, D. Hall, B. Verzi1, D. Pechonis NXP Semiconductors, Austin, Texas, USA 1Keysight Technologies, Austin, Texas, USA DOI: 10.1109/ICMTS.2019.8730980 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 6.4 | Analysis of Test Structure Design Induced Variation in on Si On-wafer TRL Calibration in sub-THz C. Yadav, S. Fregonese, M. Deng, M. Cabbia, M. De Matos, M. Jaoul, T. Zimmer IMS Laboratory, University of Bordeaux, Talence cedex, France DOI: 10.1109/ICMTS.2019.8730962 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 6.3 | Comparison of MOSFET Threshold Voltage Extraction Methods with Temperature Variation Y. -H. Cheng ON Semiconductor, Corporate Research and Development, East Greenwich, RI, USA DOI: 10.1109/ICMTS.2019.8730978 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 6.2 | On-Chip Threshold Voltage Variability Detector Targeting Supply of Ring Oscillator for Characterizing Local Device Mismatch P. Jain, B. P. Das Department of ECE, Indian Institute of Technology, Roorkee, India DOI: 10.1109/ICMTS.2019.8730952 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 6.1 | Two-transistor Voltage-Measurement-Based Test Structure for Fast Extraction of MOS Mismatch Design Parameters J. P. M. Brito, S. Bampi1 CEITEC S.A. Semiconductors, Porto Alegre, Brazil 1Graduate Program on Microelectronics - PGMICRO, Federal University of of Rio Grande do Sul - UFRGS DOI: 10.1109/ICMTS.2019.8730918 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 5.3 | A study on statistical parameter modeling of power MOSFET model by principal component analysis H. Tsukamoto, M. Shintani1, T. Sato2 Faculty of Engineering, Kyoto University, Kyoto, Japan 1Graduate School of Science and Technology, Nara Institute of Science and Technology, Nara, Japan 2Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2019.8730946 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 5.1 | Vertical Bipolar Transistor Test Structure for Measuring Minority Carrier Lifetime in IGBTs K. Takeuchi, M. Fukui, T. Saraya, K. Itou, T. Takakura, S. Suzuki, Y. Numasawa1, K. Kakushima2, T. Hoshii2, K. Furukawa2, M. Watanabe2, N. Shigyo2, H. Wakabayashi2, M. Tsukuda, A. Ogura1, K. Tsutsui2, H. Iwai2, S. Nishizawa, I. Omura, H. Ohashi2, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan 1Meiji University, Kawasaki, Japan 2Tokyo Institute of Technology, Yokohama, Japan DOI: 10.1109/ICMTS.2019.8730922 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 4.4 | Proposed one-dimensional passive array test circuit for parallel kelvin measurement with efficient area use M. Rerecich, C. D. Young1 Samsung Austin Semiconductor, LLC, Austin, TX, USA 1Materials Science and Engineering Department, University of Texas at Dallas, Dallas, TX, USA DOI: 10.1109/ICMTS.2019.8730948 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 4.3 | Evaluation of Truly Passive Crossbar Memory Arrays on Short Flow Characterization Vehicle Test Chips C. Hess, T. Brozek, H. Schneider, Y. Yu, M. Lunenborg, K. H. Ng, D. Ciplickas, R. Vallishayee, C. Dolainsky, L. H. Weiland PDF Solutions Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS.2019.8730984 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 4.2 | Optimization of 3ω Method for Phase-Change Materials Thermal Conductivity Measurement at High Temperature A. L. Serra, G. Bourgeois, M. C. Cyrille, J. Cluzel, J. Garrione, G. Navarro, E. Nowak CEA, Univ. Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS.2019.8730993 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 4.1 | Resistance Measurement Platform for Statistical Analysis of Next Generation Memory Materials T. Maeda, Y. Omura1, A. Teramoto2, R. Kuroda, T. Suwa2, S. Sugawa2 Graduate School of Engineering, Tohoku University, Sendai, Japan 1School of Engineering, Tohoku University, Sendai, Japan 2New Industry Creation Hatchery Center, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS.2019.8730955 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 3.4 | Test structure to assess the useful extent of regular dummy devices around high-precision metal fringe capacitor arrays H. Tuinhout, I. Brunets, A. Z. -v. Duijnhoven NXP Semiconductors, Eindhoven, AE, The Netherlands DOI: 10.1109/ICMTS.2019.8730988 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 3.3 | Test Structures for Characterising the Silver Chlorination Process During Integrated Ag/AgCl Reference Electrode Fabrication C. Dunare, J. R. K. Marland, E. O. Blair1, A. Tsiamis, F. Moorel, J. G. Terry, A. J. Walton, S. Smith School of Engineering, The University of Edinburgh, Edinburgh, UK 1Department of Biomedical Engineering, University of Strathclyde, Glasgow, UK DOI: 10.1109/ICMTS.2019.8730966 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 3.2 | Continuity assessment for supercritical-fluids-deposited (SCFD) Cu film as electroplating seed layer N. Usami, E. Ota1, A. Higo1, T. Momose2, Y. Mita1 Tokyo Daigaku, Bunkyo-ku, Tokyo, JP 1VLSI Design and Education Center (VDEC), The University of Tokyo 2Department of Material Engineering, The University of Tokyo DOI: 10.1109/ICMTS.2019.8730945 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 3.1 | Electrical characterization of hot-wire assisted atomic layer deposited Tungsten films K. van der Zouw, A. A. I. Aarnink, J. Schmitz, A. Y. Kovalgin MESA+, University of Twente, Enschede, AE, The Netherlands DOI: 10.1109/ICMTS.2019.8730954 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 5.2 | Modeling and Test Structures for Accurate Current Sensing in Vertical Power FETs M. Chu, T. Harjono, K. Joardar, V. Krishnamurthy Advanced Technology Development, Texas Instruments, Dallas, TX DOI: 10.1109/ICMTS.2019.8730949 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 2.3 | Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions M. Jaoul, D. Ney1, D. Céli1, C. Maneux, T. Zimmer IMS, Université Bordeaux I, Talence, France 1ST Microelectronics, Crolles, France DOI: 10.1109/ICMTS.2019.8730951 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 2.2 | Extremely Low Voltage Operatable On-Chip- Monitor-Test Circuit for Plasma Induced Damage using High sensitivity Ring-VCO(Voltage Controlled Oscillator) M. Tomita, S. Mori, Y. Fukuzaki, K. Ogawa, S. Miyake, H. Ohnuma Sony Semiconductor Solutions Corporation, Kanagawa, Japan DOI: 10.1109/ICMTS.2019.8730985 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 2.1 | Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive ring Oscillators R. Kishida, T. Asuke1, J. Furuta1, K. Kobayashil1 Department of Electrical Engineering, Tokyo University of Science, Noda, Chiba, Japan 1Department of Electronics, Kyoto Institute of Technology, Japan DOI: 10.1109/ICMTS.2019.8730967 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 1.4 | Wafer-Level Test Solution Development for a Quad-Channel Linear Driver Die in a 400G Silicon Photonics Transceiver Module Y. Wang, H. Ding, B. Blakely, A. Yan Department of Silicon Photonics Test Development, GLOBALFOUNDRIES, Essex Junction, VT, USA DOI: 10.1109/ICMTS.2019.8730947 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 1.3 | In search of a hole inversion layer in $\mathrm{Pd}/\mathrm{MoO}_{x}/\mathrm{Si}$ diodes through I- V characterization using dedicated ring-shaped test structures G. Gupta, S. D. Thammaiah, R. J. E. Hueting, L. K. Nanver MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands DOI: 10.1109/ICMTS.2019.8730920 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 1.2 | PbS Quantum Dot / ZnO Nanowires Hybrid Test Structures for Infrared Photodetector H. Wang, A. Higo1, Y. Mita2, T. Kubo, H. Segawa Research Center for Advanced Science and Technology, The University. of Tokyo, Tokyo, Japan 1VLSI Design and Education Research Center, The University of Tokyo, Tokyo, Japan 2Graduate School of Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2019.8730956 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 1.1 | A Micro Racetrack Optical Resonator Test Structure to Optimize Pattern Approximation in Direct Lithography Technologies A. Higo, T. Sawamura, M. Fujiwara, E. Ota, A. Mizushima, E. Lebrasseur, T. Arakawa1, Y. Mita2 VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan 1Faculty of Eng., Yokohama National University, Kanagawa, Japan 2Dept. of EEIS, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2019.8730981 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 2 | Taming Emerging Devices' Variation and Reliability Challenges with Architectural and System Solutions [Invited] Y. Wang, L. Shao, M. A. Lastras-Montaä±o1, K. -T. Cheng2 Department of Electrical and Computer Engineering, University of California, Santa Barbara, U.S.A. 1FC, Universidad Autónoma de San Luis Potosä, México 2School of Engineering, Hong Kong University of Science and Technology, Hong Kong DOI: 10.1109/ICMTS.2019.8730924 HOVER FOR ABSTRACT | PDF Xplore |
| 2019 | 1 | High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Field-Effect Transistors [Invited] Y. Koide Research Network and Facility Services Division, National Institute for Materials Science (NIMS), Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2019.8730974 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 10.4 | Measurement of temperature effect on random telegraph noise induced delay fluctuation A. K. M. M. Islam, M. Oka1, H. Onodera1 Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan 1Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2018.8383801 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 10.3 | System aware DUT design for optimum on-wafer noise measurement C. -H. Chen, B. Yang, P. -H. Chu, G. Brown, S. Das Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, Canada DOI: 10.1109/ICMTS.2018.8383800 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 10.2 | Measurement time reduction technique for input referred noise of dynamic comparator Y. Ishijima, S. Nakagawa, H. Ishikuro Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japan DOI: 10.1109/ICMTS.2018.8383799 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 10.1 | Importance of complete characterization setup on on-wafer TRL calibration in sub-THz range C. Yadav, M. Deng, M. De Matos, S. Fregonese, T. Zimmer IMS Laboratory, University of Bordeaux, Talence cedex, France DOI: 10.1109/ICMTS.2018.8383798 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 9.4 | Open model for external mechanical stress of semiconductors and MEMS R. T. Buhler, R. C. Giacomini Department of Electrical Engineering, Centro Universitä¡rio FEI, SP, Brazil DOI: 10.1109/ICMTS.2018.8383795 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 9.3 | Wafer level characterisation of microelectrodes for electrochemical sensing applications E. O. Blair, L. P. Basanta1, I. Schmueser2, J. R. K. Marland, A. Buchoux3, A. Tsiamis4, C. Dunare, M. Normand, A. A. Stokes, A. J. Walton, S. Smith4 School of Engineering, Institute for Integrated Micro and Nanosystems 1The University of Edinburgh, Edinburgh, Edinburgh, GB 2School of Chemistry 3School of Engineering, The University of Edinburgh, Edinburgh, UK 4School of Engineering, Institute for Bioengineering DOI: 10.1109/ICMTS.2018.8383793 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 9.2 | Test structure for electrical assessment of UV laser direct fine patterned material N. Usami, A. Higo1, A. Mizushima1, Y. Okamoto, Y. Mita Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Japan 1VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2018.8383794 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 9.1 | An on-chip test structure for studying the frictional behavior of deep-RIE MEMS sidewall surfaces R. R. Reddy, Y. Okamoto1, Y. Mita1 Tokyo Daigaku, Bunkyo-ku, Tokyo, JP 1Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2018.8383792 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 8.5 | Total ionizing dose effects on analog performance of 65 nm bulk CMOS with enclosed-gate and standard layout M. Bucher, A. Nikolaou, A. Papadopoulou, N. Makris, L. Chevas, G. Borghello1, H. D. Koch2, F. Faccio3 School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece 1DPIA, Universit degli Studi di Udine, Udine, Italy 2SEMi, Université de Mons, Mons, Belgium 3EP Dept., CERN, Geneva, Switzerland DOI: 10.1109/ICMTS.2018.8383790 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 8.4 | Sensitivity of high-k encapsulated MoS2 transistors to I-V measurement execution time P. Bolshakov, A. Khosravi, P. Zhao, R. M. Wallace, C. D. Young, P. K. Hurley1 Department of Materials Science and Engineering, The University of Texas at Dallas, TX, USA 1Tyndall National Institute, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.2018.8383789 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 8.3 | Measurement of IGBT trench MOS-gated region characteristics using short turn-around-time MOSFET test structures K. Takeuchi, M. Fukui, T. Saraya, K. Itou, S. Suzuki, T. Takakura, T. Hiramoto Institute of Industrial Science the University of Tokyo Tokyo, Japan DOI: 10.1109/ICMTS.2018.8383788 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 8.2 | Quantitative model of CMOS inverter chain ring oscillator's effective capacitance and its improvements in 14nm FinFET technology S. Y. Mun, J. Cho1, B. Zhu, P. Agnihotri, C. Y. Wong, T. J. Lee, V. Mahajan, B. W. Liu, Y. J. Shi, W. Hong, J. Ciavatti, J. G. Lee, S. B. Samavedam, D. K. Sohn ATD 14NM Device Globalfoundries, NY, Malta 12Global TCAD, Santa Clara, CA DOI: 10.1109/ICMTS.2018.8383787 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 8.1 | Evaluation of Qss on SOI back Si/SiO2 interface by newly designed charge pumping method-TEG K. Takeda, J. Ida, T. Mori, Y. Arai1 Division of Electrical Engineering, Kanazawa Institute of Technology, Ishikawa, Japan 1High Energy Accelerator Research Org.,(KEK), Tsukuba, Japan DOI: 10.1109/ICMTS.2018.8383786 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 7.2 | Algorithm based adaptive parametric testing for outlier detection and test time reduction V. Katragadda, M. Muthee, A. Gasasira, F. Seelmann, J. -H. Liao GLOBALFOUNDRIES, New York, USA DOI: 10.1109/ICMTS.2018.8383784 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 7.1 | Addressable test structure design enabling parallel testing of reliability devices L. DeBruler, D. Pretti, M. Violette, D. Peterson, S. Mujumdar, X. Li, K. Marr Micron Technology Inc., Boise, Idaho DOI: 10.1109/ICMTS.2018.8383783 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 6.4 | All-digital on-chip heterogeneous sensors for tracking the minimum energy point of processors S. Hokimoto, J. Shiomi, T. Ishihara, H. Onodera Graduate School of Informatics, Kyoto University, Kyoto, JAPAN DOI: 10.1109/ICMTS.2018.8383780 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 6.3 | Versatile chip-level integrated test vehicle for dynamic thermal evaluation S. Parameswaran, S. Balakrishnan, B. Ang Silicon Technology Group Xilinx, Inc. 2100 Logic Drive, San Jose, CA, USA DOI: 10.1109/ICMTS.2018.8383779 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 6.2 | DFT-enabled within-die AC uniformity and performance monitor structure for advanced process N. Chong, I. -R. Chen1, D. Cheng, A. Majumdar1, P. -C. Yeh1, J. Chang1 Xilinx Inc, San Jose, CA, US 1Xilinx Inc., San Jose, California, USA DOI: 10.1109/ICMTS.2018.8383778 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 6.1 | On-chip reconfigurable monitor circuit for process variation and temperature estimation T. Kishimoto, T. Ishihara, H. Onodera Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2018.8383777 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 5.4 | NPN mismatch dependence on layout C. Compton Macom, Newport Beach, CA DOI: 10.1109/ICMTS.2018.8383774 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 5.3 | Process variation estimation using a combination of ring oscillator delay and FlipFlop retention characteristics T. Konno, S. Nishizawa, K. Ito Faculty of Engineering, Saitama Univesity 255, Sakura-Ku Saitama, Japan DOI: 10.1109/ICMTS.2018.8383773 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 5.2 | Monte Carlo analysis by direct measurement using Vth-shiftable SRAM cell TEG S. Yamaguchi, D. Nishikata, H. Imi, K. Nakamura Center for Microelectronic Systems, Kyushu Institute of Technology, Iizuka, Fukuoka, JAPAN DOI: 10.1109/ICMTS.2018.8383772 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 5.1 | A test structure to reveal short-range correlation effects of mismatch fluctuations in backend metal fringe capacitors H. Tuinhout, A. Z. -v. Duijnhoven1, I. Brunets NXP Semiconductors, AE Eindhoven, The Netherlands 1NXP Semiconductors, High Tech Campus 46, 5656 AE Eindhoven, The Netherlands DOI: 10.1109/ICMTS.2018.8383771 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 4.5 | Design of ultraflexible organic differential amplifier circuits for wearable sensor technologies M. Kondo, T. Uemura, M. Akiyama, N. Namba, M. Sugiyama, Y. Noda, T. Araki, S. Yoshimoto1, T. Sekitani The Institute of Scientific and Industrial Research, Osaka, Japan 1The Institute of Scientific and Industrial Research, 8-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan DOI: 10.1109/ICMTS.2018.8383769 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 4.4 | Test structures for evaluating Al2O3 dielectrics for graphene field effect transistors on flexible substrates X. Yang, M. Bonmann, A. Vorobiev, K. Jeppson, J. Stake Department of Microtechnology and Nanoscience, Chalmers University of Technology Gothenburg, Sweden DOI: 10.1109/ICMTS.2018.8383768 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 4.3 | Test structures without metal contacts for DC measurement of 2D-materials deposited on silicon L. K. Nanver, X. Liu, T. Knezevic1 MESA+ Institute for Nanotechnology, University of Twente, Enschede, Netherlands 1Faculty of Electrical Engineering and Computing, Micro and Nano Electronics Laboratory, Croatia DOI: 10.1109/ICMTS.2018.8383767 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 4.2 | Test structures for seed layer optimisation of electroplated ferromagnetic films C. M. M. Dover, A. W. S. Ross, S. Smith, J. G. Terry, A. R. Mount, A. J. Walton School of Engineering, University of Edinburgh, UK DOI: 10.1109/ICMTS.2018.8383766 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 4.1 | Reliability analysis of the metal-graphene contact resistance extracted by the transfer length method S. Venica, F. Driussi, A. Gahoi1, S. Kataria1, P. Palestri, M. C. Lenirne1, L. Scimi Universita degli Studi di Udine, Udine, Friuli-Venezia Giulia, IT 1Rheinisch-Westfalische Technische Hochschule Aachen, Aachen, Nordrhein-Westfalen, DE DOI: 10.1109/ICMTS.2018.8383765 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 3.2 | Electrostatic test structures for transmission line pulse and human body model testing at wafer level R. Ashton, S. Fairbanks1, A. Bergen, E. Grund2 Minotaur Labs, Mesa, Arizona, USA 1SRF Technologies, Mesa, Arizona, USA 2Grund Technical Solutions, Milpitas, California, USA DOI: 10.1109/ICMTS.2018.8383762 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 3.1 | Test structure design for model-based electromigration E. Demircan, M. D. Shroff, H. -C. Lee NXP Semiconductors, Austin, TX, USA DOI: 10.1109/ICMTS.2018.8383761 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 2.4 | Efficient parameter-extraction of SPICE compact model through automatic differentiation M. Shintani, M. Hiromoto1, T. Sato1 Graduate School of Information Science, Nara Institute of Science and Technology (NAIST), Japan 1Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2018.8383759 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 2.3 | Validation of the BSIM4 irregular LOD SPICE model by characterization of various irregular LOD test structures B. Peddenpohl, M. Otrokov, J. Wells Cypress Semiconductor, Lexington, Kentucky DOI: 10.1109/ICMTS.2018.8383758 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 2.2 | Modeling split-gate flash memory cell for advanced neuromorphic computing M. Tadayoni, S. Hariharan, S. Lemke, T. Pate-Cazal, B. Bertello, V. Tiwari, N. Do Silicon Storage Technology, A Subsidiary of Microchip Technology Inc, San Jose, California, USA DOI: 10.1109/ICMTS.2018.8383757 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 2.1 | Comprehensive investigation on parameter extraction methodology for short channel amorphous-InGaZnO thin-film transistors C. Tanaka, K. Ikeda Future Memory Development Department, Institute of Memory Technology Research & Development, Saiwai-ku, Kawasaki, Japan DOI: 10.1109/ICMTS.2018.8383756 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 1.4 | Test structures to evaluate the impact of parasitic edge FET on circuits operating in weak inversion D. McQuirk, C. Baker, B. Smith NXP Semiconductors N.V, TX DOI: 10.1109/ICMTS.2018.8383754 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 1.3 | Novel test structures for extracting interface state density of advanced CMOSFETs using optical charge pumping H. -S. Song, D. -J. Oh, S. -Y. Kim, S. -K. Kwon, S. Choi1, D. H. Kim1, D. -H. Lim2, C. -H. Choi2, D. M. Kim1, H. -D. Lee Department of Electronics Engineering, Chungnam National University 1School of Electrical Engineering, Kookmin University 2Division of Materials Science and Engineering, Hanyang Universit DOI: 10.1109/ICMTS.2018.8383753 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 1.2 | Passive permutation multiplexer to detect hard and soft open fails on short flow characterization vehicle test chips C. Hess, S. Yu PDF Solutions Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2018.8383752 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | 1.1 | Test structures for debugging variation of critical devices caused by layout-dependent effects in FinFETs Q. Lin, H. Pan, J. Chang Xilinx Inc., San Jose, CA DOI: 10.1109/ICMTS.2018.8383751 HOVER FOR ABSTRACT | PDF Xplore |
| 2018 | B2 | Making Good Presentations B. Smith NXP Semiconductors HOVER FOR ABSTRACT | |
| 2018 | B1 | How To Write A Good Paper And Get It Published C. McAndrew NXP Semiconductors HOVER FOR ABSTRACT | |
| 2017 | 9.4 | Test structures for nano-gap fabrication process development for nano-electromechanical systems S. Smith, Y. Takeshiro1, Y. Okamoto1, J. G. Terry2, A. J. Walton2, R. Ikeno3, K. Asada3, Y. Mita1 Institute for Bioengineering, The University of Edinburgh, UK 1Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan 2Institute for Integrated Micro and Nano Systems, The University of Edinburgh, UK 3VLSI Design and Education Centre, The University of Tokyo, Japan DOI: 10.1109/ICMTS.2017.7954289 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 9.3 | Test structure configurations for analysis of field effect influenced self-heating and thermal coupling in High Voltage SiGe HBTs B. Ó. hAnnaidh, E. Coyne, B. Lane Process Development, Raheen Industrial Estate, Limerick, Ireland DOI: 10.1109/ICMTS.2017.7954288 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 9.2 | Novel C-V measurements based method for the extraction of GaN buffer layer residual doping level in HEMT I. Nifa, C. Leroux, A. Torres, M. Charles, G. Reimbold, G. Ghibaudo1, E. Bano1 Univ. Grenoble Alpes 1IMEP-LAHC, MINATEC/INPG, Grenoble, France DOI: 10.1109/ICMTS.2017.7954287 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 9.1 | A microsecond time resolved current collapse test setup dedicated to GaN-based Schottky diode characterization T. Lorin, W. Van Den Daele, C. Gillot, M. Charles, J. Biscarrat, M. Plissonnier, G. Ghibaudo1, G. Reimbold CEA, MINATEC Campus, Grenoble, France 1IMEP-LAHC, Universitä© Grenoble Alpes, Grenoble, France DOI: 10.1109/ICMTS.2017.7954286 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 8.4 | Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs M. Bucher, A. Nikolaou, N. Mavredakis, N. Makris, M. Coustans1, J. Lolivier2, P. Habas2, A. Acovic2, R. Meyer2 School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece 1Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland 2EM Microelectronic-Marin SA, Marin-Epagnier, Switzerland DOI: 10.1109/ICMTS.2017.7954285 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 8.3 | Statistical low-frequency noise characterization in sub-15 nm Si/SiGe nanowire Trigate pMOSFETs C. G. Theodorou, R. Lavieville, T. A. Karatsori, S. Barraud1, C. A. Dimitriadis2, G. Ghibaudo IMEP-LAHC, Univ. Grenoble Alpes, Grenoble, France 1CEA-LETI, Univ. Grenoble Alpes, Grenoble, France 2Department of Physics, Aristotle university of Thessaloniki, Greece DOI: 10.1109/ICMTS.2017.7954284 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 8.2 | A variability-based analysis technique revealing physical mechanisms of MOSFET low-frequency noise T. H. Both, J. A. Croon, M. B. da Silva1, H. P. Tuinhout, A. Z. -v. Duijnhoven, A. J. Scholten, G. I. Wirth1 NXP Semiconductors, Eindhoven, The Netherlands 1Universidade Federal do Rio Grande do Sul, Programa de Pós-Graduaä§ä£o em Microeletrônica (PGMicro), Porto Alegre, Brazil DOI: 10.1109/ICMTS.2017.7954283 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 8.1 | A statistical modeling methodology of RTN gate size dependency based on skewed ring oscillators A. K. M. M. Islam, T. Nakai1, H. Onodera1 Institute of Industrial Science, The University of Tokyo, Tokyo, JAPAN 1Graduate School of Informatics, Kyoto University, Kyoto, JAPAN DOI: 10.1109/ICMTS.2017.7954282 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 7.4 | Test structures for stepwise deformation sensing on super-flexible strain sensors C. Wang, B. B. Xu, J. G. Terry1, S. Smith1, A. J. Walton1, Y. Li Faculty of Engineering and Environment, Northumbria University, UK 1SMC, The university of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2017.7954281 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 7.3 | Test structures for optimizing polymer electrolyte performance in a microfabricated electrochemical oxygen sensor J. R. K. Marland, C. Dunare, A. Tsiamis, E. Gonzä¡lez-Fernä¡ndez1, E. O. Blair, S. Smith, J. G. Terry, A. F. Murray, A. J. Walton Schocl of Engineering, University of Edinburgh, Edinburgh, EH9 3FF, UK 1School of Chemistry, University of Edinburgh, Edinburgh, EH9 3FJ, UK DOI: 10.1109/ICMTS.2017.7954280 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 7.2 | Test structures for the characterisation of sensor packaging technology E. O. Blair, A. Buchoux, A. Tsiamis1, C. Dunare, J. R. K. Marland1, J. G. Terry, S. Smith1, A. J. Walton Institute for Integrated Micro and Nano Systems 1Institute for Bioengineering School of Engineering, The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2017.7954279 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 7.1 | A test structure to characterize transparent electrode array platform with TFTs for bio-chemical applications A. Tixier-Mita, S. Ihida, G. Cathcart1, F. A. Shaik1, H. Fujita, Y. Mita2, H. Toshiyoshi3 Institute of Industrial Sciences, The university of Tokyo, Tokyo, Japan 1Research Center for Advanced Research Science and Technology, The University of Tokyo, Tokyo, Japan 2Department of Electrical Engineering and Information Systems, The university of Tokyo, Tokyo, Japan 3Tokyo Daigaku, Bunkyo-ku, Tokyo, JP DOI: 10.1109/ICMTS.2017.7954278 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 6.3 | Development of an Advanced System for Automated 200 mm Wafer Mapping of Stress Using Test Structures S. Lokhandwala, J. Murray, S. Smith, A. R. Mount1, J. G. Terry, A. J. Walton Scottish Microelectronics Centre, The university of Edinburgh, Edinburgh, UK 1Joseph Black Building, The university of Edinburgh, UK DOI: 10.1109/ICMTS.2017.7954277 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 6.2 | A new test vehicle for RRAM array characterization C. Nguyen, C. Cagli, L. Kadura, J. -F. Nodin, S. Bernasconi, G. Reimbold CEA-Leti, Grenoble, FRANCE DOI: 10.1109/ICMTS.2017.7954276 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 6.1 | An arrayed test structure for transistor damage assessment induced by circuit analysis and repairing processes with back-side-accessing Focused Ion Beam N. Usami, J. Kinoshita1, R. Ikeno2, Y. Okamoto, M. Tanno1, K. Asada2, Y. Mita3 Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan 1Van Partners, Toyota Tsusho Electronics Corporation, Tokyo, Japan 2VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan 3Dept. of Spacecraft Engineering, Institute of Space and Astronautical Science, Japan DOI: 10.1109/ICMTS.2017.7954275 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 5.4 | High voltage MOSFETs integration on advanced CMOS technology: Characterization of thick gate oxides incorporating high k metal gate stack from logic core process D. Morillon, F. Julien1, J. Coignus2, A. Toffoli2, L. Welter1, C. Jahan2, J. -P. Reynard1, E. Richard1, P. Masson3 EpOC/Nice Sophia-Antipolis University, Biot, France 1STMicroelectronics, France 2CEA LETI, Grenoble, France 3Universite de Nice Sophia Antipolis, Nice, Provence-Alpes-Cote d'Azu, FR DOI: 10.1109/ICMTS.2017.7954274 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 5.3 | DC and RF characterization of RF MOSFET embedding structure A. Takeshige, K. Katayama, S. Amakawa, K. Takano, T. Yoshida, M. Fujishima Graduate School of Advanced Sciences of Matter, Hiroshima University, Hiroshima, Japan DOI: 10.1109/ICMTS.2017.7954273 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 5.2 | Design of a Broadband CMOS RF Power Amplifier to establish device-circuit aging correlations E. Barajas, D. Mateo, X. Aragones, A. Crespo-Yepes1, R. Rodriguez1, J. Martin-Martinez1, M. Nafria1 Dept. Enginyeria Electrònica, Universitat Politècnica de Catalunya (UPC), Barcelona, Spain 1Dept. Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB), Barcelona, Spain DOI: 10.1109/ICMTS.2017.7954272 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 5.1 | A 130 to 170 GHz integrated noise source based on avalanche silicon Schottky diode in BiCMOS 55 nm for in-situ noise characterization J. C. A. Goncalves, T. Quemerais1, D. Gloria2, G. Avenier2, S. Lepilliet, G. Ducournau3, C. Gaquière, F. Danneville Liemn, UMR CNRS 8520, Villeneuve-d'Ascq, France 1STMicroelectronics, Grenoble, France 2STMicroelectronics, Crolles, France 3Institut d'Electronique de Microelectronique et de Nanotechnologie, Villeneuve-d'Ascq, Hauts-de-France, FR DOI: 10.1109/ICMTS.2017.7954271 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 4.4 | Input capacitance determination of power MOSFETs from switching trajectories K. Oishi, M. Shintani, M. Hiromoto, T. Sato Graduate School of Informatics, Kyoto University, Sakyo, Kyoto, Japan DOI: 10.1109/ICMTS.2017.7954270 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 4.3 | Impact of access resistance on New-Y function methodology for MOSFET parameter extraction in advanced FD-SOI technology J. -B. Henry, A. Cros, J. Rosa, Q. Rafhay1, G. Ghibaudo1 STMicroelectronics, TR&D/STD/TPS/SiRel, Crolles, France 1IMEP-LAHC, MINATEC Campus, Grenoble, France DOI: 10.1109/ICMTS.2017.7954269 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 4.2 | True Kelvin CMOS Test Structure to achieve accurate and repeatable DC wafer-level measurements for device modelling applications C. B. Sia Cascade Microtech Inc. (A FormFactor Company), Singapore DOI: 10.1109/ICMTS.2017.7954268 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 4.1 | Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI K. Pradeep, G. Gouget1, T. Poiroux2, P. Scheer3, A. Juge3, G. Ghibaudo IMEP-LAHC, MINATEC Campus, Grenoble, Cedex 1, France 1STMicroelectronics, Crolles, FR 2CEA-Leti, MINATEC Campus, Grenoble Cedex 9, France 3STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2017.7954267 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 3.4 | Ring-oscillator test-structures for sub-0.1% accuracy wafer-level characterization of active- and standby current consumption, variability, and fast aging of oscillation frequencies M. Vertregt, H. Tuinhout, N. Wils, A. Zegers, J. Croon NXP Semiconductors High Tech Campus, The Netherlands DOI: 10.1109/ICMTS.2017.7954266 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 3.3 | Vth-shiftable SRAM cell TEGs for direct measurement for the immunity of the threshold voltage variability S. Yamaguchi, H. Imi, S. Tokumaru, T. Kondo, H. Yamamoto, K. Nakamura Center for Microelectronic Systems, Kyushu Institute of Technology, Fukuoka, Japan DOI: 10.1109/ICMTS.2017.7954265 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 3.2 | Measurement of mismatch factor and noise of SRAM PUF using small bias voltage Ziyang Cui, Baikun Zheng, Yanhao Piao, Shiyu Liu, Ronghao Xie, H. Shinohara Graduate School of Information, Production and Systems, Waseda University, Fukuoka, Japan DOI: 10.1109/ICMTS.2017.7954264 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 3.1 | Statistical characterization and modeling of drain current local and global variability in 14 nm bulk FinFETs T. Karatsori, C. Theodorou, R. Lavieville, T. Chiarella1, J. Mitard1, N. Horiguchi1, C. A. Dimitriadis2, G. Ghibaudo IMEP-LAHC, Univ. Grenoble Alpes, Minatec, Grenoble, France 1IMEC, Leuven, Belgium 2Department of Physics, Aristotle University of Thessaloniki, Greece DOI: 10.1109/ICMTS.2017.7954263 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 2.4 | Test structures for understanding the impact of ultra-high vacuum metal deposition on top-gate MoS2 field-effect-transistors P. Bolshakov, P. Zhao, C. M. Smyth, A. Azcatl, R. M. Wallace, C. D. Young, P. K. Hurley1 Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX, USA 1Tyndall National Institute, University College Cork, Dyke Parade, Cork, Ireland DOI: 10.1109/ICMTS.2017.7954262 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 2.3 | Electromechanical testing of ZnO thin films under high uniaxial strain R. Tuyaerts, J. -P. Raskin1, J. Proost Universite catholique de Louvain, Louvain-la-Neuve, BE 1Institute of Information and Communication Technologies, Universit catholique de Louvain, Louvain-la-Neuve, Belgium DOI: 10.1109/ICMTS.2017.7954261 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 2.2 | The outstanding properties of graphene-insulator-semiconductor (GIS) test structures for photoelectric determination of semiconductor devices band diagram K. Piskorski, V. Passi1, J. Ruhkopf1, M. C. Lemme1, H. M. Przewlocki Institute of Electron Technology, Warsaw, Poland 1University of Siegen, Siegen, Germany DOI: 10.1109/ICMTS.2017.7954260 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 2.1 | Detailed characterization and critical discussion of series resistance in graphene-metal contacts S. Venica, F. Driussi1, A. Gahoi, V. Passi, P. Palestri1, M. C. Lemme, L. Selmi1 University of Siegen, School of Science and Technology, Siegen, Germany 1Universitä¡ degli Studi di Udine, Dipartimento Politecnico di Ingegneria e Architettura (DPIA), Udine, Italy DOI: 10.1109/ICMTS.2017.7954259 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 1.4 | Electrical test structures for verifying continuity of ultra-thin insulating and conducting films S. Banerjee, R. van der Velde, M. Yang, J. Schmitz, A. Y. Kovalgin1 MESA+ Institute for Nanotechnology, University of Twente, Enschede, AE, The Netherlands 1Universiteit Twente, Enschede, Overijssel, NL DOI: 10.1109/ICMTS.2017.7954258 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 1.3 | Dealing with leakage current in TLM and CTLM structures with vertical junction isolation S. N. Bystrova, S. M. Smits, J. H. Klootwijk1, R. A. M. Wolters, A. Y. Kovalgin, L. K. Nanver2, J. Schmitz MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands 1Philips Research, Enschede, The Netherlands 2Aalborg University, Aalborg, Denmark DOI: 10.1109/ICMTS.2017.7954257 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 1.2 | Test structures for studying flexible interconnect supported by carbon nanotube scaffolds D. Jiang, S. Sun, M. Edwards, K. Jeppson Department of Microtechnology and Nanoscience, Electronics Materials and Systems Laboratory, Gothenburg, Sweden DOI: 10.1109/ICMTS.2017.7954256 HOVER FOR ABSTRACT | PDF Xplore |
| 2017 | 1.1 | Characterization and monitoring structures for robustness against cyclic thermomechanical stress: Design and influence of Ti-Al(Cu) layer scheme A. Mann, H. Lohmeyer, Y. Joseph1 Robert Bosch GmbH Automotive Electronics, Reutlingen, Germany 1Technische Universität Bergakademie Freiberg, Institute of Electronic and Sensor Materials, Freiberg, Germany DOI: 10.1109/ICMTS.2017.7954255 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 10.4 | A reliable Schottky barrier height extraction procedure B. -Y. Tsui, T. -Y. Fu Department of Electronics Engineering & Institute of Electronics, National Chiao-Tung University ED641, Hsinchu, Taiwan, R. O. C DOI: 10.1109/ICMTS.2016.7476206 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 10.3 | Comparing current flows in ultrashallow pn-/Schottky-like diodes with 2-diode test method X. Liu, L. K. Nanver Semiconductor Components, University of Twente, Enschede, the Netherlands DOI: 10.1109/ICMTS.2016.7476205 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 10.2 | Test structures for the characterisation of conductive carbon produced from photoresist S. Scarfì, S. Smith1, A. Tabasnikov, I. Schmüser, E. Blair, A. S. Bunting, A. J. Walton, A. F. Murray1, J. G. Terry Institute for Integrated Micro and Nano Systems, The University of Edinburgh, Edinburgh, EH9 3FF 1Institute for Biomedical Engineering, The University of Edinburgh, Edinburgh, EH9 3FF DOI: 10.1109/ICMTS.2016.7476204 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 10.1 | Chip level characterisation studies of Ni and NiFe electrochemical deposition using test structures J. Murray, R. Perry, J. G. Terry, S. Smith, A. R. Mount, A. J. Walton The University of Edinburgh, Edinburgh, Edinburgh, GB DOI: 10.1109/ICMTS.2016.7476203 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 9.4 | Top-gated MoS2 capacitors and transistors with high-k dielectrics for interface study P. Zhao, A. Azcatl, P. Bolshakov-Barrett, R. M. Wallace, C. D. Young, P. K. Hurley1 Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX, USA 1University of College Cork, Tyndall National Institute, Cork, Ireland DOI: 10.1109/ICMTS.2016.7476201 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 9.3 | Novel test structure for evaluating dynamic dopant activation after ion implantation J. -R. Tsai, R. -D. Chang1, C. -H. Chou1, H. -C. Liao1, S. -K. Huang1, S. -H. Lin1, J. -C. Lin1 Department of Photonics and Communication Engineering, Asia University 500, Taiwan, R. O. C. 1Department of Electronic Engineering, Chang Gung University, Taiwan, R. O. C. DOI: 10.1109/ICMTS.2016.7476200 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 9.2 | Interface trap density estimation in FinFETs from the subthreshold current J. Schmitz, B. Kaleli1, P. Kuipers, N. van den Berg2, S. M. Smits, R. J. E. Hueting MESA+ Institute for Nanotechnology, University of Twente, Enschede, The Netherlands 1ASML, Veldhoven, The Netherlands 2Micronit Microftuidics, Enschede, The Netherlands DOI: 10.1109/ICMTS.2016.7476199 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 9.1 | Test structures to support the development and process verification of microelectrodes for high temperature operation in molten salts E. O. Blair, D. K. Corrigan1, I. Schmueser, J. G. Terry, S. Smith, A. R. Mount1, A. J. Walton SMC, The University of Edinburgh, Edinburgh, UK 1EASTCHEM, The University of Edinburgh, Edinburgh, Scotland, UK DOI: 10.1109/ICMTS.2016.7476198 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 8.4 | Impact of a laser pulse on HfO2-based RRAM cells reliability and integrity A. Krakovinsky, M. Bocquet, R. Wacquez1, J. Coignus1, D. Deleruyelle, C. Djaou, G. Reimbold1, J. -M. Portal CEA - DRT/DPACA, Laboratoire SAS, Centre de Microelectronique de Provence 1IM2NP - UMR CNRS 7334, Aix-Marseille Université, France DOI: 10.1109/ICMTS.2016.7476196 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 8.3 | Ultra-small and ultra-reliable innovative fuses scalable from 0.35um to 28nm S. Chung, W. -K. Fang, Y. Hsu, J. Hsiao, L. Lin, W. -H. Yu Attopsemi Technology Co.,LTD, Hsinchu, Taiwan, R.O.C DOI: 10.1109/ICMTS.2016.7476195 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 8.2 | Challenges of modeling the Split-Gate SuperFlash® Memory Cell with 1.1V Select Transistor M. Tadayoni, S. Martinie1, O. Rozeau1, S. Hariharan, C. Raynaud1, N. Do Silicon Storage Technology, Inc., A subsidiary of Microchip Technology Inc., San Jose, CA, USA 1CEA-LETI, Grenoble, France DOI: 10.1109/ICMTS.2016.7476194 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 8.1 | New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM Y. Shuto, S. Yamamoto, S. Sugahara Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, Yokohama, Japan DOI: 10.1109/ICMTS.2016.7476193 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 7.3 | Measurement of SRAM power-up state for PUF applications using an addressable SRAM cell array test structure K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto, H. Shinohara1 Institute of Industrial Science, University of Tokyo, Tokyo, Japan 1Graduate School of Information, Production and Systems Waseda University, Fukuoka, Japan DOI: 10.1109/ICMTS.2016.7476191 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 7.2 | A new write stability metric using extended write butterfly curve for yield estimation in SRAM cells at low supply voltage H. Qiu, K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476190 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 7.1 | Test circuits to characterize setup/hold/access times, minimum voltage and maximum frequency of operation for memory compilers N. Dhamija, G. Lalani, M. Nelson1, J. Brown1, H. Spruth1, P. Sharma Freescale Semiconductor, NOIDA, INDIA 1Freescale Semiconductor, Austin, TX, USA DOI: 10.1109/ICMTS.2016.7476189 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 6.3 | Demonstration of MOS capacitor measurement for wafer manufacturing using a Direct Charge Measurement K. Takano, M. Goto, E. Shiling1, A. Gasasira2, J. -H. Liao2 Keysight Technologies International Japan, Hachioji-shi, Tokyo, Japan 1Keysight Technologies, Santa Rosa, CA, USA 2GLOBALFOUNDRIES, NY, USA DOI: 10.1109/ICMTS.2016.7476187 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 6.2 | Extraction of floating-gate capacitive parameters in split-gate flash memory cells Y. Tkachev Silicon Storage Technology Inc., Microchip Technology, Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2016.7476186 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 6.1 | Highly effective and versatile test structure for evaluating dielectric properties using flexible pulse generator on chip S. Mori, K. Sawada, M. Tomita, K. Ogawa, T. Suzuki, H. Oishi, M. Bairo, Y. Fukuzaki, H. Ohnuma Sony Corporation, Atsugi-shi, Japan DOI: 10.1109/ICMTS.2016.7476185 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 5.3 | Test structures of LASCR device for RF ESD protection in nanoscale CMOS process C. -Y. Lin, R. -K. Chang Department of Electrical Engineering, National Taiwan Normal University, Taiwan DOI: 10.1109/ICMTS.2016.7476183 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 5.2 | A test structure set for on-wafer 3D-TRL calibration M. Potéreau, A. Curutchet, R. D'Esposito, M. De Matos, S. Fregonese, T. Zimmer IMS-Lab University of Bordeaux, Talence, France DOI: 10.1109/ICMTS.2016.7476182 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 5.1 | A high power curve tracer for characterizing full operational range of SiC power transistors Y. Nakamura, M. Shintani1, T. Sato1, T. Hikihara Graduate School of Engineering, Kyoto University, Kyoto, Japan 1Graduate School of Informatics, Kyoto University, Kyoto, Japan DOI: 10.1109/ICMTS.2016.7476181 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 4.3 | Statistical analysis and modeling of Random Telegraph Noise based on gate delay variation measurement A. K. M. Mahfuzul Islam, T. Nakai1, H. Onodera2 Institute of Industrial Science, The University of Tokyo 1Graduate School of Informatics, Kyoto University 2JST, CREST DOI: 10.1109/ICMTS.2016.7476179 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 4.2 | Test structures for CMOS RF reliability assessment L. Heiß, A. Lachmann1, R. Schwab1, G. Panagopoulos1, P. Baumgartner1, M. Y. Virupakshappaa1, D. Schmitt-Landsiedel2 Technische Universitat Munchen, Munchen, Bayern, DE 1Intel Deutschland GmbH, Neubiberg, Germany 2Technical University of Munich (TUM), Munich, Germany DOI: 10.1109/ICMTS.2016.7476178 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 4.1 | New access resistance extraction methodology for 14nm FD-SOI technology J. -B. Henry, A. Cros, J. Rosa, Q. Rafhay1, G. Ghibaudo1 STMicroelectronics, Crolles Site, TR&D/STD/TPS/SiRel, Crolles, France 1IMEP-LAHC, MINATEC Campus, Grenoble, France DOI: 10.1109/ICMTS.2016.7476177 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 3.4 | Design and use of an array-based test structure to characterize mechanical stress effects caused by WLCSP solder bumps H. Tuinhout, R. van Dalen1 NXP Semiconductors - Technology & Operations, FEI - Modeling, Netherlands 1Now with Ampleon, Netherlands DOI: 10.1109/ICMTS.2016.7476175 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 3.3 | Advanced ioff measureable MOSFET array with eliminating leakage current of peripheral circuits T. Suzuki, S. Mori, H. Oishi, M. Bairo, M. Tomita, K. Ogawa, Y. Fukuzaki, H. Ohnuma Sony Corporation, Atsugi-shi, Kanagawa, Japan DOI: 10.1109/ICMTS.2016.7476174 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 3.2 | Proposal of a new array structure to enable the detection of soft failure and the aging test with overcurrent of resistive element S. Sato, Y. Omura Faculty of Engineering Science, Kansai University, Osaka, Japan DOI: 10.1109/ICMTS.2016.7476173 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 3.1 | Random telegraph noise measurement and analysis based on arrayed test circuit toward high S/N CMOS image sensors R. Kuroda, A. Teramoto1, S. Sugawa1 Graduate School of Engineering, Tohoku University, Sendai, Japan 1New Industry Creation Hatchery Center, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS.2016.7476172 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 2.4 | Transistor self-heating correction and thermal conductance extraction using only DC data C. C. McAndrew, A. Lorenzo-Cassagnes, O. L. Hartin1 NXP Semiconductors, Tempe, AZ 1Arizona State University, Tempe, AZ DOI: 10.1109/ICMTS.2016.7476170 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 2.3 | Hotspot test structures for evaluating carbon nanotube microfin coolers and graphene-like heat spreaders K. Jeppson, J. Bao1, S. Huang1, Y. Zhang, S. Sun, Y. Fu2, J. Liu Chalmers University of Technology, Gothenburg, Sweden 1Chalmers University of Technology, SHT Smart High Tech, Gothenburg, Sweden 2Shanghai University SMIT Center, Jiading Campus, Shanghai, China DOI: 10.1109/ICMTS.2016.7476169 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 2.2 | Dedicated test-structures for investigation of the thermal impact of the BEOL in advanced SiGe HBTs in time and frequency domain R. D'Esposito, S. Fregonese, T. Zimmer, A. Chakravorty1 CNRS-UMR 5218, Université de Bordeaux 1Department of Electrical Engineering, IIT Madras, Chennai, India DOI: 10.1109/ICMTS.2016.7476168 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 2.1 | A test structure for analysis of metal wire effect on temperature distribution in stacked IC T. Matsuda, H. Demachi, H. Iwata, T. Hatakeyama, T. Ohzone1 Toyama Prefectural University, Toyama, Japan 1Dawn Enterprise, Nagoya, Japan DOI: 10.1109/ICMTS.2016.7476167 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 1.4 | Microfabricated test structures for thermal gas sensor M. Denoual, M. Pouliquen, D. Robbes, O. de Sagazan1, J. Grand1, H. Awala1, S. Mintova2, S. Inoue3, A. Mita-Tixier3, Y. Mita3 GREYC-CNRS, ENSICAEN, France 1LCS-CNRS, University of Caen, France 2IETR, University of Rennes, France 3Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476165 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 1.3 | Spring-constant measurement methods for RF-MEMS capacitive switches J. Wang, J. Bielen1, C. Salm, J. Schmitz The MESA+ Institute for Nanotechnology, University of Twente, Netherlands 1EPCOS Netherlands, Netherlands DOI: 10.1109/ICMTS.2016.7476164 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 1.2 | An end-point visualization test structure for all plasma dry release of Deep-RIE MEMS Y. Okamoto, E. Lebrasseur, I. Mori, Y. Mita Department of Electrical Engineering The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476163 HOVER FOR ABSTRACT | PDF Xplore |
| 2016 | 1.1 | An efficient method to evaluate 4 million micro-bump interconnection resistances for 3D stacked 16-mpixel image sensor Y. Takemoto, H. Kato, T. Kondo, N. Takazawa, M. Tsukimura, H. Saito, K. Kobayashi, J. Aoki, S. Suzuki, Y. Gomi, S. Matsuda, Y. Tadaki Imager and Analog LSI technology Department, Olympus Corporation, Hachioji-shi, Tokyo, Japan DOI: 10.1109/ICMTS.2016.7476162 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 10.4 | Electromagnetic field test structure chip for back end of the line metrology L. You, J. -J. Ahn, E. Hitz, J. Michelson, Y. Obeng, J. Kopanski Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2015.7106101 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 10.3 | Systematic calibration procedure of process parameters for electromagnetic field analysis of millimeter-wave CMOS devices K. Takano, K. Katayama, S. Mizukusa, S. Amakawa, T. Yoshida, M. Fujishima Hiroshima University, Graduate School of Advanced Sciences of Matter, Higashihiroshima, Hiroshima, Japan DOI: 10.1109/ICMTS.2015.7106100 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 10.2 | Observations on substrate characterisation through Coplanar Transmission Line Impedance measurements L. Floyd, J. Pike, J. Tao, N. Jackson1 Tyndall National Institute, Cork, Ireland 1Tyndall National Institute, Cork, IE DOI: 10.1109/ICMTS.2015.7106099 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 10.1 | Characterization of wideband decoupling power line with extremely low characteristic impedance for millimeter-wave CMOS circuits R. Goda, S. Amakawa, K. Katayama, K. Takano, T. Yoshida, M. Fujishima Graduate School of Advanced Sciences of Matter Hiroshima University 1-3-1 Kagamiyama Higashihiroshima, Japan DOI: 10.1109/ICMTS.2015.7106098 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 9.4 | Sensitivity-independent extraction of Vth variation utilizing log-normal delay distribution A. K. M. Mahfuzul Islam, H. Onodera Graduate School of Informatics, Kyoto University, Sakyo-ku, Kyoto, Japan DOI: 10.1109/ICMTS.2015.7106155 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 9.3 | Reduction of overhead in adaptive body bias technology due to triple-well structure based on measurement and simulation Y. Ogasahara, T. Sekigawa, M. Hioki, T. Nakagawa, T. Tsutsumi, H. Koike National Institute of Advanced Industrial Science and Technology(AIST), Tsukuba, Japan DOI: 10.1109/ICMTS.2015.7106154 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 9.2 | Test circuit for accurate measurement of setup/hold and access time of memories N. Agarwal Physical Design Group ARM Embedded Technologies Pvt. Ltd., Bangalore, India DOI: 10.1109/ICMTS.2015.7106153 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 9.1 | Silicon measurements of characteristics for passgate/pull-down/pull-up MOSs and search MOS in a 28 nm HKMG TCAM bitcell K. Nii, K. Yamaguchi, M. Yabuuchi, N. Watanabe, T. Hasegawa, S. Yoshida, T. Okagaki, M. Yokota, K. Onozawa Renesas Electronics Corporation, Tokyo, Japan DOI: 10.1109/ICMTS.2015.7106140 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 8.3 | A capacitive based piezoelectric AlN film quality test structure N. Jackson, O. Z. Olszewski, L. Keeney, A. Blake, A. Mathewson Tyndall National Institute, University College Cork Lee Maltings, Prospect Row, Cork, Ireland DOI: 10.1109/ICMTS.2015.7106139 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 8.2 | A fully-automated methodology and system for printed electronics foil characterization F. Vila, J. Pallarès, A. Conde, L. Terés IMB-CNM (CSIC) Cerdanyola del Vallès, Barcelona, Spain DOI: 10.1109/ICMTS.2015.7106138 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 8.1 | Test structures for the wafer mapping and correlation of electrical, mechanical and high frequency magnetic properties of electroplated ferromagnetic alloy films E. Sirotkin, S. Smith, R. Walker, J. G. Terry, A. J. Walton Scottish Microelectronics Centre, University of Edinburgh, United Kingdom DOI: 10.1109/ICMTS.2015.7106137 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 7.5 | Combined transmission line measurement structures to study thin film resistive sensor fabrication A. Tabasnikov, A. J. Walton, S. Smith Institute for Integrated Micro and Nano Systems, The niversity of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2015.7106136 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 7.4 | Sheet resistance measurement for process monitoring of 400 °C PureB deposition on Si L. Qi, L. K. Nanver Delft University of Technology, Delft, The Netherlands DOI: 10.1109/ICMTS.2015.7106135 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 7.3 | Novel sheet resistance measurement on AlGaN/GaN HEMT wafer adapted from four-point probe technique J. Lehmann, C. Leroux, G. Reimbold, M. Charles, A. Torres, E. Morvan, Y. Baines, G. Ghibaudo1, E. Bano1 Univcrsité Grenoble Alpes, Grenoble, cedex, France 1IMEP-LAHC, Grenoble cedex 1 DOI: 10.1109/ICMTS.2015.7106134 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 7.2 | Characterization of recessed Ohmic contacts to AlGaN/GaN M. Hajlasz, J. J. T. M. Donkers1, S. J. Sque1, S. B. S. Heil1, D. J. Gravesteijn1, F. J. R. Rietveld2, J. Schmitz3 Materials innovation institute (M2i), Delft, The Netherlands 1NXP Semiconductors Research, Eindhoven, The Netherlands 2NXP Semiconductors, Nijmezen, The Netherlands 3Universiteit Twente, Enschede, Overijssel, NL DOI: 10.1109/ICMTS.2015.7106133 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 7.1 | Design and evaluation of an integrated thin film resistor matching test structure H. Tuinhout, N. Wils, P. Huiskamp, E. de Koning NXP Semiconductors - Technology & Operations, Integrated Technology Platforms Eindhoven & Nijmegen, the Netherlands DOI: 10.1109/ICMTS.2015.7106127 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 6.4 | In-line monitoring test structure for Charge-Based Capacitance Measurement (CBCM) with a start-stop self-pulsing circuit K. Sawada, G. Van der Plas1, S. Mori, C. Vladimir1, A. Mercha1, V. Diederik1, Y. Fukuzaki, H. Ammo Sony Corporation, Atsugi-shi, Kanagawa, Japan 1IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.2015.7106126 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 6.3 | Area and performance study of FinFET with detailed parasitic capacitance analysis in 16nm process node T. Okagaki, K. Shibutani, H. Matsushita, H. Ojiro, M. Morimoto, Y. Tsukamoto, K. Nii, K. Onozawa Renesas Electronics Corp, Tokyo, Japan DOI: 10.1109/ICMTS.2015.7106125 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 6.2 | A novel new gate charge measurement method A. Mikata, H. Kakitani, R. Takeda, A. Wadsworth Keysight Technologies, Hachioji-shi, Tokyo, Japan DOI: 10.1109/ICMTS.2015.7106124 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 6.1 | Monitoring test structure for plasma process induced charging damage using charge-based capacitance measurement (PID-CBCM) S. Mori, K. Ogawa, H. Oishi, T. Suzuki, M. Tomita, M. Bairo, Y. Fukuzaki, H. Ohnuma Sony Corporation, Kanagawa, Japan DOI: 10.1109/ICMTS.2015.7106123 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 5.4 | Measurement of Vth variation due to STI stress and inverse narrow channel effect at ultra-low voltage in a variability-suppressed process Y. Ogasahara, M. Hioki, T. Nakagawa, T. Sekigawa, T. Tsutsumi, H. Koike Industrial Science and Technology(AIST), National Institute of Advanced, Tsukuba, Japan DOI: 10.1109/ICMTS.2015.7106122 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 5.3 | Threshold voltage extraction method in field-effect devices with power-law dependence of mobility on carrier density V. Mosser, D. Seron1, Y. Haddab ITRON SAS, Issy Technology Center 1Itron SAS, Malakoff, FR DOI: 10.1109/ICMTS.2015.7106121 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 5.2 | A simple method for characterization of MOSFET serial resistance asymmetry D. Tomaszewski, G. Głuszko, J. Malesińska, K. Domański, M. Zaborowski, K. Kucharski, D. Szmigiel, A. Sierakowski Instytut Technologii Elektronowej (ITE), Warsaw, Poland DOI: 10.1109/ICMTS.2015.7106120 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 5.1 | Compact modeling solution of layout dependent effect for FinFET technology D. C. Chen, G. S. Lin, T. H. Lee, R. Lee1, Y. C. Liu, M. F. Wang, Y. C. Cheng, D. Y. Wu Advanced Technology Development Division, United Microelectronics Corporation (UMC), Hsin-Chu City, Taiwan ROC 1Advanced Technology Development Division, United Microelectronics Corporation (UMC) DOI: 10.1109/ICMTS.2015.7106119 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 4.9 | NPN CML ring oscillators for model verification and process monitoring C. Compton MACOM, Newport Beach, CA, USA DOI: 10.1109/ICMTS.2015.7106118 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 4.8 | Cross-correlation of electrical measurements via physics-based device simulations: Linking electrical and structural characteristics A. Padovani, L. Larcher, L. Vandelli, M. Bertocchi1, R. Cavicchioli1, D. Veksler2, G. Bersuker3 MDLab s.r.i., Saint Christophe, Aosta, AO, Italy 1DISMI University of Modena and Reggio Emilia, Reggio Emilia, RE, Italy 2SEMATECH, Albany, NY, USA 3NA DOI: 10.1109/ICMTS.2015.7106117 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 4.7 | Elastic instabilities induced large surface strain sensing structures (EILS) Y. Li, J. G. Terry1, S. Smith1, A. J. Walton1, G. McHale, B. Xu Faculty of Engineering and Environment, Northumbria University, Newcastle upon Tyne, UK 1SMC Institute for Integrated Micro and Nano Systems School of Engineering, The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2015.7106116 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 4.6 | Measurement and modeling of IC self-heating including cooling system properties T. Nishimura, H. Tanoue, Y. Oodate, H. J. Mattausch, M. Miura-Mattausch Graduate School of Advanced Science of Matter, Hiroshima University, Higashi-Hiroshima, Japan DOI: 10.1109/ICMTS.2015.7106115 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 4.5 | A test structure for reliability analysis of CMOS devices under DC and high frequency AC stress T. Matsuda, K. Ichihashi, H. Iwata, T. Ohzone1 Department of Information Systems Engineering, Toyama Prefectural University 1Dawn Enteprise, Nagoya, Japan DOI: 10.1109/ICMTS.2015.7106114 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 4.3 | The impact of deep trench and well proximity on MOSFET performance H. Sheng, T. Bettinger, J. Bates Freescale Semiconductor Inc., Tempe, AZ, USA DOI: 10.1109/ICMTS.2015.7106113 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 4.2 | Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via H. Shinkawata, N. Tsuboi, A. Tsuda1, S. Sato2, Y. Yamaguchi Renesas Electronics Corporation, Production and Technology Unit, Hitachinaka-shi, Ibaraki-ken, Japan 1Renesas System Design Corporation, Tokyo, Japan 2Kansai University, Suita, Osaka, Japan DOI: 10.1109/ICMTS.2015.7106112 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 4.1 | A proposal for early warning indicators to detect impending metallization failure of DMOS transistors in cyclic operation M. Ritter, M. Pfost Robert Bosch Center for Power Electronics, Reutlingen University Alteburgstr. 150, Reutlingen, Germany DOI: 10.1109/ICMTS.2015.7106097 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 4.1 | A test structure for characterizing the cleanliness of glass beads using low-frequency dielectric spectroscopy M. Buehler Decagon Devices, Inc., WA DOI: 10.1109/ICMTS.2015.7106111 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 3.5 | Silicon thickness monitoring strategy for FD-SOI 28nm technology A. Cros, F. Monsieur, Y. Carminati, P. Normandon, D. Petit, F. Arnaud, J. Rosa STMicroelectronics, Crolles Site, Crolles, France DOI: 10.1109/ICMTS.2015.7106110 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 3.4 | New compact model for performance and process variability assessment in 14nm FDSOI CMOS technology Y. Denis, F. Monsieur, G. Ghibaudo1, J. Mazurier, E. Josse, D. Rideau, C. Charbuillet, C. Tavernier, H. Jaouen STMicroelwknectronics, FR, Crolles 1IMEP-LAHC, Grenoble Cedex DOI: 10.1109/ICMTS.2015.7106109 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 3.3 | Robust process capability index tracking for process qualification C. Gu, C. C. McAndrew Freescale Semiconductor, Tempe, AZ DOI: 10.1109/ICMTS.2015.7106108 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 3.2 | Employing an on-die test chip for maximizing parametric yields of 28nm parts J. Mueller, S. Jallepalli, R. Mooraka, S. Hector Freescale Semiconductor, Austin, Tx, USA DOI: 10.1109/ICMTS.2015.7106107 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 3.1 | Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy G. Moore, J. -H. Liao, S. McDade1, B. Verzi1 IBM Microelectronics, NY, USA 1Keysight Technologies, Burlington, VT, USA DOI: 10.1109/ICMTS.2015.7106106 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 2.4 | A four-terminal JFET compact model for high-voltage power applications W. Wu, S. Banerjee, K. Joardar Texas Instruments, Dallas, TX DOI: 10.1109/ICMTS.2015.7106105 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 2.3 | Modeling of T-model equivalent circuit for spiral inductors in 90 nm CMOS technology J. -W. Jeong, S. -K. Kwon, J. -N. Yu, S. -Y. Jang, S. -H. Oh, C. -Y. Kim1, G. -w. Lee, H. -D. Lee Department of Electronics Engineering, Chungnam National Univ., Yuseong, Daejeon, Korea 1Department of Electronics Engineering, Chungnam National University, Daejeon, Daejeon, KR DOI: 10.1109/ICMTS.2015.7106104 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 2.2 | Compact modeling and parameter extraction strategy of normally-on MOSFET T. Umeda, Y. Hirano, D. Suzuki, A. Tone, T. Inoue, H. Kikuchihara, M. Miura-Mattausch, H. J. Mattausch Graduate School of Advanced Sciences of Matter Hiroshima University 1-3-1 Kagamiyama, Higashi-Hiroshima Hiroshima, Japan DOI: 10.1109/ICMTS.2015.7106103 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 2.1 | SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells S. Martinie, O. Rozeau, M. Tadayoni1, C. Raynaud, E. Nowak, S. Hariharan2, N. Do2 CEA-LETI, Grenoble, Cedex 9, France 1Silicon Storage Technology Inc, Sunnyvale, CA, US 2Silicon Storage Technology Inc., Microchip Technology Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2015.7106102 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 1.3 | Circuit architecture and measurement technique to reduce the leakage current stemming from peripheral circuits with an array structure in examining the resistive element S. Sato, T. Ito, Y. Omura Kansai University, Suita, Osaka, Japan DOI: 10.1109/ICMTS.2015.7106096 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 1.2 | A novel structure of MOSFET array to measure ioff-ion with high accuracy and high density T. Suzuki, A. Anchlia1, V. Cherman2, H. Oishi, S. Mori, J. Ryckaert2, K. Ogawa, G. Van der Plas2, E. Beyne2, Y. Fukuzaki, D. Verkest2, H. Ohnuma Sony Corporation, Kanagawa, Japan 1imec vzw (currently working for XENICS corporation) 2imec vzw, Kapeldreef75, Belgium DOI: 10.1109/ICMTS.2015.7106095 HOVER FOR ABSTRACT | PDF Xplore |
| 2015 | 1.1 | 14nm BEOL TDDB reliability testing and defect analysis T. Kane IBM Systems Technology Group/Microelectronics Division DOI: 10.1109/ICMTS.2015.7106094 HOVER FOR ABSTRACT | PDF Xplore |
| 2014 | Statistical analysis of resistive switching characteristics in ReRAM test arrays C. Zambelli, A. Grossi, P. Olivo, D. Walczyk1, T. Bertaud1, B. Tillack1, T. Schroeder2, V. Stikanov3, C. Walczyk1 Dipartimento di Ingegneria, Università degli Studi di Ferrara, Ferrara, Italy 1IHP Microelectronics, Frankfurt (Oder), Germany 2Brandenburgische Technische Universität, Cottbus, Germany 3IASA, Kiev, Ukraine DOI: 10.1109/ICMTS.2014.6841463 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Processor yield at 14nm and beyond G. Yeric Research and Development, ARM Austin, TX, USA DOI: 10.1109/ICMTS.2014.6841477 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | 3D IC testing using a chip prober and a transparent membrane probe card N. Watanabe, M. Aoyagi, M. Eto1, K. Kawano1 Nano-electronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba-shi, Ibaraki, Japan 1STK TECHNOLOGY CO., LTD., Oita-shi, Oita, Japan DOI: 10.1109/ICMTS.2014.6841474 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Effect of seed layers on the performance of planar spiral microinductors R. Walker, E. Sirotkin, J. G. Terry, S. Smith, M. P. Y. Desmulliez1, A. J. Walton Institute of Integrated Micro and Nano Systems, The University of Edinburgh, UK 1Heriot-Watt University, Edinburgh, Edinburgh, GB DOI: 10.1109/ICMTS.2014.6841481 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Characterisation of residual stress in dielectric films studied by automated wafer mapping R. Walker, E. Sirotkin, G. Schiavone, J. G. Terry, S. Smith, A. R. Mount1, M. P. Y. Desmulliez2, A. J. Walton Institute of Integrated Micro and Nano Systems, The University of Edinburgh, UK 1School of Chemistry, The University of Edinburgh, UK 2MIcroSystems Engineering Centre, Heriot-Watt University, Edinburgh, UK DOI: 10.1109/ICMTS.2014.6841475 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Calibration methods for silicon nanowire BioFETs A. Vacic, J. M. Criscione, E. Stern, N. K. Rajan1, T. Fahmy, M. A. Reed1 Yale University, New Haven, CT, US 1Yale University, New Haven, CT, USA DOI: 10.1109/ICMTS.2014.6841493 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | A cross-coupled common centroid test structures layout method for high precision MIM capacitor mismatch measurements H. Tuinhout, N. Wils NXP Semiconductors - Central R&D, Design Platforms Organization, High Tech Campus Eindhoven, the Netherlands DOI: 10.1109/ICMTS.2014.6841500 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Comparison of channel length extracted from gate capacitance with that extracted from channel resistance K. Tsuji, K. Terada Faculty of Information Sciences, Hiroshima City University, Hiroshima, JAPAN DOI: 10.1109/ICMTS.2014.6841473 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Evaluation of ultra-low specific contact resistance extraction by cross-bridge Kelvin resistor structure and transmission line method structure B. -Y. Tsui, H. -T. Tseng Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan R. O. C DOI: 10.1109/ICMTS.2014.6841468 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | A novel compact model of the product marginal yield and its application for performance maximization A. Tsuda, T. Okagaki, M. Fujii, T. Tsutsui, Y. Takazawa, K. Shibutani, S. Ogasawara, M. Yokota, K. Onozawa Device Platform Dep, Renesas Electronics Corporation, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.2014.6841478 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Compressively-stressed test structures for opaque micro-stmctures releasing visualization A. Tixier-Mita, E. Lebrasseur, T. Takahashi, Y. Mita1, H. Fujita1, H. Toshiyoshi2, F. Olivier2, L. P. Bruno2 The University of Tokyo, Tokyo, Japan 1Tokyo Daigaku, Bunkyo-ku, Tokyo, JP 2Departernent SATIE/IFR, Ecole Nationale Supérieure Cachan, France DOI: 10.1109/ICMTS.2014.6841488 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Reconsideration of effective MOSFET channel length extracted from channel resistance K. Terada Faculty of Information Sciences, Hiroshima City University, Hiroshima, JAPAN DOI: 10.1109/ICMTS.2014.6841459 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Test structure for electrical characterization of copper nanowire anisotropic conductive film (NW-ACF) for 3D stacking applications J. Tao, A. Mathewson, K. M. Razeeb Microsystems Center, Tyndall National Institute, Cork, Ireland DOI: 10.1109/ICMTS.2014.6841487 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Understanding the switching mechanism of charge-injection GeTe/Sb2Te3 phase change memory through electrical measurement and analysis of 1R test structure N. Takaura, T. Ohyanagi, M. Tai, M. Kitamura, M. Kinoshita, K. Akita, T. Morikawa, S. Kato1, M. Araidai1, K. Kamiya1, T. Yamamoto1, K. Shiraishi1 Phase Change Device Research Group, Low-power Electronics Association & Project (LEAP), Tsukuba, Ibaraki, Japan 1Graduate School of Pure and Applied Sciences, University of Tsukuba, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2014.6841464 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Characterization and development of materials for an integrated high-temperature sensor using resistive test structures A. Tabasnikov, A. S. Bunting, J. G. Terry, J. Murray, G. Cummins1, C. Zhao2, J. Zhou2, R. Y. Fu2, M. P. Y. Desmulliez1, A. J. Walton, S. Smith Institute for Integrated Micro and Nano Systems, The University of Edinburgh, Edinburgh, UK 1School of Engineering and Physical Sciences, Heriot-Watt University, Edinburgh, UK 2School of Engineering, University of the West of Scotland, Paisley, UK DOI: 10.1109/ICMTS.2014.6841491 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Extraction procedure for emitter series resistance contributions in SiGeC BiCMOS technologies F. Stein, Z. Huszka1, N. Derrier2, C. Maneux, D. Celi2 IMS, Université Bordeaux I, Talence, France 1AMS AG, Unterpremstatten, Austria 2STMicroelectronics, France DOI: 10.1109/ICMTS.2014.6841462 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Test structure to evaluate the impact of neighboring features on stress of metal interconnects B. Smith, M. Shroff Freescale Semiconductor, Inc., Austin, TX DOI: 10.1109/ICMTS.2014.6841495 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Air-CPW test structure for broadband permeability spectra measurements of thin ferromagnetic films E. Sirotkin, R. Walker, J. G. Terry, S. Smith, A. J. Walton Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2014.6841489 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Cascode configuration as a substitute to LDE MOSFET for improved electrical mismatch performance L. Rahhal, G. Bertrand1, A. Bajolet1, J. Rosa1, G. Ghibaudo IMEP-LAHC, Grenoble, France 1STMicroelectronics, France DOI: 10.1109/ICMTS.2014.6841499 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Split-CV for pseudo-MOSFET characterization: Experimental setups and associated parameter extraction methods L. Pirro, I. Ionica, G. Ghibaudo, S. Cristoloveanu IMEP-LAHC Grenoble, France DOI: 10.1109/ICMTS.2014.6841461 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | A single-photon avalanche diode test chip in 150nm CMOS technology L. Pancheri, G. -F. Dalla Betta, L. H. Campos Braga1, H. Xu1, D. Stoppa1 DII, University of Trento Via Sommarive, Trento, Italy 1Fondazione Bruno Kessler, Trento, Italy DOI: 10.1109/ICMTS.2014.6841486 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Low specific contact resistivity nickel to silicon carbide determined using a two contact circular test structure Y. Pan, A. M. Collins, P. W. Leech, G. K. Reeves, A. S. Holland1, P. Tanner2 School of Electrical and Computer Engineering, RMIT University, Melbourne, Australia 1Centre of Technology, RMIT University, Ho Chi Minh City, Vietnam 2Queensland Microtechnology Facility, Griffith University, Brisbane, Australia DOI: 10.1109/ICMTS.2014.6841471 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | On wafer silicon integrated noise source characterization up to 110 GHz based on Germanium-on-Silicon photodiode S. Oeuvrard, J. . -F. Lampin, G. Ducournau, S. Lepilliet, F. Danneville, T. Quemerais1, D. Gloria1 IEMN, Villeneuve d'Ascq, France 1STMicroelectronics, Crolles Cedex, France DOI: 10.1109/ICMTS.2014.6841484 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Effective field and universal mobility in high-k metal gate UTBB-FDSOI devices O. Nier, D. Rideau1, A. Cros1, F. Monsieur1, G. Ghibaudo2, R. Clerc3, J. C. Barbé4, C. Tavernier1, H. Jaouen1 DIEGM, University of Udine, Udine, Italy 1STMicroelectronics, Crolles, France 2IMEP-LAHC, Grenoble 3Laboratoire Hubert Curien (UMR 5516), Institut d'Optique Graduate School, Saint-Etienne, France 4CEA-LETI, Grenoble, France DOI: 10.1109/ICMTS.2014.6841460 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | A test structure of bypass diodes for on-chip high-voltage silicon photovoltaic cell array I. Mori, M. Kubota, Y. Mita Department of Electrical Engineering, The University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2014.6841485 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Thickness evaluation of deposited pureb layers in micro-/millimeter-sized windows to Si V. Mohammadi, S. Ramesh, L. K. Nanver Dept. Microelectronics, Delft University of Technology, Delft, CT, The Netherlands DOI: 10.1109/ICMTS.2014.6841492 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | A test structure for analysis of temperature distribution in stacked IC with sensing device array T. Matsuda, K. Yamada, H. Iwata, T. Hatakeyama, M. Ishizuka, T. Ohzone1 Toyama Prefectural University, Toyama, Japan 1Dawn Enterprise, Nagoya, Japan DOI: 10.1109/ICMTS.2014.6841476 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | A new technique for probing the energy distribution of positive charges in gate dielectric Z. Ji, S. W. M. Hatta, J. F. Zhang, W. Zhang, J. Niblock, P. Bachmayr, L. Stauffer, K. Wright, S. Greer School of Engineering, Liverpool John Moores University, Liverpool, UK DOI: 10.1109/ICMTS.2014.6841470 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | In-situ variability characterization of individual transistors using topology-reconfigurable ring oscillators A. K. M. Mahfuzul Islam, H. Onodera Graduate School of Informatics, Kyoto University, Sakyo-ku, Kyoto, JAPAN DOI: 10.1109/ICMTS.2014.6841479 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Accurate modeling of dynamic variability of SRAM cell in 28 nm FDSOI technology J. El Husseini, A. Subirats, X. Garros, A. Makoseij, O. Thomas, G. Reimbold, V. Huard1, F. Cacho1, X. Federspiel1 CEA-Leti, Grenoble, France 1STMicroelectronics, Crolles cedex, France DOI: 10.1109/ICMTS.2014.6841466 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Direct probing characterization vehicle test chip for wafer level exploration of transistor pattern on product chips C. Hess, L. Weiland, A. Joag, B. Murugan, S. Zhao, K. Doong1, S. Lin1, H. Eisenmann2 PDF Solutions Inc., San Jose, CA, USA 1PDF Solutions Inc., Zhubei City, Hsinchu County, Taiwan, R.O.C. 2PDF Solutions Inc., Munich, Germany DOI: 10.1109/ICMTS.2014.6841496 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Matched test structures for accurate characterization in millimeter wave range R. Hamani, C. Andrei1, B. Jarry, J. Lintignat XLIM, Limoges, France 1NXP Semiconductors, France DOI: 10.1109/ICMTS.2014.6841483 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Common-floating gate test structure for separation of cycling-induced degradation components in split-gate flash memory cells N. Do, Y. Tkachev Silicon Storage Technology, Inc. (a subsidiary of Microchip Technology Inc.), San Jose, CA, USA DOI: 10.1109/ICMTS.2014.6841465 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | A semi-distributed method for inductor de-embedding J. Dang, A. Noculak1, F. Korndörfer2, C. Jungemann1, B. Meinerzhagen BST, TU, Braunschweig, Germany 1ITHE, RWTH Aachen University, Aachen, Germany 2IHP GmbH, Frankfurt (Oder), Germany DOI: 10.1109/ICMTS.2014.6841482 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Analysis of process impact on local variability thanks to addressable transistors arrays A. Cros, T. Quemerais, A. Bajolet, Y. Carminati, P. Normandon, F. Kergomard, N. Planes, D. Petit, F. Arnaud, J. Rosa Crolles Site, STMicroelectronics, France DOI: 10.1109/ICMTS.2014.6841498 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | A compact array for characterizing 32k transistors in wafer scribe lanes C. S. Chen, L. Lil1, Q. Lim, H. H. Teh, N. F. Binti Omar, C. L. Ler2, J. T. Watt Process Technology Development, Altera Corporation, San Jose, CA, USA 1Altera Corp, San Jose, CA, US 2Process Technology Development, Altera Corporation, Penang, Malaysia DOI: 10.1109/ICMTS.2014.6841497 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | An approach to characterize ultra-thin conducting films protected against native oxidation by an in-situ capping layer H. Van Bui, F. B. Wiggers, M. P. de Jong, A. Y. Kovalgin MESA+ Institute for Nanotechnology, University of Twente, Enschede, AE, The Netherlands DOI: 10.1109/ICMTS.2014.6841467 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Gated contact chains for process characterization in FinFET technologies T. Brozek, S. Lam, S. Yu, M. Pak, T. Liu, R. Valishayee, N. Yokoyama1 PDF Solutions, San Jose, CA, USA 1PDF Solutions, KK, Tokyo, Japan DOI: 10.1109/ICMTS.2014.6841469 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | Effects of metal spacing and poly-silicon layers on pulsed-laser single event transient testing J. Bi, C. Zeng, L. Gao, D. Li, G. Liu, J. Luo, Z. Han, Z. Han1 Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China 1School of Microelectronics, University of Chinese Academy of Sciences, Beijing, China DOI: 10.1109/ICMTS.2014.6841494 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | | Circuits to measure the delay variability of MOSFETs K. Balakrishnan, K. Jenkins IBM T.J. Watson Research Center, Yorktown Heights, NY, USA DOI: 10.1109/ICMTS.2014.6841480 HOVER FOR ABSTRACT | PDF Xplore |
| 2014 | Process parameter calibration for millimeter-wave CMOS back-end device design with electromagnetic field analysis S. Amakawa, A. Orii, K. Katayama, K. Takano, M. Motoyoshi, T. Yoshida, M. Fujishima Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashihiroshima, Japan DOI: 10.1109/ICMTS.2014.6841490 HOVER FOR ABSTRACT | PDF Xplore | |
| 2014 | A novel apparatus for the volume estimation of in vitro thrombus growth A. Affanni, R. Specogna, F. Trevisan Dept. of Electrical, Mechanical and Management Engineering, University of Udine, Udine, Italy DOI: 10.1109/ICMTS.2014.6841472 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Test structures for electrical evaluation of high aspect ratio TSV arrays fabricated using planarised sacrificial photoresist R. Zhang, Y. Li, J. Murray, A. S. Bunting, S. Smith, C. C. Dunare, J. T. M. Stevenson, M. P. Desmulliez, A. J. Walton SMC, Institute of Integrated Micro and Nano Systems, School of Engineering, Institute of Integrated Systems, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2013.6528142 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Comparison of C-V measurement methods for RF-MEMS capacitive switches Jiahui Wang, C. Salm, J. Schmitz MESA Institute for Nanotechnology, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS.2013.6528145 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Characterisation and integration of Parylene as an insulating structural layer for high aspect ratio electroplated copper coils R. Walker, E. Sirotkin, I. Schmueser, J. G. Terry, S. Smith, J. T. M. Stevenson, A. J. Walton Institute of Integrated Micro and Nano Systems, School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, UK DOI: 10.1109/ICMTS.2013.6528137 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Evaluation of 1/f noise variability in the subthreshold region of MOSFETs H. Tuinhout, A. Z. -v. Duijnhoven NXP Semiconductors - Design Platforms, Eindhoven, The Netherlands DOI: 10.1109/ICMTS.2013.6528151 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Effective channel length estimation using charge-based capacitance measurement K. Tsuji, K. Terada Faculty of Information Sciences, Hiroshima University, Hiroshima, Japan DOI: 10.1109/ICMTS.2013.6528146 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Reconsideration of the threshold voltage variability estimated with pair transistor cell array K. Terada, N. Higuchi, K. Tsuji Faculty of Information Sciences, Hiroshima University, Hiroshima, Japan DOI: 10.1109/ICMTS.2013.6528155 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | BSIM4 parameter extraction for tri-gate Si nanowire transistors C. Tanaka, M. Saitoh, K. Ota, T. Numata Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama, Kanagawa, Japan DOI: 10.1109/ICMTS.2013.6528163 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Efficient technique for Si validation of level shifters P. Sharma, B. Smith1, D. Hall1, M. Nelson1, U. Lohani Freescale Semiconductor, Inc., Noida, India 1Freescale Semiconductor, Inc., Austin, TX, USA DOI: 10.1109/ICMTS.2013.6528173 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Electrical and mechanical characterizations of a large-area, printed organic transistor active matrix with floating-gate-based nonuniformity compensator T. Sekitani, T. Yokota, T. Tokuhara, T. Someya Department of Electrical and Electronic Engineering and Department of Applied Physics, University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2013.6528165 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Micromechanical test structures for the characterisation of electroplated NiFe cantilevers and their viability for use in MEMS switching devices G. Schiavone, S. Smith, J. Murray1, J. G. Terry, M. P. Y. Desmulliez2, A. J. Walton Institute for Integrated Micro and Nano Systems, Joint Research Institute for Integrated Systems, School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1Institute for Integrated Micro and Nano Systems, Joint Research Institute for Integrated Systems, School of Engineering, Scottish Microelectronics Centre, School of Chemistry, Joseph Black Building, University of Edinburgh, Edinburgh, UK 2MIcroSystems Engineering Centre, Joint Research Institute for Integrated Systems, School of Engineering & Physical Sciences, Heriot-Watt University, Edinburgh, UK DOI: 10.1109/ICMTS.2013.6528138 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Measurements of SRAM sensitivity against AC power noise with effects of device variation T. Sawada, K. Yoshikawa, H. Takata1, K. Nii1, M. Nagata Graduate School of System Informatics, Kobe University, Kobe, Japan 1Renesas Electronics Corporation, Tokyo, Japan DOI: 10.1109/ICMTS.2013.6528149 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Characterization of capacitance mismatch using simple difference Charge-based Capacitance measurement (DCBCM) test structure K. Sawada, G. Van der Plas1, Y. Miyamori2, T. Oishi3, C. Vladimir1, A. Mercha1, V. Diederik1, H. Ammo3 IMEC, Sony Corporation, Leuven, Belgium 1IMEC, Leuven, Belgium 2Sony Semiconductor Corporation, Kumamoto, Japan 3Sony Corporation, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.2013.6528144 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Newly developed Test-Element-Group for detecting soft failures of the low-resistance-element using doubly nesting array S. Sato, H. Shinkawata, A. Tsuda, T. Yoshizawa, T. Ohno Devices and Analysis Technology Div., Production and Technology Unit., Renesas Electronics Corporation, Hyogo, Japan DOI: 10.1109/ICMTS.2013.6528152 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | New methodology for drain current local variability characterization using Y function method L. Rahhal, A. Bajolet, C. Diouf, A. Cros, J. Rosa, N. Planes, G. Ghibaudo1 STMicroelectronics, Crolles, France 1Minatec , INPG, IMEP-LAHC, Grenoble, France DOI: 10.1109/ICMTS.2013.6528153 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | A proper approach to characterize retention-after-cycling in 3D-Flash devices Fengying Qiao, A. Arreghini1, P. Blomme1, G. Van den bosch1, Liyang Pan, Jun Xu, J. Van Houdt1 Institute of Microelectronics, Tsinghua University, Beijing, China 1Imec, Leuven, Belgium DOI: 10.1109/ICMTS.2013.6528169 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Measurement and investigation of thermal properties of the on-chip metallization for integrated power technologies M. Pfost, C. Boianceanu1, I. Lascau1, D. -I. Simon1, S. Sosin1 Robert Bosch Center for Power Electronics, Reutlingen University, Reutlingen, Germany 1ATV PTP TM, Infineon Technologies Romania, Bucharest, Romania DOI: 10.1109/ICMTS.2013.6528157 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | On the length of THRU standard for TRL de-embedding on Si substrate above 110 GHz A. Orii, M. Suizu, S. Amakawa, K. Katayama, K. Takano, M. Motoyoshi, T. Yoshida, M. Fujishima Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashihiroshima, Japan DOI: 10.1109/ICMTS.2013.6528150 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | A novel test structure to implement a programmable logic array using split-gate flash memory cells H. Om'mani, M. Tadayoni, N. Thota, Ian Yue, Nhan Do A Subsidiary of Microchip Technology Inc., Silicon Storage Technology, San Jose, California, USA DOI: 10.1109/ICMTS.2013.6528170 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Mosaic SRAM Cell TEGs with intentionally-added device variability for confirming the ratio-less SRAM operation H. Okamura, T. Saito, H. Goto, M. Yamamoto, K. Nakamura Center for Microelectronic Systems, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan DOI: 10.1109/ICMTS.2013.6528174 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | | Tr variance evaluation induced by probing pressure and its stress extraction methodology in 28nm High-K and Metal Gate process T. Okagaki, T. Hasegawa, H. Takashino, M. Fujii, A. Tsuda, K. Shibutani, Y. Deguchi, M. Yokota, K. Onozawa Renesas Electronics Corporation, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.2013.6528172 HOVER FOR ABSTRACT | PDF Xplore |
| 2013 | Die-to-die and within-die variation extraction for circuit simulation with surface-potential compact model Y. Ohnari, A. A. Khan, A. Dutta, M. Miura-Mattausch, H. J. Mattausch Research Institute for Nanodevice and Bio Systems, Hiroshima University, Higashi, Hiroshima, Japan DOI: 10.1109/ICMTS.2013.6528162 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Optical high frequency test structure and test bench definition for on wafer silicon integrated noise source characterization up to 110 GHz based on Germanium-on-Silicon photodiode S. Oeuvrard, J. . -F. Lampin, G. Ducournau, L. Virot1, J. M. Fedeli2, J. M. Hartmann2, F. Danneville, Y. Morandini3, D. Gloria1 IEMN, Villeneuve d'Ascq, France 1TR&D, TPS Laboratory, STMicroelectronics, Crolles, France 2LETI, CEA, Grenoble, France 3Dolphin Integration GmbH, Meylan, France DOI: 10.1109/ICMTS.2013.6528148 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Investigation of devices of in-vivo energy harvesting through blood-flow-like excitation R. O'Keeffe, N. Jackson, A. Mathewson, K. G. McCarthy1 Tyndall National Institute, University College Cork, Cork, Ireland 1Department of Electrical and Electronic Engineering, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.2013.6528139 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Analysis of narrow gate to gate space dependence of MOS gate-source/drain capacitance by using contact-less and drawn-out source/drain test structure Y. Naruta, S. Kumashiro1 Renesas Electronics Corporation, Kodaira, Tokyo, Japan 1Renesas Electronics Corporation, Kawasaki, Kanagawa, Japan DOI: 10.1109/ICMTS.2013.6528160 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | A test structure for analysis of temperature distribution in CMOS LSI with sensing device array T. Matsuda, H. Hanai, H. Iwata, D. Kondo, T. Hatakeyama, M. Ishizuka, T. Ohzone1 Department of Information Systems Engineering, Toyama Prefectural University, Imizu, Japan 1Dawn Enterprise Company Limited, Nagoya, Japan DOI: 10.1109/ICMTS.2013.6528159 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Benchmarking of a surface potential based organic thin-film transistor model against C10-DNTT high performance test devices T. K. Maiti, T. Hayashi1, H. Mori2, M. J. Kang2, K. Takimiya2, M. Miura-Mattausch3, H. J. Mattausch3 HiSIM Research Center, Hiroshima University, Higashi, Hiroshima, Japan 1Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashi, Hiroshima, Japan 2Department of Applied Chemistry, Graduate School of Engineering, Hiroshima University, Higashi, Hiroshima, Japan 3HiSIM Research Center, Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashi, Hiroshima, Japan DOI: 10.1109/ICMTS.2013.6528164 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | A new Ultra-Fast Single Pulse technique (UFSP) for channel effective mobility evaluation in MOSFETs Z. Ji, J. Gillbert1, J. F. Zhang, W. Zhang School of Engineering, Liverpool John Moores University, Liverpool, UK 1Keithley Instruments, Inc., UK DOI: 10.1109/ICMTS.2013.6528147 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Three- and four-point Hamer-type MOSFET parameter extraction methods revisited K. O. Jeppson Department of Microtechnology and Nanoscience, Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS.2013.6528161 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | A novel BJT structure for high- performance analog circuit applications S. -M. Hwang, H. -M. Kwon, J. -H. Jang, H. -Y. Kwak, S. -K. Kwon, S. -Y. Sung, J. -K. Shin, J. -N. Yu, I. -S. Han, Y. -S. Chung, J. -H. Lee, G. -W. Lee, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejeon, South Korea DOI: 10.1109/ICMTS.2013.6528154 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | An integrated CMOS-MEMS probe having two-tips per cantilever for individual contact sensing and kelvin measurement with two cantilevers K. Hosaka, S. Morishita, I. Mori, M. Kubota, Y. Mita School of Engineering, University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2013.6528136 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Comparison of electrical techniques for temperature evaluation in power MOS transistors A. Ferrara, P. G. Steeneken1, K. Reimann1, A. Heringa2, L. Yan2, B. K. Boksteen, M. Swanenberg3, G. E. J. Koops2, A. J. Scholten2, R. Surdeanu2, J. Schmitz, R. J. E. Hueting MESA Institute for Nanotechnology, University of Twente, Enschede, Netherlands 1NXP Semiconductors, Eindhoven, Netherlands 2NXP Semiconductors, Leuven, Belgium 3NXP Semiconductors, Nijmegen, Netherlands DOI: 10.1109/ICMTS.2013.6528156 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | A novel silicon interposer for measuring devices requiring complex two-sided contacting J. Derakhshandeh, N. Golshani, L. A. Steenweg, W. van der Vlist, L. K. Nanver DIMES, Delft University of Technology Engineering, Delft, Netherlands DOI: 10.1109/ICMTS.2013.6528143 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures C. -T. Dai, M. -D. Ker Institute of Electronics, National Chiao-Tung University, Taiwan DOI: 10.1109/ICMTS.2013.6528158 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Greek cross test structure for inkjet printed thin films E. Däaz, E. Ramon, J. Carrabina CAIAC, Microelectronics and Electronic Systems Department, Universitat Autònoma de Barcelona, Barcelona, Spain DOI: 10.1109/ICMTS.2013.6528166 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | On-wafer integrated system for fast characterization and parametric test of new-generation Non Volatile Memories E. Covi, A. Cabrini, L. Vendrame1, L. Bortesi1, R. Gastaldi1, G. Torelli2 Dipartimento di Ingegneria Industriale e dellInformazione, University of Pavia, Pavia, Italy 1Micron Semiconductor Italia s.r.l., R&D - Technology Development, Agrate Brianza, Italy 2Universita degli Studi di Pavia, Pavia, Lombardia, IT DOI: 10.1109/ICMTS.2013.6528171 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Process control monitors for individual single-walled carbon nanotube transistor fabrication processes K. Chikkadi, M. Haluska, C. Hierold, C. Roman Micro and Nanosystems, Department of Mechanical and Process Engineering, ETH Zurich, Zurich, Switzerland DOI: 10.1109/ICMTS.2013.6528167 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Characterization and simulation of NMOS pass transistor reliability for FPGA routing circuits C. S. Chen, J. T. Watt Process Technology Development, Altera Corporation, San Jose, CA, USA DOI: 10.1109/ICMTS.2013.6528175 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | Test structure and analysis for accurate RF-characterization of tungsten through silicon via (TSV) grounding devices V. Blaschke, H. Jebory1 TowerJazz Semiconductors Limited, Newport, CA, USA 1TowerJazz Semiconductors Limited, Newport Beach, CA, USA DOI: 10.1109/ICMTS.2013.6528141 HOVER FOR ABSTRACT | PDF Xplore | |
| 2013 | A new measurement set-up to investigate the charge trapping phenomena in RF MEMS packaged switches M. Barbato, V. Giliberto, G. Meneghesso Department of Information Engineering, University of Padova, Padova, Italy DOI: 10.1109/ICMTS.2013.6528140 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Modification and characterisation of material hydrophobicity for surface acoustic wave driven microfluidics H. Zou, Y. Li, S. Smith, A. S. Bunting, A. J. Walton, J. G. Terry Institute for Integrated Micro and Nano Systems, School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2012.6190614 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Parameter extraction for relaxation-time based non-quasi-static MOSFET models Z. Zhu, C. C. McAndrew1, Ik-Sung Lim1, G. Gildenblat School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA 1Freescale Semiconductor, Inc., Tempe, AZ, USA DOI: 10.1109/ICMTS.2012.6190645 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Very low frequency noise characterization of semiconductor devices using DC parameter analyzers H. Tuinhout, A. Zegers-van Duijnhoven, A. Heringa NXP Semiconductors-Central Research and Development, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2012.6190641 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Threshold voltage variation extracted from MOSFET C-V curves by charge-based capacitance measurement K. Tsuji, K. Terada, R. Takeda, T. Tsunomura1, A. Nishida1, T. Mogami1 Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan 1MIRAI-Selete, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2012.6190623 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A novel test structure for FEOL device CCTG CBCM measurement in advanced 28nm technology W. Tsao, Kin Hooi Dia, Zheng Zeng, Cheng Hsing Chien MediaTek, Inc., Hsinchu, Taiwan DOI: 10.1109/ICMTS.2012.6190658 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A novel high-throughput on-wafer electromechanical sensitivity characterization system for piezoresistive cantilevers G. Tosolini, L. G. Villanueva1, F. Perez-Murano, J. Bausells Instituto de Microelectrónica de Barcelona (CNM, CSIC), Bellaterra, Spain 1California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.2012.6190613 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | An improved procedure to extract the limiting carrier velocity in ultra scaled CMOS devices P. Toniutti, R. Clerc, P. Palestri1, C. Diouf2, A. Cros2, D. Esseni1, F. Boeuf2, G. Ghibaudo, L. Selmi1 IMEP-LAHC, MINA TEC, Grenoble, France 1DIEGM, Udine, Italy 2STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2012.6190642 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Phase Change Memory advanced electrical characterization for conventional and alternative applications A. Toffoli, M. Suri, L. Perniola1, A. Persico2, C. Jahan2, J. F. Nodin2, V. Sousa, B. DeSalvo, G. Reimbold LETI, CEA, Grenoble, France 1CEA, LETI, MINATEC Campus, 17 rue des Martyrs, France 2CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 GRENOBLE Cedex 9, France DOI: 10.1109/ICMTS.2012.6190618 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Study on Device Matrix Array structure for MOSFET gm variability evaluation K. Terada, R. Takeda, K. Tsuji, T. Tsunomura1, A. Nishida1, T. Mogami1 Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan 1MIRAI-Selete, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2012.6190621 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | New evaluation method of low-k dielectric films by using a gated PN-junction diode and a field MOS transistor Y. Tamaki, M. Ito, M. Hashino, Y. Kawamoto Consortium for Advanced Semiconductor Materials and Related Technologies, Kokubunji, Tokyo, Japan DOI: 10.1109/ICMTS.2012.6190632 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A compact circuit for wafer-level monitoring of operational amplifier high-frequency performance using DC parametric test equipment Z. G. Sparling, V. C. Tyree, N. Cox, P. T. Vernier MOSIS Service, Information Sciences Institute, Viterbi School of Engineering, University of Southern California, Marina del Rey, CA, USA DOI: 10.1109/ICMTS.2012.6190633 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Simultaneous characterization of mechanical and electrical performances of ultraflexible and stretchable organic integrated circuits T. Sekitani, T. Yokota, K. Kuribara, T. Someya Department of Electrical and Electronic Engineering and Department of Applied Physics, University of Tokyo, Bunkyo, Tokyo, Japan DOI: 10.1109/ICMTS.2012.6190648 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Quantitative wafer mapping of residual stress in electroplated NiFe films using independent strain and Young's modulus measurements G. Schiavone, M. P. Y. Desmulliez1, S. Smith, J. Murray2, E. Sirotkin, J. G. Terry, A. R. Mount3, A. J. Walton Institute for Integrated Micro and Nano Systems, Joint Research Institute for Integrated Systems, School of Engineering, Scottish Microelectronics Centre, The University of Edinburgh, Edinburgh, UK 1MIcro Systems Engineering Centre, joint Research Institute for Integrated Systems, School of Engineering & Physical Sciences, Heriot-Watt University, Edinburgh, UK 2School of Chemistrv, Joseph Black Building, The University of Edinburgh, UK 3School of Chemistrv, Joseph Black Building, The University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2012.6190629 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Combined C-V/I-V front-end-of-line measurement S. Polonsky, S. Realov1, J. -H. Liao2, M. Hargrove3, M. Ketchen IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA 1Department of Electrical Engineering, Columbia University, New York, NY, USA 2Systems and Technology Group, IBM, Hopewell Junction, NY, USA 3GLOBALFOUNDRIES, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.2012.6190656 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Electrical characterisation of dry microneedle electrodes for portable bio-potential recording applications F. Pini, C. O'Mahony1, K. G. McCarthy Dept. of Electrical and Electronic Engineering, University College Cork, Cork, Ireland 1Tyndall National Institute, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.2012.6190624 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A novel high accurate analytical technique of the leak current for the product chip T. Okagaki, N. Takeshita, S. Tanaka, S. Tateishi, K. Shibutani, T. Tsutsui, H. Abe, M. Yokota, K. Onozawa Renesas Electronics Corporation, Hyogo, Japan DOI: 10.1109/ICMTS.2012.6190626 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A novel structure of MOSFET array to measure off-leakage current with high accuracy H. Oishi, T. Suzuki, M. Bairo, S. Mori, K. Ogawa, H. Ohnuma Semiconductor Technology Development Division, Core Device Development Group, Research and Development Platform, Sony Corporation, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.2012.6190604 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Development of a novel system for characterizing MOSFET noise in higher frequency regimes K. Ohmori, R. Hasunuma, K. Yamada JST-CREST, Japan DOI: 10.1109/ICMTS.2012.6190639 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Ring oscillator with calibration circuit for accurate on-chip IR-drop measurement S. Nishizawa, H. Onodera1 Graduate School of Informatics,Kyoto University, Sakyo-ku, Kyoto, JAPAN 1JST-CREST, Japan DOI: 10.1109/ICMTS.2012.6190602 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Correlation of optical and electrical test structures for characterisation of copper self-annealing J. Murray, S. Smith1, G. Schiavone1, J. G. Terry1, A. R. Mount2, A. J. Walton1 School of Chemistry, University of Edinburgh, UK 1Institute for Integrated Micro and Nano Systems (Joint Research Institute for Integrated Systems), School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 2The University of Edinburgh, Edinburgh, Edinburgh, GB DOI: 10.1109/ICMTS.2012.6190635 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A blur-range test structure of collimation-controller-integrated silicon shadow mask for three-dimensional surface patterning with sputtering S. Morishita, M. Kubota, Y. Mita Department of Electrical Engineering and Information Systems, University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2012.6190615 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Evaluation of dynamic bonding stress and interlayer cracking using a combo sensor Y. Miki, H. Watanabe Corporate Technology Development Group, Ricoh Company Limited, Ikeda, Osaka, Japan DOI: 10.1109/ICMTS.2012.6190647 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | | Self-biasing and self-amplifying MOSFET mismatch test structure C. C. McAndrew, M. Zunino, B. Braswell Freescale Semiconductor, Inc., Tempe, AZ, USA DOI: 10.1109/ICMTS.2012.6190651 HOVER FOR ABSTRACT | PDF Xplore |
| 2012 | Reliability analysis of NAND gates with modified channel length in series n-MOSFETs T. Matsuda, Y. Tokumitsu, H. Hanai, H. Iwata, T. Ohzone1 Department ofInformation Systems Engineering, Toyama Prefectural University, Japan 1Dawn Enterprise, Nagoya, Japan DOI: 10.1109/ICMTS.2012.6190625 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | In-situ calibration and verification techniques for the characterization of microwave circuits and devices I. Martinez Centellax, Inc., Santa Rosa, CA, USA DOI: 10.1109/ICMTS.2012.6190637 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | An extended de-embedding method for on-wafer components Yu-Ling Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chewn-Pu Jou, Chin-Wei Kuo, Min-Che Jeng, Fu-Lung Hsuch, Chih-Hua Hsiao1, Guo-Wei Huang1 Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan 1National Nano Device Laboratories, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2012.6190638 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Dynamic pixel test pattern for CMOS image sensor K. Lee, H. Lee, M. Jang, J. Kim, S. Kim, J. Moon, I. Cho, K. Yoo Hynix Semiconductor Inc., Kyoungi-Do, Korea DOI: 10.1109/ICMTS.2012.6190617 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A test circuit for extremely low gate leakage current measurement of 10 aA for 80,000 MOSFETs in 80 s Y. Kumagai, T. Inatsuka1, R. Kuroda, A. Teramoto2, T. Suwa2, S. Sugawa2, T. Ohmi2 Graduate School of Engineering, Tohoku University, Aoba-ku, Japan 1Graduate School of Engineering, Tohoku University 2New Industry Creation Hatchery Center, Tohoku University, Sendai, Japan DOI: 10.1109/ICMTS.2012.6190631 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Simple gate charge (Qg) measurement technique for on-wafer statistical monitoring and modeling of power semiconductor devices V. Krishnamurthy, A. Gyure, P. Francis Texas Instruments, Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS.2012.6190627 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Calibration of library element optimization to improve static power V. Kolagunta, S. Sundareswaran1, P. Sharma1, D. Hall1, M. A. Thompson2, B. Smith1, S. Veeraraghavan1 Global Foundries, Inc., Malta, NY, USA 1Freescale Semiconductor, Inc., Austin, TX, USA 2Austin, TX, USA DOI: 10.1109/ICMTS.2012.6190603 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Self-heating parameter extraction of power MOSFETs based on transient drain current measurements and on the 2-cell self-heating model R. Koh, T. Iizuka Technology Development Unit, RENESAS Electronics, Kawasaki, Kanagawa, Japan DOI: 10.1109/ICMTS.2012.6190644 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | 32nm yield learning using addressable defect arrays M. Karthikeyan, J. Cassels, L. Arie IBM Systems and Technology Group, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.2012.6190620 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Nano CV probe characterization analysis comparison with conventional CV probe pad analysis T. Kane, M. P. Tenney IBM Systems and Technology Group, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.2012.6190657 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Active “multi-fingers”: Test structure to improve MOSFET matching in sub-threshold area Y. Joly, L. Lopez1, J. . -M. Portal, H. Aziza, Y. Bert2, F. Julien2, P. Fornara2 IM2NP Laboratory (UMR CNRS 6242), Marseille, France 1S TMicroelectronics, Rousset, France 2STMicroelectronics, Rousset, France DOI: 10.1109/ICMTS.2012.6190652 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A diaphragm based piezoelectric AlN film quality test structure N. Jackson, R. O'Keeffe, R. O'Leary1, M. O'Neill2, F. Waldron, A. Mathewson Tyndall National Institute, University College Cork, Cork, Ireland 1University College Cork National University of Ireland, Cork, IE 2Analog Devices Inc., Limerick, Ireland DOI: 10.1109/ICMTS.2012.6190612 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Compact thermal-interaction model for dynamic within chip temperature determination by circuit simulation K. Ishiguro, A. Ueno, A. Toda, M. Miyake, H. J. Mattausch, M. Miura-Mattausch, K. Matsuzawa1, T. Iizuka1, S. Yamaguchi1, T. Hoshida1, A. Kinoshita1, T. Arakawa1 Graduate School of Advanced Science of Matter, Hiroshima University, Higashihiroshima, Japan 1Semiconductor Technology Academic Research Center, Kanagawa, Japan DOI: 10.1109/ICMTS.2012.6190643 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A universal test structure for the direct measurement of the design margin of even-stage ring oscillators with CMOS latch Y. Hirakawa, A. Motomura, K. Ota, N. Mimura, K. Nakamura Center for Microelectronic Systems, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan DOI: 10.1109/ICMTS.2012.6190605 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A proposition on test circuit structures using selectively metal-covered transistors for a laser irradiation failure analysis H. Hatano Department of Electrical and Electronic Engineering, Faculty of Science and Technology, Shizuoka Institute of Science and Technology, Fukuroi, Shizuoka, Japan DOI: 10.1109/ICMTS.2012.6190622 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Fast and accurate characterizationst of interconnect capacitance network using Degenerated Exhaustive Direct Charge Measurements (DEDCM) M. Goto, J. Taniguchi, K. Takano Agilent Technologies International Japan Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.2012.6190659 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Inhomogeneous ring oscillator for WID variability and RTN characterization S. Fujimoto, I. A. K. M. Mahfzul, T. Matsumoto, H. Onodera1 Graduate School of Informatics, Kyoto University, Japan 1CREST, Japan Science and Technology Agency, Japan DOI: 10.1109/ICMTS.2012.6190607 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Experimental extraction of substrate-noise coupling between MOSFETs and its compact modeling for circuit simulation S. Emoto, T. Miyoshi, M. Miyake, H. J. Mattausch, M. Miura-Mattausch, T. Iizuka1, Y. Sahara1, T. Hoshida1, K. Matsuzawa1, T. Arakawa1 Graduate School of Advanced Science of Matter, Hiroshima University, Higashihiroshima, Japan 1Semiconductor Technology Academic Research Center, Shin-Yokohama, Kanagawa, Japan DOI: 10.1109/ICMTS.2012.6190628 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | A novel compact CBCM method for high resolution measurement in 28nm CMOS technology Kin Hooi Dia, Willy Tsao, Cheng Hsing Chien, Zheng Zeng MediaTek, Inc., Hsinchu, Taiwan DOI: 10.1109/ICMTS.2012.6190619 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Improved precision methodology for access resistance extraction using Kelvin test structures A. Cros, G. Morin, G. Castaneda, F. Dieudonné, J. Rosa TResearch and Development/STD/TPS/ECR, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2012.6190634 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Piezoresistive membrane deflection test structure for the evaluation of hermeticity in low cavity volume MEMS and microelectronic packages S. Costello, M. P. Y. Desmulliez, S. McCracken1, C. Lowrie, S. Cargill, A. J. Walton2 MIcroSystems Engineering Centre (MISEC), Institute for Integrated Systems (IIS), School of Engineering and Physical Sciences, Heriot-Watt University, Edinburgh, UK 1Centre House, Midlothian Innovation Centre, MCS Limited, Midlothian, UK 2Scottish Microelectronics Centre, Institute of Integrated Systems (lIS), School of Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2012.6190611 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Impact of mask making imperfections on the performance of matching critical sub-circuit blocks L. J. Choi, M. Poulter, J. de Santis, G. Cestra, L. Moberly, K. Gadepally, H. McCulloh, R. Beera, V. Garg1, K. Green1, J. Prater Texas Instruments, Inc., Santa Clara, CA, USA 1Toppan Photomasks, Inc., Round Rock, TX, USA DOI: 10.1109/ICMTS.2012.6190654 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Addressable test structures for MOSFET variability analysis S. Chitrashekaraiah, S. Guo, R. Herberholz, D. Vigar, M. Redford1 CSR Limited, Cambridge, UK 1CSR Technology Inc, 217 Devcon Drive, San Jose, CA, 95112, USA DOI: 10.1109/ICMTS.2012.6190608 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Test structures for interdie variations monitoring in presence of statistical random variability G. Castaneda, A. Juge1, G. Ghibaudo, D. Golanski1, D. Hoguet2, J. -M. Portal3, B. Borot1 IMEP_LAHC, Minatec, INPG, Grenoble, France 1STMicroelectronics, Crolles, France 2STMicroelectronics, Crolles, FR 3IM2NP IMT Technopole de Château Gombert France, Marseilles, France DOI: 10.1109/ICMTS.2012.6190609 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | The MEMS 5-in-1 Reference Materials (RM 8096 and 8097) J. Cassard, J. Geist, M. Gaitan, D. G. Seiler Semiconductor and Dimensional Metrology Division, Physical Measurement Laboratory, National Institute for Standards and Technology, USA DOI: 10.1109/ICMTS.2012.6190649 HOVER FOR ABSTRACT | PDF Xplore | |
| 2012 | Characterization and modeling methodology for the evaluation of statistical variation of MOSFETs L. Bortesi, L. Vendrame, P. Fantini, A. Spessot, A. L. Lacaita1 Research and Development-Technology Development, Micron Technology, Inc., Agrate-Brianza, Italy 1IFN-CNR, Politecnico of Milano, Milano, Italy DOI: 10.1109/ICMTS.2012.6190653 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Modeling the frequency dependence of MOSFET gate capacitance Z. Zhu, G. Gildenblat, C. C. McAndrew1, I. -S. Lim1 School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA 1Freescale Semiconductor, Inc., Tempe, AZ, USA DOI: 10.1109/ICMTS.2011.5976853 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Characterization and modelling of gate current injection in embedded non-volatile flash memory A. Zaka, D. Garetto1, D. Rideau, P. Palestri2, J. -P. Manceau1, E. Dornel1, Q. Rafhay3, R. Clerc3, Y. Leblebici4, C. Tavernier, H. Jaouen STMicroelectronics, Crolles, France 1IBM S and TG, Crolles, France 2DIEGM, University of Udine, Udine, Italy 3MINATEC, LAHC, IMEP, Grenoble, France 4Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland DOI: 10.1109/ICMTS.2011.5976874 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Radiation effects upon the mismatch of identically laid out transistor pairs J. Verbeeck, P. Leroux, M. Steyaert1 Department IBW-RELIC, Katholieke hogeschool Kempen, Geel, Belgium 1Department ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.2011.5976845 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Evaluation of MOSFET C-V curve variation using test structure for charge-based capacitance measurement K. Tsuji, K. Terada, R. Kikuchi, T. Tsunomura1, A. Nishida1, T. Mogami1 Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan 1MIRAI-Selete, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2011.5976852 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Electrical estimation of channel dopant uniformity using test MOSFET array K. Terada, K. Sanai, K. Tsuji, T. Tsunomura1, A. Nishida1, T. Mogami1 Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan 1MIRAI-Selete, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2011.5976871 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | New test structure for evaluating low-k dielectric interconnect layers by using ring-oscillators and metal comb/serpentine patterns Y. Tamaki, M. Ito, Y. Takimoto1, M. Hashino, Y. Kawamoto Consortium for Advanced Semiconductor Materials and Related Technologies (CASMAT), Kokubunji-shi, Tokyo, JAPAN 1JSR Corporation, Japan DOI: 10.1109/ICMTS.2011.5976873 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Silicon high frequency test structures improvement for millimeter wave varactors characterization optimization and modeling F. Sonnerat, R. Debroucke1, Y. Morandini2, D. Gloria, J. -D. Arnould3, C. Gaquière4 TRD, TPS Laboratory, STMicroelectronics, Crolles, France 1I.E.M.N, Villeneuve d'Ascq, France 2SRDC, IBM, Crolles, France 3IMEP, Grenoble, France 4NA DOI: 10.1109/ICMTS.2011.5976868 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Nonlinear network analyzer measurements for better transistor modeling F. Sischka Agilent Technologies, Inc., Boblingen, Germany DOI: 10.1109/ICMTS.2011.5976867 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Gated diode in breakdown voltage collapse regime -- A test vehicle for oxide characterization A. Rusu, M. Badila1, A. Rusu University POLITEHNICA of Bucharest, Romania 1On Semiconductor, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2011.5976875 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Contact resistance measurement structures for high frequencies D. Roy, R. M. T. Pijper, L. F. Tiemeijer, R. A. M. Wolters Central Research and Development, NXP Semiconductors, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2011.5976859 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Device variability and correlation control by automated tuning of SPICE cards to PCM measurements A. Revelant, L. Lucci, L. Selmi1, B. Ankele Infineon Technologies Austria AG, Villach, Austria 1DIEGM, Università degli Studi di Udine, Udine, Italy DOI: 10.1109/ICMTS.2011.5976877 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Low cost wafer level parallel test strategy for reliability assessments in sub-32nm technology nodes M. Rafik, F. Dieudonné, G. Morin Crolles Site, TResearch and Development, STD, TPS, ECR, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2011.5976856 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Front-end-of-line quadrature-clocked voltage-dependent capacitance measurement S. Polonsky, P. Solomon, J. -h. Liao1, L. Medina1, M. Ketchen IBM Thomson J.Watson Research Center, Yorktown Heights, NY, USA 1IBM Systems and Technology Group, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.2011.5976851 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | | An efficient array structure to characterize the impact of through silicon vias on FET devices D. Perry, J. Cho1, S. Domae2, P. Asimakopoulos3, A. Yakovlev3, P. Marchal4, G. Van der Plas4, N. Minas4 Qualcomm, San Diego, CA, USA 1Samsung, IMEC, Belgium 2Panasonic, IMEC, Belgium 3University of Newcastle, UK 4IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.2011.5976872 HOVER FOR ABSTRACT | PDF Xplore |
| 2011 | Matching characteristics of metal resistors H. Namba, T. Hashimoto, K. Hayashi, M. Furumiya Device Framework Development Department, Renesas Electronics Corporation, 1753, Shimonumabe, Nakahara-Ku, Kawasaki, Kanagawa 211-8668, Japan DOI: 10.1109/ICMTS.2011.5976844 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Characterisation of electroplated NiFe films using test structures and wafer mapped measurements J. Murray, G. Schiavone1, S. Smith1, J. Terry1, A. R. Mount2, A. J. Walton1 School of Chemistry, University of Edinburgh, UK 1Institute for Integrated Micro and Nano Systems (part of the Joint Research Institute for Integrated Systems), School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 2The University of Edinburgh, Edinburgh, Edinburgh, GB DOI: 10.1109/ICMTS.2011.5976861 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Improved parameter extraction procedures for the R3 model C. C. McAndrew, T. Bettinger Freescale Semiconductor, Inc., Tempe, AZ, USA DOI: 10.1109/ICMTS.2011.5976858 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Admittance characterization and interface trap property extraction for Ge/III-V MOS structures K. Martens IMEC, Belgium DOI: 10.1109/ICMTS.2011.5976850 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Variation-sensitive monitor circuits for estimation of Die-to-Die process variation I. A. K. M. Mahfuzul, A. Tsuchiya, K. Kobayashi1, H. Onodera2 Graduate School of Informatics, Kyoto University, Kyoto, Japan 1Graduate School of Science and Technology, Kyoto Institute of Technology, Kyoto, Japan 2CREST, Japan Science and Technology Agency, Japan DOI: 10.1109/ICMTS.2011.5976878 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Innovative thin film deposition technologies enabling new materials and new device integration roadmaps J. W. Maes ASM, The Netherlands DOI: 10.1109/ICMTS.2011.5976869 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Lateral bipolar structures for evaluating the effectiveness of surface doping techniques G. Lorito, L. Qi, L. K. Nanver DIMES, Delft University of Technnology, Delft, Netherlands DOI: 10.1109/ICMTS.2011.5976870 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | A versatile defectivity monitor designed for efficient test and failure analysis M. Lauderdale, B. Smith Freescale Semiconductor, Inc., Austin, TX, USA DOI: 10.1109/ICMTS.2011.5976855 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Scalable thermal resistance model for single and multi-finger silicon-on-insulator MOSFETs S. Khandelwal, J. Watts1, E. Tamilmani2, L. Wagner3 Department of Electronics and Telecommunication, Norwegian University of Science and Technology, Norway 1IBM Semiconductor Research and Development Centre, Burlington, USA 2IBM Semiconductor Research and Development Centre, Bangalore, India 3IBM Semiconductor Research and Development Centre, East Fishkill, USA DOI: 10.1109/ICMTS.2011.5976843 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Design of a test chip with small embedded temperature sensor structures realized in a common-drain power trench technology H. Köck, R. Illing1, T. Ostermann1, S. Decker2, D. Dibra2, G. Pobegen3, S. de Filippis4, M. Glavanovics3, D. Pogany Institute of Solid State Electronics, University of Technology, Vienna, Vienna, Austria 1DC ATV BP, Infineon Technologies Austria AG, Villach, Austria 2ATV PTP TD, Infineon Technologies, Neubiberg, Germany 3KAI (Kompetenzzentrum Automobil-und Industrie-Elektronik), Villach, Austria 4Department of Electronic and Telecommunication Engineering, University of Napoli Federico II, Naples, Italy DOI: 10.1109/ICMTS.2011.5976842 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Novel BJT test structure for high-performance matching characteristics in CMOS-based analog applications Y. -J. Jung, B. -S. Park, I. -S. Han, H. -M. Kwon, S. -U. Park, J. -D. Bok, Y. -S. Chung, M. -G. Lim, J. -H. Lee, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejeon, South Korea DOI: 10.1109/ICMTS.2011.5976846 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Product relevant device leakage scribe characterization vehicle test chip for efficient full wafer testing C. Hess, R. Firu, R. Vallishayee, S. Yu, P. Zhao, S. Zhao PDF Solutions, Inc.orporated, San Jose, CA, USA DOI: 10.1109/ICMTS.2011.5976857 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Exploring capacitance-voltage measurements to find the piezoelectric coefficient of aluminum nitride T. van Hemert, D. Sarakiotis, S. Jose, R. J. E. Hueting, J. Schmitz MESA Institute for Nanotechnology, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS.2011.5976862 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Test structures and a measurement system for characterising the lifetime of EWOD devices D. Gruber, Y. Li1, S. Smith1, A. Tiwari1, F. Deng1, A. A. Stokes2, J. G. Terry1, A. S. Bunting1, L. Mackay1, P. Langridge-Smith2, A. J. Walton1 SIRCAMS School of Chemistry, University of Edinburgh, Edinburgh, UK 1Scottish Microelectronic Centre, Institute of Micro and Nano Systems Institute of Integrated Systems School of Engineering, University of Edinburgh, Edinburgh, UK 2The University of Edinburgh, Edinburgh, Edinburgh, GB DOI: 10.1109/ICMTS.2011.5976864 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Gap-closing test structures for temperature budget determination E. J. Faber, R. A. M. Wolters1, J. Schmitz MESA Institute for Nanotechnology, Semiconductor Components Group, University of Twente, Enschede, Netherlands 1NXP Semiconductors, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2011.5976840 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Experimental procedure for accurate trap density study by low frequency charge pumping measurements A. Datta, F. Driussi, D. Esseni, G. Molas1, E. Nowak1 DIEGM, IU.NET, University of Udine, Udine, Italy 1Leti, CEA, Grenoble, France DOI: 10.1109/ICMTS.2011.5976876 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Strategy for in-line MOS transistor transport optimization A. Cros Crolles Site, TResearch and Development/STD/TPS/ECR, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2011.5976860 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Interdigitated electrode modelling for applications in dielectrophoresis C. Chung, S. Smith, A. Menachery, P. Bagnaninchi, A. J. Walton, R. Pethig Institute for Integrated Micro and Nano Systems, School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, UK DOI: 10.1109/ICMTS.2011.5976863 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Simple current and capacitance methods for bulk finFET height extraction and correlation to device variability T. Chiarella, B. Parvais, N. Horiguchi, M. Togo, C. Kerner, L. Witters, P. Absil, S. Biesemans, T. Hoffmann IMEC vzw, Leuven, Belgium DOI: 10.1109/ICMTS.2011.5976879 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Decoupling of RTS noise in high density CMOS image sensor using new test structures J. -D. Bok, I. -S. Han, H. -M. Kwon, S. -U. Park, Y. -J. Jung, S. -H. Park, W. -I. Choi, M. -L. Ha, J. -I. Lee, H. -D. Lee Department of Electronics Engineering, Chungnam National University, Daejeon, South Korea DOI: 10.1109/ICMTS.2011.5976865 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | High temperature on-wafer measurement structure for DMOS characterization C. Boianceanu, D. Simon, R. Blanaru, D. Costachescu, M. Pfost1 Infineon Technologies Romania, IFRO ATV TM, Bucharest, Romania 1Robert-Bosch-Center of Power Electronics, Reutlingen University, Reutlingen, Germany DOI: 10.1109/ICMTS.2011.5976841 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Sensing mobility mismatch due to local interconnect mechanical stress in CMOS technology S. Blayac, C. Rivero1, P. Fornara1, L. Lopez1, N. Demange1 CMP/PS2, Ecole des Mines de Saint Etienne, Gardanne, France 1STMicroelectronics, Rousset, France DOI: 10.1109/ICMTS.2011.5976847 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | A simple system for on-die measurement of atto-Farad capacitance E. Baruch, S. Shperber, R. Levy, Y. Weizman, J. Fridburg, R. Marks Freescale Semiconductor Israel Limited, Herzliya, Israel DOI: 10.1109/ICMTS.2011.5976854 HOVER FOR ABSTRACT | PDF Xplore | |
| 2011 | Microsecond pulsed DC matching measurements on MOSFETs in strong and weak inversion P. Andricciola, H. Tuinhout, N. Wils, J. Schmitz Central Research and Development, NXP Semiconductors, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2011.5976866 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Global parameter extraction for a multi-gate MOSFETs compact model S. Yao, T. H. Morshed, D. D. Lu, S. Venugopalan, W. Xiong1, C. R. Cleavelin, A. M. Niknejad, C. Hu Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, USA 1SiTD, Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.2010.5466821 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Compact models of parasitic resistance of resistors for analog circuits K. Yamada Technology Foundation Dev. Op. Unit, Core Development Division, NEC Electronics Corporation Limited, Kawasaki, Kanagawa, Japan DOI: 10.1109/ICMTS.2010.5466818 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies N. Wils, H. Tuinhout, M. Meijer NXP Semiconductors Central Research and Development/Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2010.5466825 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Direct probing of trapped charge dynamics in SiN by Kelvin Force Microscopy E. Vianello, E. Nowak1, D. Mariolle1, N. Chevalier1, L. Perniola1, G. Molas1, J. P. Colonna1, F. Driussi, L. Selmi DIEGM, University of Udine-IUNET, Udine, Italy 1CEA-LETI Minatec Grenoble, Grenoble, France DOI: 10.1109/ICMTS.2010.5466851 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Methodology to evaluate long channel matching deterioration and effects of transistor segmentation on MOSFET matching H. Tuinhout, N. Wils, M. Meijer, P. Andricciola NXP Semiconductors Central Research and Development/Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2010.5466824 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Test structures to quantify contact placement-impacted drain current variations R. O. Topaloglu, Z. -Y. Wu, A. B. Icel Global Foundries, Inc., Sunnyvale, CA, USA DOI: 10.1109/ICMTS.2010.5466822 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | SIS wide-band model extraction methodology for SOI on-chip inductor R. O. Topaloglu, J. -S. Goo, A. L. S. Loke1, M. M. Oshima1, S. W. Sim1 Global Foundries, Inc., Sunnyvale, CA, USA 1Advanced Micro Devices, Inc., Sunnyvale, CA, USA DOI: 10.1109/ICMTS.2010.5466850 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Highly automated sequence for Phase Change Memory test structure characterization A. Toffoli, A. Fantini, G. Betti Beneventi1, L. Perniola, R. Kies, V. Vidal2, J. F. Nodin, V. Sousa, A. Persico, J. Cluzel, C. Jahan, S. Maitrejean, G. Reimbold, B. DeSalvo, F. Boulanger CEA-LETI Minatec Grenoble, Grenoble, France 1Universita degli Studi di Modena e Reggio Emilia, Reggio Emilia, Italy 2STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2010.5466865 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | New RF intrinsic parameters extraction procedure for advanced MOS transistors J. C. Tinoco, A. G. Martinez-Lopez1, M. Emam2, J. . -P. Raskin2 Departamento de Ingenieräa en Telecomunicaciones, División de Ingenieräa Eléctrica, Facultad de Ingenieräa, Universidad Nacional Auténoma de México, Mexicali, Mexico 1Col. Jardänes de San German, Puerto de Tuxpan s/n entre Puerto Tampico y Chetumal, Universidad Politécnica de la Región Ribereä±a, Tamaulipas, Mexico 2Microwave Laboratory, Université catholique de Louvain, Louvain-la-Neuve, Belgium DOI: 10.1109/ICMTS.2010.5466853 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | MOSFET-array for extracting parameters expressing SPICE-parameter variation K. Terada, N. Ekida, K. Tsuji, T. Tsunomura1, A. Nishida1 Faculty of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan 1MIRAI-Selete, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2010.5466855 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Test structures for characterization of through silicon vias M. Stucchi, D. Perry1, G. Katti2, W. Dehaene2 IMEC, Leuven, Belgium 1Qualcomm CDMA Technologies, San Diego, CA, USA 2ESAT Department, Katholieke Universiteit Leuven, Leuven, Belgium DOI: 10.1109/ICMTS.2010.5466841 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Kelvin resistor structures for the investigation of corner serif Proximity Correction S. Smith, A. Tsiamis, M. McCallum1, A. C. Hourd2, J. T. M. Stevenson, A. J. Walton Institute of Integrated Micro and Nano Systems (Part of the Joint Research Institute of Integrated Systems), School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, UK 1Nikon Precision Europe GmbH, HoustonSuite, Livingston, UK 2Division of Electronic Engineering & Physics, Harris Building, University of Dundee, Dundee, UK DOI: 10.1109/ICMTS.2010.5466866 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Fabrication of test structures to monitor stress in SU-8 films used for MEMS applications S. Smith, N. L. Brockie, J. Murray, C. J. Wilson1, A. B. Horsfall2, J. G. Terry, J. T. M. Stevenson, A. R. Mount3, A. J. Walton Institute of Integrated Micro and Nano Systems (Part of the Joint Research Institute of Integrated Systems), School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1IMEC, Leuven, Belgium 2School of Electrical, Electronic and Computer Engineering, Merz Court, University of Newcastle, Newcastle-upon-Tyne, UK 3School of Chemistry, Joseph Black Building, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2010.5466870 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Analysis of the performance of a micromechanical test structure to measure stress in thick electroplated metal films S. Smith, N. L. Brockie, J. Murray, C. J. Wilson1, A. B. Horsfall2, J. G. Terry, J. T. M. Stevenson, A. R. Mount3, A. J. Walton Institute of Integrated Micro and Nano Systems (Part of the Joint Research Institute of Integrated Systems), School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1IMEC, Leuven, Belgium 2School of Electrical, Electronic and Computer Engineering, Merz Court, University of Newcastle, Newcastle-upon-Tyne, UK 3School of Chemistry, Joseph Black Building, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2010.5466852 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | On the validity of bisection-based thru-only de-embedding T. Sekiguchi, S. Amakawa, N. Ishihara, K. Masu Integrated Research Institute, Tokyo Institute of Technology, Yokohama, Japan DOI: 10.1109/ICMTS.2010.5466857 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | A unique and accurate extraction technique of the asymmetric bottom-pillar resistance for the vertical MOSFET K. Sakui, T. Endoh Center of Interdisciplinary Research, JST-CREST, University of Tohoku, Sendai, Japan DOI: 10.1109/ICMTS.2010.5466812 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Characterization & modeling of gate-induced-drain-leakage with complete overlap and fringing model D. Rideau, V. Quenette, D. Garetto1, E. Dornel1, M. Weybright1, J. P. Manceau1, O. Saxod, C. Tavernier, H. Jaouen STMicroelectronics, Crolles CEDEX, France 1IBM France, Crolles, France DOI: 10.1109/ICMTS.2010.5466816 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | A test structure for integrated capacitor array matching characterization W. Posch, G. Promitzer, E. Seebacher Austria Microsystems AG, Austria DOI: 10.1109/ICMTS.2010.5466833 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | | Small embedded sensors for accurate temperature measurements in DMOS power transistors M. Pfost, D. Costachescu, A. Podgaynaya1, M. Stecher2, S. Bychikhin2, D. Pogany2, E. Gornik2 Infineon Technologies Romania, IFRO ATV TM, Bucharest, Romania 1Infineon Technologies AG, ATV PTP TSP, Neubiberg, Germany 2Institute of Solid-State Electronics, University of Technology, Vienna, Vienna, Austria DOI: 10.1109/ICMTS.2010.5466872 HOVER FOR ABSTRACT | PDF Xplore |
| 2010 | An efficient method of calibrating MOSFET capacitances by way of excluding intra- DUT parasitic contributions Y. Naruta, R. Koh, T. Iizuka NEC Electronics Corporation Limited, Kawasaki, Japan DOI: 10.1109/ICMTS.2010.5466828 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Fully understanding the mechanism of misalignment-induced narrow-transistor failure and carefully evaluating the misalignment-tolerant SRAM-cell layout S. Nakai, Y. Miyazaki, R. Nakamura, M. Suga, T. Tsuruta, M. Yasuda1, T. Kashiwagi, Y. Maki Fujitsu Microelectronics Limited, Japan 1Fujitsu VLSI Limited, Japan DOI: 10.1109/ICMTS.2010.5466834 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Correlation between Direct Charge Measurement (DCM) and LCR meter on deep submicron CMOS test structure capacitance measurement Y. Miyake, M. Goto, S. Fujii, H. Nishimura Agilent Technologies International Japan Limited, Japan DOI: 10.1109/ICMTS.2010.5466830 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | A Balanced-SeeSaw MEMS swing probe for vertical profilometry of deep micro structures Y. Mita, J. -B. Pourciel1, M. Kubota1, S. Ma1, S. Morishita1, A. Tixier-Mita1, T. Masuzawa1 University of Tokyo, Japan 1LAAS-CNRS, Université de Toulouse, France DOI: 10.1109/ICMTS.2010.5466858 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design N. Minas, G. Van der Plas, H. Oprins, Y. Yang1, C. Okoro1, A. Mercha, V. Cherman, C. Torregiani, D. Perry2, M. Cupac, M. Rakowski, P. Marchal IMEC, Belgium 1Katholieke Universiteit Leuven, Belgium 2Qualcomm CDMA Technologies, Inc., Leuven, Belgium DOI: 10.1109/ICMTS.2010.5466836 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Pulsed measurement method for characterizing chemical solutions using nanowire field effect transistors M. Mescher, B. Marcelis, M. de Wild, J. H. Klootwijk Micro Systems and Devices, Philips Research Eindhoven, Netherlands DOI: 10.1109/ICMTS.2010.5466863 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Orientation dependence and asymmetry of subthreshold characteristics in CMOSFETs T. Matsuda, Y. Matsumura, H. Iwata, T. Ohzone1 Department of Information Systems Engineering, Toyama Prefectural University, Toyama, Japan 1Dawn Enterprise, Nagoya, Japan DOI: 10.1109/ICMTS.2010.5466854 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Comprehensive quality assurance methodology for BSIM4.5 corner parameter extraction H. Masuda, S. Itoh1, H. Koike2, N. Wakita3, R. Inagaki4 Renesas Technology Corporation, Japan 1Seiko-Epson Corporation, Russia 2Semiconductor Technology, Academic Research Center, Japan 3Toshiba Corporation, Japan 4Rohm Company Limited, Thailand DOI: 10.1109/ICMTS.2010.5466819 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | A test vehicle and a two step procedure to evaluate a massive number of single-walled carbon nanotube field effect transistors I. Martin-Fernandez, M. Sansa, F. Perez-Murano, P. Godignon, E. Lora-Tamayo Instituto de Microelectrónica de Barcelona-Centro Nacional de Microelectrónica-Consejo Superior de Investigaciones Cientäficas, Cerdanyola del Valles, Spain DOI: 10.1109/ICMTS.2010.5466860 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Test structures for characterising the integration of EWOD and SAW technologies for microfluidics Y. Li, Y. Q. Fu1, B. W. Flynn, W. Parkes, Y. Liu1, S. Brodie1, J. G. Terry, L. I. Haworth, A. S. Bunting, J. T. M. Stevenson, S. Smith, A. J. Walton Institute of Integrated Micro and Nano Systems (IMNS), [Part of the Institute of Integrated Systems], School of Engineering, University of Edinburgh, UK 1Microsystems Engineering Centre, [Part of the Institute of Integrated Systems], School of Engineering and Physical Sciences, Heriot-Watt University, Edinburgh, UK DOI: 10.1109/ICMTS.2010.5466861 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | A bulk micromachined vertical nano-gap Pirani wide-range pressure test structure for packaged MEMS performance monitoring M. Kubota, T. Okada1, Y. Mita1, M. Sugiyama, Y. Nakano2 Institute of Engineering Innovation, Graduate School of Engineering, University of Tokyo, Bunkyo, Tokyo, Japan 1Department of Electrical Engineering and Information Systems, Graduate School of Engineering, University of Tokyo, Bunkyo, Tokyo, Japan 2Research Center of Advanced Science and Technology, University of Tokyo, Bunkyo, Tokyo, Japan DOI: 10.1109/ICMTS.2010.5466871 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Investigation on the field leakage current in 0.35μm CMOS technology at high temperature S. T. Kong, P. S. Ronald, C. Lee X-FAB Semiconductor Foundries AG, Plymouth, UK DOI: 10.1109/ICMTS.2010.5466849 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | An embedded process monitor test chip architecture S. Idgunji, V. Chandra, C. Pietrzyk, I. Iqbal, R. Aitken, G. Yeric1 Research and Development, ARM, Inc., San Jose, CA, USA 1Research and Development, ARM, Inc., Austin, TX, USA DOI: 10.1109/ICMTS.2010.5466842 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Fast RF-CV characterization through high-speed 1-port S-parameter measurements R. W. Herfst, P. G. Steeneken1, M. P. J. Tiggelman, J. Stulemeijer2, J. Schmitz MESA Institute of Nanotechnology, University of Twente, Enschede, Netherlands 1NXP Semiconductors, Eindhoven, Netherlands 2Surface Acoustic Wave Components Division, EPCOS Netherlands B.V., Nijmegen, Netherlands DOI: 10.1109/ICMTS.2010.5466829 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Novel test structures for temperature budget determination during wafer processing E. J. Faber, R. A. M. Wolters1, J. Schmitz MESA Institute of Nanotechnology, Semiconductor Components Group, University of Twente, Enschede, Netherlands 1NXP Semiconductors, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2010.5466867 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | A universal structure for SRAM cell characterization X. Deng, T. W. Houston, A. Duong, W. K. Loh Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.2010.5466815 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device S. H. Choi, Y. H. Park, C. H. Park, S. H. Lee, M. H. Yoo, G. T. Kim1 CAE, Semiconductor Research and Development Center, Samsung Electronics Company Limited, Hwasung, South Korea 1School of Electrical Engineering, Korea University, South Korea DOI: 10.1109/ICMTS.2010.5466864 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Electrical characterization of novel PMNT thin-films W. Chen, K. G. McCarthy1, M. Çopuroğlu, S. O'Brien, R. Winfield, A. Mathewson Tyndall National Institute, University College Cork, Ireland 1Department of Electrical & Electronic Engineering, University College Cork, Ireland DOI: 10.1109/ICMTS.2010.5466848 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Combined test structure for systematic and stochastic mosfets and gate resistance process variation assessment L. Bortesi, L. Vendrame, G. Fontana Numonyx, Research and Development Technology Development, Agrate-Brianza, Italy DOI: 10.1109/ICMTS.2010.5466810 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | On-wafer inductance and resistance characterization of sub-5pH deep silicon via (DSV) V. Blaschke, R. Zwingman TowerJazz Limited, Newport Beach, CA, USA DOI: 10.1109/ICMTS.2010.5466839 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Generation, elimination and utilization of harmonics in ring oscillators M. Bhushan, M. B. Ketchen1 IBM Systems and Technology Group, NY, USA 1T.J. Watson Research Center, IBM Research GmbH, Yorktown Heights, NY, USA DOI: 10.1109/ICMTS.2010.5466847 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | On-chip in-situ measurements of Vth and AC gain of differential pair transistors Y. Bando, S. Takaya, T. Ohkawa1, T. Takaramoto1, T. Yamada1, M. Souda1, S. Kumashiro1, M. Nagata Department of Computer Science and Systems Engineering, Kobe University, Japan 1MIRAI-Selete, Japan DOI: 10.1109/ICMTS.2010.5466809 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Test circuit for measuring single-event-induced charge sharing in deep-submicron technologies O. A. Amusan, B. L. Bhuva, M. C. Casey1, M. J. Gadlage, D. McMorrow2, J. S. Melinger2, L. W. Massengill Electrical Engineering and Computer Science Department, Vanderbilt University, Nashville, TN, USA 1NASA, USA 2Naval Research Laboratory, Inc., Washington D.C., DC, USA DOI: 10.1109/ICMTS.2010.5466844 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | Ring oscillator based embedded structure for decoupling PMOS/NMOS degradation with switching activity replication F. Ahmed, L. Milor School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA DOI: 10.1109/ICMTS.2010.5466845 HOVER FOR ABSTRACT | PDF Xplore | |
| 2010 | A test structure for statistical evaluation of pn junction leakage current based on CMOS image sensor technology K. Abe, T. Fujisawa, H. Suzuki, S. Watabe, R. Kuroda, S. Sugawa, A. Teramoto1, T. Ohmi1 Graduate School of Engineering, University of Tohoku, Japan 1New Industry Creation Hatchery Center, University of Tohoku, Japan DOI: 10.1109/ICMTS.2010.5466868 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Automated Test Structure Generation for Characterizing Plasma Induced Damage in MOSFET D vices T. Zwingman, A. Gabrys, A. J. West National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2009.4814619 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Improved Parameter Extraction Procedure for PSP-Based MOS Varactor Model Z. Zhu, J. Victory1, S. Chaudhry2, L. Dong2, Z. Yan2, J. Zheng2, W. Wu, X. Li, Q. Zhou, P. Kolev3, C. C. McAndrew, G. Gildenblat Department of Electrical Engineering, Arizona State University, Tempe, AZ, USA 1Sentinel IC Technologies, Irvine, CA, USA 2Jazz Semiconductor, Newport Beach, CA, USA 3RFMD, Inc., San Diego, CA, USA DOI: 10.1109/ICMTS.2009.4814629 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Parameter extraction for the PSP MOSFET model by the combination of genetic and Levenberg-Marquardt algorithms Q. Zhou, W. Yao, W. Wu, X. Li, Z. Zhu, G. Gildenblat Ira A. Fulton School of Engineering, Department of Electrical Engineering, Arizona State University, Tempe, AZ, USA DOI: 10.1109/ICMTS.2009.4814627 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Extracting Resistances of Carbon Nanostructures in Vias W. Wu, S. Krishnan, K. Li, X. Sun, R. Wu, T. Yamada, C. Y. Yang Center of Nanostructures, Santa Clara University, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2009.4814603 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Demonstration of a Sub-micron Damascene Cu/Low-k Mechanical Sensor to Monitor Stress in BEOL Metallization C. J. Wilson, K. Croes, Z. Tokei, G. P. Beyer, A. B. Horsfall1, A. G. O'Neill1 IMEC vzw, Leuven, Belgium 1School of Electrical, Electronic, and Computer Engineering, University of Newcastle, Newcastle-upon-Tyne, UK DOI: 10.1109/ICMTS.2009.4814604 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | A Test Structure for Statistical Evaluation of Characteristics Variability in a Very Large Number of MOSFETs S. Watabe, S. Sugawa, K. Abe, T. Fujisawa, N. Miyamoto1, A. Teramoto1, T. Ohmi2 Graduate School of Engineering, University of Tohoku, Sendai, Japan 1New Industry Creation Hatchery Center, University of Tohoku, Sendai, Japan 2WPI Research center, University of Tohoku, Sendai, Japan DOI: 10.1109/ICMTS.2009.4814622 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | High precision on-wafer backend capacitor mismatch measurements using a benchtop semiconductor characterization system H. Tuinhout, F. van Rossem, N. Wils NXP Semiconductors Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2009.4814598 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Measurement of MOSFET C-V Curve Variation Using CBCM Method K. Tsuji, K. Terada, T. Nakamoto, T. Tsunomura1, A. Nishida1 Graduate School of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan 1MIRAI-Selete, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2009.4814615 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Electrical Test Structures for Investigating the Effects of Optical Proximity Correction A. Tsiamis, S. Smith, M. McCallum1, A. C. Hourd2, J. T. M. Stevenson, A. J. Walton Institute of Integrated Micro and Nano Systems, School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1Nikon Precision Europe GmbH, West Lothian, UK 2Compugraphics International Limited, Glenrothes, Fife, UK DOI: 10.1109/ICMTS.2009.4814632 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | In-Situ Silicon Integrated Tuner for Automated On-Wafer MMW Noise Parameters Extraction using Multi-Impedance Method for Transistor Characterization Y. Tagro, D. Gloria1, S. Boret1, Y. Morandini1, G. Dambrine Institut d'Electronique, de Microélectronique et de Nanotechnologie, IEMN, Villeneuve d'Ascq, France 1Technology Research and Development-TPS, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2009.4814637 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | | Non-Contact, Pad-less Measurement Technology and Test Structures for Characterization of Cross-Wafer and In-Die Product Variability G. Steinbrueck, J. S. Vickers, M. Babazadeh, M. M. Pelella, N. Pakdaman Tau-Metrix, Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS.2009.4814617 HOVER FOR ABSTRACT | PDF Xplore |
| 2009 | Characterization and modeling of mechanical stress in silicon-based devices A. Spessot, A. Colombi, G. P. Carnevale, P. Fantini Numonyx Research and Development-Technology development, Agrate-Brianza, Italy DOI: 10.1109/ICMTS.2009.4814628 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Application of Matching Structures to Identify the Source of Systematic Dimensional Offsets in GHOST Proximity Corrected Photomasks S. Smith, A. Tsiamis, M. McCallum1, A. C. Hourd2, J. T. M. Stevenson, A. J. Walton Institute of Integrated Micro and Nano Systems, School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, UK 1Nikon Precision Europe GmbH, Livingston, UK 2Eastfield Industrial Estate, Compugraphics International Limited, Glenrothes, Fife, UK DOI: 10.1109/ICMTS.2009.4814609 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Application of a Micromechanical Test Structure to the Measurement of Stress in an Electroplated Permalloy Film S. Smith, N. L. Brockie, J. G. Terry, N. Wang, A. B. Horsfall1, A. J. Walton Institute of Integrated Micro and Nano Systems, School of Engineering, Scottish Microelectronics Centre, University of Edinburgh, UK 1School of Electrical, Electronic and Computer Engineering, Merz Court, University of Newcastle, Newcastle-upon-Tyne, UK DOI: 10.1109/ICMTS.2009.4814614 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Estimating MOSFET Leakage from Low-cost, Low-resolution Fast Parametric Test S. Saxena, T. Uezono, R. Vallishayee1, R. Lindley, A. Swimmer, S. Winters PDF Solutions, Incorporated, Richardson, TX, USA 1PDF Solutions, Incorporated, San Jose, CA, USA DOI: 10.1109/ICMTS.2009.4814623 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Nanomechanical test structure for optimal alignment in stencil-based lithography M. Sansa, J. Arcamone, J. Verd1, A. Uranga1, G. Abadal, E. Lora-Tamayo, N. Barniol1, M. A. F. van den Boogaart2, V. Savu2, J. Brugger2, F. Perez-Murano Instituto de Microelectronica de Barcelona CNM-IMB (CSIC), Campus UAB, Bellaterra (Barcelona), Spain 1Dept.Electronics Engineering, Universitat Autonoma de Barcelona, ETSE-UAB, Bellaterra (Barcelona), Spain 2Microsystems Laboratory (LMISl), EPFL, EPFL, Lausanne, Switzerland DOI: 10.1109/ICMTS.2009.4814631 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Fast Embedded Characterization of FEOL Variations in MOS Devices F. Rigaud, J. M. Portal, P. Dreux1, J. Vast1, H. Aziza, G. Bas1 IM2NP-Laboratoire Mat érioux et Micro éelectronique de Provence, IMT-Technopôle de Château Gombert, UMR CNRS 6242, Marseilles, France 1STMicroelectronics, Rousset, France DOI: 10.1109/ICMTS.2009.4814642 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Test Structure for High-Voltage LD-MOSFET Mismatch Characterization in 0.35 um HV-CMOS Technology W. Posch, C. Murhammer, E. Seebacher Austria Microsystems AG, Unterpremstatten, Austria DOI: 10.1109/ICMTS.2009.4814618 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | An enhanced model for thin film resistor matching T. G. O'Dwyer, M. P. Kennedy1 Analog Devices Inc.orporated, Wilmington, MA, USA 1Department of Microelectronic Engineering, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.2009.4814608 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Static Noise Margin Evaluation Method Based on Direct Polynomial-Curve-Fitting with Universal SRAM Cell Inverter TEG Measurement K. Nakamura, K. Noda, H. Koike1 Center of Microelectronic Systems, Kyushu Institute of Technology, Fukuoka, Japan 1Fukuoka Industry Science and Technology Foundation, Fukuoka, Japan DOI: 10.1109/ICMTS.2009.4814599 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Benefit of Direct Charge Measurement (DCM) on Interconnect Capacitance Measurement Y. Miyake, M. Goto Agilent Technologies International Japan Limited, Hachioji, Japan DOI: 10.1109/ICMTS.2009.4814644 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Mismatch Measure Improvement Using Kelvin Test Structures in Transistor Pair Configuration in Sub-Hundred Nanometer MOSFET Technology C. M. Mezzomo, M. Marin, C. Leyris, G. Ghibaudo1 STMicroelectronics, Crolles, France 1Minatec, IMEP-LAHC GRENOBLE, Grenoble, France DOI: 10.1109/ICMTS.2009.4814611 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | An Analysis of Temperature Impact on MOSFET Mismatch S. Mennillo, A. Spessot, L. Vendrame, L. Bortesi Research and Development-Technology Development, Numonyx, Agrate-Brianza, Italy DOI: 10.1109/ICMTS.2009.4814610 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | A Test Structure for Spectrum Analysis of Hot-Carrier-Induced Photoemission from Scaled MOSFETs under DC and AC Operation T. Matsuda, T. Maezawa, H. Iwata, T. Ohzone1 Department of Information Systems Engineering, Toyama Prefectural University, Imizu, Toyama, Japan 1Dawn Enterprise, Nagoya, Japan DOI: 10.1109/ICMTS.2009.4814613 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Test Structure to Extract Circuit Models of Nanostructures Operating at High Frequencies F. R. Madriz, J. R. Jameson, S. Krishnan, X. Sun, C. Y. Yang Center of Nanostructures, Santa Clara University, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2009.4814605 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | A Test Structure for Assessing Individual Contact Resistance F. Liu, K. Agarwal IBM Austin Research Laboratory, Austin, TX, USA DOI: 10.1109/ICMTS.2009.4814641 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Test Chip to Evaluate Measurement Methods for Small Capacitances J. J. Kopanski, M. Y. Afridi, C. Jiang1, C. A. Richter Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1University of Illinois, Urbana-Champaign, Champaign, USA DOI: 10.1109/ICMTS.2009.4814606 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Addressable Arrays Implemented with One Metal Level for MOSFET and Resistor Variability Characterization M. B. Ketchen, M. Bhushan1, G. Costrini IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA 1IBM Systems and Technology Group, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.2009.4814600 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Test Structures Utilizing High-Precision Fast Testing For 32nm Yield Enhancement M. Karthikeyan, L. Medina, E. Shiling IBM Systems and Technology Group, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.2009.4814624 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Advanced Method for Measuring Ultra-Low Contact Resistivity Between Silicide and Silicon Based on Cross Bridge Kelvin Resistor T. Isogai, H. Tanaka1, A. Teramoto1, T. Goto1, S. Sugawa, T. Ohmi2 Graduate School of Engineering, University of Tohoku, Japan 1New Industry Creation Hatchery Center, University of Tohoku, Japan 2WPI Research Center, University of Tohoku, Japan DOI: 10.1109/ICMTS.2009.4814621 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Array Test Structure for Ultra-Thin Gate Oxide Degradation Issues K. M. Hafkemeyer, A. Domdey, D. Schroeder, W. H. Krautschneider Institute of Nanoelectronics, Hamburg University of Technology, Hamburg, Germany DOI: 10.1109/ICMTS.2009.4814616 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | | Four point probe structures with buried electrodes for the electrical characterization of ultrathin conducting films A. W. Groenland, R. A. M. Wolters1, A. Y. Kovalgin, J. Schmitz MESA Institute of Nanotechnology, Semiconductor Components, University of Twente, Enschede, Netherlands 1NXP-TMSC Research Center, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2009.4814639 HOVER FOR ABSTRACT | PDF Xplore |
| 2009 | Characterization and Model Parameter Extraction of Symmetrical Centre Tapped Inductor using Build in Mixed Mode and Pure Differential S-Parameters F. Gianesello, Y. Morandini, S. Boret, D. Gloria Technology R&D, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2009.4814636 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Accurate Time Constant of Random Telegraph Signal Extracted by a Sufficient Long Time Measurement in Very Large-Scale Array TEG T. Fujisawa, K. Abe, S. Watabe, N. Miyamoto1, A. Teramoto1, S. Sugawa, T. Ohmi1 Graduate School of Engineering, University of Tohoku, Sendai, Japan 1New Industry Creation Hatchery Center, University of Tohoku, Sendai, Japan DOI: 10.1109/ICMTS.2009.4814601 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Test Structure Design, Extraction, and Impact Study of FEOL Capacitance Parameters in Advanced 45nm Technology S. Ekbote, P. Sadagopan, Y. Chen, W. Sy, R. Zhang, M. Han QUALCOMM, Inc.orporated, San Diego, CA, USA DOI: 10.1109/ICMTS.2009.4814647 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | 4K-cells Resistive and Charge-Base-Capacitive Measurement Test Structure Array (R-CBCM-TSA) for CMOS Logic Process Development, Monitor and Model K. Y. Y. Doong, K. -J. Chang1, S. . -C. Lin, H. C. Tseng, A. Dagonis, S. Pan Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan 1Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2009.4814645 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Mapping the Edge Roughness of Test-Structure Features for Nanometer-Level CD Reference-Materials M. W. Cresswell, M. Davidson, G. I. Mijares, R. A. Allen, J. Geist, M. Bishop1 Semiconductor Electronics Division, Electronics and Electrical Engineering Laboratory, National Institute for Standards and Technology, Gaithersburg, MD, USA 1International Sematech, Austin, TX, USA DOI: 10.1109/ICMTS.2009.4814633 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Practical Considerations for Measurements of Test Structures for Dielectric Characterization W. Chen, K. G. McCarthy, A. Mathewson Tyndall National Institute and Department of Electrical & Electronic Engineering, University College Cork, Ireland DOI: 10.1109/ICMTS.2009.4814646 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Efficient Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultra-Thin Oxide Partially-Depleted (PD) SOI Floating Body CMOS D. Chen, R. Lee, Y. C. Liu, G. S. Lin, M. C. Tang, M. F. Wang, C. S. Yeh, S. C. Chien Advanced Technology Development Division, United Microelectronics Corporation Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2009.4814626 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | Metal and Dielectric Thickness: a Comprehensive Methodology for Back-End Electrical Characterization L. Bortesi, L. Vendrame Numonyx, Research and Development Technology Development, Agrate-Brianza, Italy DOI: 10.1109/ICMTS.2009.4814640 HOVER FOR ABSTRACT | PDF Xplore | |
| 2009 | S-Parameter-Based Modal Decomposition of Multiconductor Transmission Lines and Its Application to De-Embedding S. Amakawa, K. Yamanaga, H. Ito1, T. Sato, N. Ishihara, K. Masu2 Integrated Research Institute, Tokyo Institute of Technology, Japan 1Precision and Intelligence Laboratory, Tokyo Institute of Technology, Japan 2Tokyo Kogyo Daigaku, Meguro-ku, Tokyo, JP DOI: 10.1109/ICMTS.2009.4814635 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Physics and modeling of transistor matching degradation under matched external stress Xiaoju Wu, Zhenwu Chen, P. Madhani Analog Technology Development, Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.2008.4509344 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Influence of STI stress on drain current matching in advanced CMOS N. Wils, H. Tuinhout, M. Meijer1 NXP-TMSC Research Center, Eindhoven, Netherlands 1NXP Semiconductors Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2008.4509345 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | A novel high speed automatic layout system to place and route test structures for parametric test capability A. J. West, S. Mondal, D. Patra, K. Goswami, S. Sural1 Indian Institute of Technology, Kharagpur, India 1National Semiconductor Corporation, Santa Clara, USA DOI: 10.1109/ICMTS.2008.4509316 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Prediction of stress-induced characteristic changes for small-scale analog IC Naohiro Ueda, Eri Nishiyama, Hideyuki Aota, Hirobumi Watanabe Electronic Devices Company, Ricoh Company Limited, Kato, Hyogo, Japan DOI: 10.1109/ICMTS.2008.4509323 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Investigation of Electrical and Optical CD Measurement Techniques for the Characterisation of On-Mask GHOST Proximity Corrected Features A. Tsiamis, S. Smith1, M. McCallum2, A. C. Hourd3, O. Toublan3, J. T. M. Stevenson3, A. J. Walton3 French Branchraphics, Mentor Limited, Saint Ismier, France 1Eastfield Industrial Estate, Compugraphics International Limited, Glenrothes, Fife, UK 2Nikon Precision Europe GmbH, West Lothian, UK 3Institute of Integrated Micro and Nano Systems, School of Engineering and Electronics, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2008.4509310 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | 2.6-GHz RF inductive power delivery for contactless on-wafer characterization J. Tompson, A. Dolin1, P. Kinget Department of Electrical Engineering, Columbia University, New York, NY, USA 1Anadigics, Warren, NJ, USA DOI: 10.1109/ICMTS.2008.4509334 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Test structure for characterizing metal thickness in damascene CMP technology A. Toffoli, S. Maitrejean, J. D. de Pontcharra, F. de Crecy, D. Bouchu, L. Arnaud, F. Boulanger CEA-LETI/MINATEC, Grenoble, France DOI: 10.1109/ICMTS.2008.4509340 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Identifying dielectric and resistive electrode losses in high-density capacitors at radio frequencies M. P. J. Tiggelman, K. Reimann1, J. Liu1, M. Klee, W. Keur2, R. Mauczock2, J. Schmitz2, R. J. E. Hueting Philips Research, Eindhoven, Netherlands 1NXP Semiconductors Research, Eindhoven, Netherlands 2Department of Semiconductor Components,Institute for Nanotechnology, University of Twente, MESA Research Institute, Enschede, Netherlands DOI: 10.1109/ICMTS.2008.4509337 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Mismatch characterization of a high precision resistor array test structure Weidong Tian, P. Steinmann, E. Beach, I. Khan, P. Madhani Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.2008.4509307 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Fully considered layout variation analysis and compact modeling of MOSFETs and its application to circuit simulation Takuji Tanaka, Akira Satoh, Mitsuru Yamaji1, Osamu Yamasaki, Hiroshi Suzuki1, Tsuyoshi Sakata, Yoshio Inoue, Masaru Ito2, Seiichiro Yamaguchi2, Hiroshi Arimoto Fujitsu Laboratories Limited, Akiruno, Tokyo, Japan 1FUJITSU VLSI Limited, Akiruno, Tokyo, Japan 2FUJITSU VLSI Laboratories Limited, Akiruno, Tokyo, Japan DOI: 10.1109/ICMTS.2008.4509342 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Circular Geometry MOS Transistor Analysis of SOI Substrates for High Energy Physics Particle Detectors S. L. Suder, F. H. Ruddell, J. H. Montgomery1, B. M. Armstrong1, H. S. Gamble1, G. Casse1, T. Bowcock1, P. P. Allport Department of Physics, University of Liverpool, UK 1Northern Ireland Semiconductor Research Centre, Queen''s University Belfast, Belfast, UK DOI: 10.1109/ICMTS.2008.4509322 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | A study of cross-bridge kelvin resistor structures for reliable measurement of low contact resistances N. Stavitski, J. H. Klootwijk1, H. W. van Zeijl2, A. Y. Kovalgin, R. A. M. Wolters3 MESA + Institute for Nanotechnology, University of Twente, Enschede, The Netherlands 1Philips Research, High Tech Campus 4, Eindhoven, The Netherlands 2DIMES, Delft University of Technology, Delft, CT, The Netherlands 3NXP Research Eindhoven, Eindhoven, AE, The Netherlands DOI: 10.1109/ICMTS.2008.4509338 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | On-mask mismatch resistor structures for the characterisation of maskmaking capability S. Smith, A. Tsiamis1, M. McCallum2, A. C. Hourd2, J. T. M. Stevenson, A. J. Walton, S. Enderling Institute of Integrated Micro and Nano Systems, The University of Edinburgh, UK 1Nikon Precision Europe GmbH, West Lothian, UK 2Nikon Precision Europe GmbH, Appleton Place, Appleton Parkway, Livingston, West Lothian, UK DOI: 10.1109/ICMTS.2008.4509343 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Comparison of measurement techniques for advanced photomask metrology S. Smith, A. Tsiamis, M. McCallum1, A. C. Hourd2, J. T. M. Stevenson3, A. J. Walton, R. G. Dixson, R. A. Allen, J. E. Potzick2, M. W. Cresswell2, N. G. Orji2 National Institute for Standards and Technology, Gaithersburg, MD, USA 1Eastfield Industrial Estate, Compugraphics International Limited, Glenrothes, Fife, UK 2Institute of Integrated Micro and Nano Systems, School of Engineering and Electronics Scottish Microelectronics Centre, University of Edinburgh, UK 3Nikon Precision Europe GmbH, West Lothian, UK DOI: 10.1109/ICMTS.2008.4509311 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | A novel biasing technique for addressable parametric arrays B. Smith, U. Annamalai1, A. Arriordaz, V. Kolagunta, J. Schmidt, M. Shroff Freescale Semiconductor, Austin, TX, USA 1University of Arkansas, Austin, TX, USA DOI: 10.1109/ICMTS.2008.4509333 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Comb capacitor structures for measurement of post-processed layers D. Roy, J. H. Klootwijk1, N. A. M. Verhaegh, H. H. A. J. Roosen2, R. A. M. Wolters NXP Semiconductors, Eindhoven, The Netherlands 1NXP Semiconductors Research, Eindhoven, Netherlands 2Philips Research, Eindhoven, The Netherlands DOI: 10.1109/ICMTS.2008.4509339 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Mixed test structure for soft and hard defect detection F. Rigaud, J. M. Portal, H. Aziza, D. Nee1, J. Vast1, F. Argoud1, B. Borot2 IMT-Technopole de Chateau Gombert, Institut Materiaux Microelectronique Nanosciences de Provence, UMR CNRS 6242, Marseilles, France 1ST Microelectronics, ZI Rousset, Rousset, France 2STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2008.4509313 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Test structure definition for dummy metal filling strategy dedicated to advanced integrated RF inductors C. Pastore, F. Gianesello, D. Gloria, E. Serret, P. Benech1 STMicroelectronics Group, Crolles, France 1IMEP, Grenoble, France DOI: 10.1109/ICMTS.2008.4509341 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Advanced test structure design for dielectric characterisation of novel high-k materials J. A. O'Sullivan, Wenbin Chen1, K. G. McCarthy2, G. M. Cream2 Dept. of Electrical and Electronic Engineering, University College, Cork, Ireland 1Department of Electrical and Electronic Engineering, University College Cork, Ireland 2Tyndall National Institute, Ireland DOI: 10.1109/ICMTS.2008.4509335 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Life condition monitoring on smart power devices using a sequence of current and charge-based capacitance measurements Zhenqiu Ning, E. de Vylder, F. Bauwens, B. Vlachakis, H. -X. Delecourt, R. Gillon, P. Van Torre1, D. Hegsted AMI Semiconductor Belgium bvba, Oudenaarde, Belgium 1Hogeschool GENT, GENT, Belgium DOI: 10.1109/ICMTS.2008.4509312 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Test circuit for measuring pulse widths of single-event transients causing soft errors B. Narasimham, M. J. Gadlage, B. L. Bhuva, R. D. Schrimpf, L. W. Massengill, W. T. Holman, A. F. Witulski, K. F. Galloway Dept. of Electrical Engineering and Computer Science, Vanderbilt University, Nashville, TN, USA DOI: 10.1109/ICMTS.2008.4509329 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | A study of variation in characteristics and subthreshold humps for 65-nm SRAM using newly developed SRAM cell array test structure A. Mizumura, T. Suzuki, T. Arima1, H. Maeda1, H. Ammo Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation, Astugi, Kanagawa, Japan 1Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation, Sony LSI Design Incorporated, Astugi, Kanagawa, Japan DOI: 10.1109/ICMTS.2008.4509306 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | A test structure for channel length engineering of NAND gates in standard cell library T. Matsuda, Y. Sugiyama, J. Takakuwa, H. Iwata, T. Ohzone1 Department of Information Systems Engineering, Toyama Prefectural University, Japan 1Dawn Enterprise, Nagoya, Japan DOI: 10.1109/ICMTS.2008.4509317 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Test structures for the evaluation of 3D chip interconnection schemes A. Mathewson, J. Brun1, R. Franiatte1, A. Nowodzinski1, R. Ancient1, N. Sillon1, F. Depoutot2, B. Dubois-Bonvalot2 Tyndall National Institute, Cork, Ireland 1CEA-Leti-Minatec, Grenoble, France 2Hardware Security Research Group Gemalto, Grenoble, France DOI: 10.1109/ICMTS.2008.4509325 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | An evaluation of test structures for measuring the contact resistance of 3-D bonded interconnects H. Lin, S. Smith, J. T. M. Stevenson, A. M. Gundlach, C. C. Dunare, A. J. Walton Institute for Integrated Micro and Nano Systems, Part of the Institute for Integrated Systems, School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2008.4509326 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Conduit Diffusion of Dopants in Tungsten Silicide Layers S. Liao, M. Bain, P. Baine, D. W. McNeill, B. M. Armstrong, H. S. Gamble Northern Ireland Semiconductor Research Centre, Queen's University of Belfast, Northern Ireland, UK DOI: 10.1109/ICMTS.2008.4509315 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Test structure for characterising low voltage coplanar EWOD system Yifan Li, Mita Yoshio1, L. Haworth, W. Parkes, Masanori Kubota1, A. Walton School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK 1University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2008.4509318 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Characterization of MOSFETs intrinsic performance using in-wafer advanced Kelvin-contact device structure for high performance CMOS LSIs Rihito Kuroda, Akinobu Teramoto1, Takanori Komuro2, Weitao Cheng, Syunichi Watabe, Ching Foa Tye, Shigetoshi Sugawa1, Tadahiro Ohmi1 Graduate School of Engineering, University of Tohoku, Sendai, Japan 1New industry Creation Hatchery Center, University of Tohoku, Japan 2Agilent Technologies International Japan Limited, Japan DOI: 10.1109/ICMTS.2008.4509331 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Short-flow test chip utilizing fast testing for defect density monitoring in 45nm M. Karthikeyan, W. Cote, L. Medina, E. Shiling, A. Gasasira, A. Henning, W. Ferrante, M. Craig, T. Merbeth IBM Systems and Technology Group, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.2008.4509314 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Operational amplifier based test structure for transistor threshold voltage variation B. L. Ji, D. J. Pearson, I. Lauer, F. Stellari, D. J. Frank, L. Chang, M. B. Ketchen IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA DOI: 10.1109/ICMTS.2008.4509305 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Characterization of T-shaped terminal impedances of differential short stubs in advanced CMOS technology Chiaki Inui, Minoru Fujishima School of Frontier Science, University of Tokyo, Kashima, Chiba, Japan DOI: 10.1109/ICMTS.2008.4509336 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | | High density test structure array for accurate detection and localization of soft fails C. Hess, M. Squcciarini, Shia Yu1, J. Burrows, Jianjun Cheng, R. Lindley1, A. Swimmer1, S. Winters1 PDF Solutions, Inc.orporated, San Diego, CA, USA 1PDF Solutions, Inc.orporated, San Jose, CA, USA DOI: 10.1109/ICMTS.2008.4509327 HOVER FOR ABSTRACT | PDF Xplore |
| 2008 | Rapid characterization of parametric distributions using a multi-meter J. Hayes, K. Agarwal, S. Nassif IBM Austin Research Laboratory, Austin, TX, USA DOI: 10.1109/ICMTS.2008.4509308 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Highly automated test chip layout and test plan development for parametric electrical test A. Gabrys, W. Greig, A. J. West, P. Lindorfer, W. French National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2008.4509321 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | New Y-function-based methodology for accurate extraction of electrical parameters on nano-scaled MOSFETs D. Fleury, A. Cros, H. Brut, G. Ghibaudo1 STMicroelectronics Group, Crolles, France 1IMEP MINATEC, Grenoble, France DOI: 10.1109/ICMTS.2008.4509332 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | New method for non destructive snap-back characterization in multi-finger power MOSFETs F. Dieudonne, A. Constant, J. Rosa, B. Gautheron, J. -F. Revel ST Microelectronics, Crolles Site, Crolles, France DOI: 10.1109/ICMTS.2008.4509328 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Measurement and optimisation of bond strength for anodic bonding of glass to dielectric thin films G. Cummins, H. Lin, A. J. Walton Institute of Micro and Nano Systems Institute of Integrated Systems, University of Edinburgh, UK DOI: 10.1109/ICMTS.2008.4509324 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Beyond van der Pauw: Sheet resistance determination from arbitrarily shaped planar four-terminal devices with extended contacts M. Cornils, O. Paul1 Albert-Ludwigs-Universitat Freiburg, Freiburg im Breisgau, Baden-Württemberg, DE 1Department of Microsystems Engineering (IMTEK), University of Freiburg, Germany DOI: 10.1109/ICMTS.2008.4509309 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Measurement of the MOSFET drain current variation under high gate voltage Tetsuo Chagawa, Kazuo Terada1, Jianyu Xiang1, Katsuhiro Tsuji, Takaaki Tsunomura, Akio Nishida Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan 1MIRAI-Selete, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2008.4509319 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | Spacing impact on MOSFET mismatch A. Cathignol, S. Mennillo1, S. Bordez2, L. Vendrame1, G. Ghibaudo3 STMicroelectronics, Crolles, FR 1STMicroelectronics, Advanced R&D, NVMTD-FMG, Agrate, Italy 2STMicroelectronics-Crolles 2 Alliance, Crolles, France 3IMEP, Minatec, INPG Paris Louis Néel, Grenoble, France DOI: 10.1109/ICMTS.2008.4509320 HOVER FOR ABSTRACT | PDF Xplore | |
| 2008 | CMOS latch metastability characterization at the 65-nm-technology node M. Bhushan, M. B. Ketchen1, K. K. Das1 IBM Systems and Technology Group, Hopewell Junction, NY, USA 1IBM Research, Thomas J. Watson Research Center, Yorktown Heights, NY, USA DOI: 10.1109/ICMTS.2008.4509330 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | A Transmission-Line Based Technique for De-Embedding Noise Parameters K. H. K. Yau, A. M. Mangan, P. Chevalier1, P. Schvan2, S. P. Voinigescu Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada 1STMicroelectronics, Crolles, France 2NORTEL, 3500 Carling Ave., Ottawa ON, K2H 8E9, Canada DOI: 10.1109/ICMTS.2007.374491 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Impact of Sinter Process and Metal Coverage on Transistor Mismatching and Parameter Variations in Analog CMOS Technology X. Wu, J. Trogolo1, F. Inoue2, Z. Chen1, P. Jones-Williams1, I. Khan1, P. Madhani Mixed Signal Technology Development, Dallas, TX, USA 1Mixed Signal Technology Development, TTexas Instruments, Dallas, TX, USA 2MIHO8, Inashiki-gun, Ibaraki-Ken, Japan DOI: 10.1109/ICMTS.2007.374457 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | A New Test Structure for Shallow Trench Isolation (STI) Depth Monitor Q. Wang, S. Pendharkar, B. Hu, B. Russell, P. Jones-Williams Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.2007.374449 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Excess Base Current Model for Gamma-Irradiated SiGe Bipolar Transistors M. Ullan, J. P. Alegre1, S. Diez, G. Pellegrini, F. Campabadal, M. Lozano, E. Lora-Tamayo Centro Nacional de Microelectróica, CSIC, Barcelona, Spain 1Dpto. Ing. Electrónica y Comunicaciones, Universidad de Zaragoza, Zaragoza, Spain DOI: 10.1109/ICMTS.2007.374475 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Development of Eectrilcal On-Mask CD Test Structures Based on Optical Metrology Features A. Tsiamis, S. Smith, M. McCallum1, A. C. Hourd2, O. Toublan3, J. T. M. Stevenson, A. J. Walton Institute of Integrated Micro and Nano Systems, School of Engineering and Electronics, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1Nikon Precision Europe GmbH, West Lothian, UK 2Eastfield Industrial Estate, Compugraphics International Limited, Glenrothes, Fife, UK 3French Branch, Mentor Graphics (Ireland) Limited, Saint Ismier, France DOI: 10.1109/ICMTS.2007.374477 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Reducing AC impedance measurement errors caused by the DC voltage dependence of broadband high-voltage bias-tees M. P. J. Tiggelman, K. Reimann1, J. Schmitz MESA Institute for Nanotechnology, Department of Semiconductor Components, University of Twente, Enschede, Netherlands 1NXP Semiconductors Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2007.374483 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Gate Oxide Leakage and Floating Gate Capacitor Matching Test W. Tian, J. Trogolo, B. Todd, L. Hutter Texas Instruments, Inc., USA DOI: 10.1109/ICMTS.2007.374467 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Novel parameter extraction method for low field drain current of nano-scaled MOSFETs T. Tanaka Fujitsu Laboratories Limited, Akiruno, Tokyo, Japan DOI: 10.1109/ICMTS.2007.374496 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Electrical Measurement of On-Mask Mismatch Resistor Structures S. Smith, A. Tsiamis, M. McCallum1, A. C. Hourd2, J. T. M. Stevenson2, A. J. Walton2 Institute of Integrated Micro and Nano Systems, School of Engineering and Electronics, Scottish Microelectronics Centre, University of Edinburgh, UK 1Nikon Precision Europe GmbH, West Lothian, UK 2Compugraphics International Limited, Glenrothes, Fife, UK DOI: 10.1109/ICMTS.2007.374445 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Extraction of Sheet Resistance and Linewidth from All-Copper ECD Test Structures Fabricated from Silicon Preforms B. J. R. Shulver, A. S. Bunting, A. M. Gundlach, L. I. Haworth, A. W. S. Ross, S. Smith, A. J. Snell, J. T. M. Stevenson, A. J. Walton, R. A. Allen1, M. W. Cresswell1 Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh, UK 1Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, Maryland, U.S.A DOI: 10.1109/ICMTS.2007.374447 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Array Based Test Structure for Optical-Electrical Overlay Calibration B. J. R. Shulver, R. A. Allen1, A. J. Walton, M. W. Cresswell1, J. T. M. Stevenson, S. Smith, A. S. Bunting, C. Dunare, A. M. Gundlach, L. I. Haworth, A. W. S. Ross, A. J. Snell Institute for Integrated Micro and Nano Systems, Scottish Microelectronics Centre, School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK 1Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2007.374476 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | The rectangular bipolar transistor tetrode structure and its application M. Schroter, S. Lehmann1 ECE Department, University of California, San Diego, La Jolla, CA, USA 1Chair for Electron Devices and Integrated Circuits, Dresden University of Technology, Dresden, Germany DOI: 10.1109/ICMTS.2007.374484 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Faster ESD device characterization with wafer-level HBM M. Scholz, D. Tremoullies, D. Linten, Y. Rolain1, R. Pintelon1, M. Sawada2, T. Nakaei2, T. Hasebe2, G. Groeseneken3 IMEC vzw, Leuven, Belgium 1Faculty of Engineering, Vrije Universiteit Brussel, Belgium 2Hanwa Electronic Industry Company Limited, Wakayama, Japan 3Electrical Engineering Department, IMEC and Katholieke Universiteit Leuven, Leuven, Belgium DOI: 10.1109/ICMTS.2007.374462 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Impact of Transitor Matching on Features of Digital Circuit Blocks U. Schaper, T. Kodytek, W. Kamp, R. Kunemund Infineon Technologies AG, COM BTS, Neubiberg, Germany DOI: 10.1109/ICMTS.2007.374459 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Methodology for performing RF reliability experiments on a generic test structure G. T. Sasse, R. J. de Vries, J. Schmitz MESA Institute for Nanotechnology, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS.2007.374478 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Test Structure for Process and Product Evaluation F. Rigaud, J. M. Portal1, H. Aziza1, D. Nee2, J. Vast2, C. Auricchio3, B. Borot4 STMicroelectronics, Rousset, France 1UMR CNRS 6137,IMT-Technopôle de Château Gombert, L2MP - Laboratoire Matériaux et Microélectronique de Provence, France 2ST Microelectronics, ZI Rousset, Rousset, France 3ST Microelectronics, Agrate Brianza, Italy 4ST Microelectronics,850 rue Jean Monnet, Crolles, France DOI: 10.1109/ICMTS.2007.374471 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Scalable approach for external collector resistance calculation C. Raya, N. Kauffmann1, F. Pourchon1, D. Celi1, T. Zimmer Laboratoire IXL, Université Bordeaux 1, Talence, France 1STMicroelectronics Central Research and Development, Crolles, France DOI: 10.1109/ICMTS.2007.374464 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Electrical Failure Analysis Methodology for DRAM of 80nm era and beyond using Nanoprober Technique H. Park, S. -Y. Han, W. -S. Lee1, C. -H. Jeon, S. Sohn, K. Chae, S. Yamada, W. Yang, D. Park Semiconductor R&D Center, Samsung Electro Mechanics Company Limited, Yongin si, Gyeonggi, South Korea 1Device Research Team, CAE Team, Yongin si, Gyeonggi, South Korea DOI: 10.1109/ICMTS.2007.374454 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | A Systematic Approach to Accurate Evaluation of CD-Metrology Tools N. G. Orji, B. D. Bunday1, R. G. Dixson, J. A. Allgair1 National Institute for Standards and Technology, Gaithersburg, MD, USA 1International SEMATECH Manufacturing Initiative, Austin, TX, USA DOI: 10.1109/ICMTS.2007.374446 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Analog characterization of dielectric relaxation of MIM capacitor using an improved recovery voltage technique Z. Ning, H. Casier, R. Gillon, H. -X. Delecourt, D. Tack, E. de Vylder, P. van Torre1, D. Hegsted AMI Semiconductor Belgium Bvba, Oudenaarde, Belgium 1Hogeschool GENT, Ghent, Belgium DOI: 10.1109/ICMTS.2007.374465 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Differential P+/Nwell varactor High Frequency Characterization Y. Morandini, D. Rapisarda1, J. -F. Larchanche1, C. Gaquiere I.E.M.N, Villeneuve d'Ascq, France 1STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2007.374480 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | On-wafer RF Figure-of-Merit Circuit Block Design for Technology Development, Process Control and PDK Validation S. Minehane, J. Cheng, T. Nakatani1, S. Moriyama, B. Aghdaie, M. Sengupta, S. Saxena, S. Winters, H. Karbasi, M. Quarantelli, S. Tonello, M. Redford PDF Solutions Inc., San Diego, CA, U.S.A. 1Corporate R&D Division, Matsushita Electric Industrial Co., Ltd., Kadoma, Kadoma City, Osaka, Japan DOI: 10.1109/ICMTS.2007.374479 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | New Methodology for the Characterization of EEPROM Extrinsic Behaviors D. Medjahed, T. Yao, D. Wojciechowski, P. Gassot, M. Yameogo1 AMI Semiconductor Belgium BVBA, Oudenaarde, Belgium 1Université de Bordeaux 1, Talence, France DOI: 10.1109/ICMTS.2007.374455 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | A Test Structure for Analysis of Asymmetry and Orientation Dependence of MOSFETs T. Matsuda, Y. Sugiyama, K. Nohara, K. Morita, H. Iwata, T. Ohzone1, T. Morishita1, K. Komoku1 Department of Information Systems Engineering, Toyama Prefectural University, Japan 1Department of Communication Engineering, Okayama Prefectural University, Japan DOI: 10.1109/ICMTS.2007.374473 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Modeling the Mismatch of High-k MIM Capacitors M. Marin, S. Cremer, J. -C. Giraudin, B. Martinet Central R&D, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2007.374466 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Benchmarking the PSP Compact Model for MOS Transistors X. Li, W. Wu, A. Jha, G. Gildenblat, R. van Langevelde1, G. D. J. Smit2, A. J. Scholten2, D. B. M. Klaassen2, C. C. McAndrew3, J. Watts4, M. Olsen, G. Coram, S. Chaudhry, J. Victory Department of Electrical Engineering, Arizona State University, Tempe, AZ, USA 1Philips Research Laboratories, Eindhoven, Netherlands 2NXP Corporate Research, Eindhoven, Netherlands 3Freescale Semiconductor, Inc., Tempe, AZ, USA 4TIBM Semiconductor Research and Development Center, System and Technology Group, Essex Junction, VT, USA DOI: 10.1109/ICMTS.2007.374495 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Test Structures for Accurate UHF C-V Measurements of Nano-Scale CMOSFETs with HfSiON and TiN Metal Gate K. -T. Lee, J. Schmitz1, G. A. Brown2, D. Heh2, R. Choi2, R. Harris2, S. -C. Song2, B. H. Lee2, I. -S. Han3, H. -D. Lee3, Y. -H. Jeong Department ofElectronic and Electrical Engineering, Pohang University of Science and Technology, Pohang, Gyeongbuk, South Korea 1MESA Institutefor Nanotechnology, University of Twente, Enschede, Netherlands 2SEMATECH, Austin, TX, USA 3Department of Electronics Engineering, Chungnam National University, Daejeon, South Korea DOI: 10.1109/ICMTS.2007.374468 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | High-Q Slow-Wave Transmission Line for Chip Area Reduction on Advanced CMOS Processes I. C. H. Lai, M. Fujishima1 Department of Frontier Informatics, University of Tokyo, Chiba, Japan 1School of Engineering and the School of Frontier Sciences, University of Tokyo, Chiba, Japan DOI: 10.1109/ICMTS.2007.374481 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Ring Oscillator Based Test Structure for NBTI Analysis M. B. Ketchen, M. Bhushan1, R. Bolam2 IBM Thomson J.Watson Research Center, Yorktown Heights, NY, USA 1IBM Systems and Technology Group, Hopewell Junction, NY, USA 2IBM Systems and Technology Group, Essex junction, VT, USA DOI: 10.1109/ICMTS.2007.374452 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Test Structure on SCR Device in Waffle Layout for RF ESD Protection M. -D. Ker, C. -Y. Lin Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Taiwan DOI: 10.1109/ICMTS.2007.374482 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | A Precise Resistance Tracing Technique for a Toggle Mode MRAM Evaluation Y. Katoh, K. Tsuji, H. Hada, N. Kasai System Devices Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.2007.374453 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Development and Use of Small Addressable Arrays for Process Window Monitoring in 65nm Manufacturing M. Karthikeyan, A. Gasasira, S. Fox, G. Yeric, M. Hall, J. Garcia1, B. Mitchell2, E. Wolf1 IBM Systems and Technology Group, Synopsys, Austin, TX, USA 1IBM Systems and Technology Group, Hopewell Junction, NY, USA 2Dallas, TX 3Marlborough, MA, USA DOI: 10.1109/ICMTS.2007.374470 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Device Array Scribe Characterization Vehicle Test Chip for Ultra Fast Product Wafer Variability Monitoring C. Hess, S. Saxena1, H. Karbasi2, S. Subramanian2, M. Quarantelli3, A. Rossoni3, S. Tonello3, S. Zhao3, D. Slisher4 PDF Solutions, Inc.orporated, San Jose, CA, USA 1PDF Solutions, Inc.orporated, Richardson, TX, USA 2PDF Solutions, Inc.orporated, San Diego, CA, USA 3PDF Solutions, Inc.orporated, Desenzano, Italy 4IBM Microelectronics, East Fishkill, USA DOI: 10.1109/ICMTS.2007.374472 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | A New Combined Methodology for Write-Margin Extraction of Advanced SRAM N. Gierczynski, B. Borot1, N. Planes1, H. Brut1 NXP Semiconductors, Crolles, France 1STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2007.374463 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Evaluation of 300 mm High Resistivity SOI UNIBOND material for RF applications up to millimeter wave using 65 nm CMOS SOI technology F. Gianesello, C. Raynaud1, D. Gloria2, S. Boret, B. Ghyselen3, C. Mazure4 STMicroelectronics, Crolles Cedex, France 1CEA-LETI, Grenoble, France 2STMicroelectronics, Crolles, France 3SOITEC S.A., Bernin, France 4SOITEC SA, Parc Technologique des Fontaines, Bernin, France DOI: 10.1109/ICMTS.2007.374485 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Test Circuit for Study of CMOS Process Variation by Measurement of Analog Characteristics K. M. G. V. Gettings, D. S. Boning Microsystems Technology Laboratories, MIT, Cambridge, MA, USA DOI: 10.1109/ICMTS.2007.374451 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Dynamic Analyses of Membranes and Thin Films on Wafer Level R. Gerbach, F. Naumann, M. Ebert, J. Bagdahn, J. Klattenhoff1, C. Rembe1 Fraunhofer Institute of Mechanics of Materials (IWM), Halle, Germany 1Polytec GmbH, Waldbronn, Germany DOI: 10.1109/ICMTS.2007.374486 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | | A Large Scale, Flip-Flop RAM imitating a logic LSI for fast development of process technology M. Fujii, K. Nii, H. Makino, S. Ohbayashi, M. Igarashi, T. Kawamura, M. Yokota, N. Tsuda, T. Yoshizawa, T. Tsutsui, N. Takeshita, N. Murata, T. Tanaka, T. Fujiwara, K. Asahina, M. Okada, K. Tomita, M. Takeuchi, H. Shinohara Renesas Technology Corporation, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.2007.374469 HOVER FOR ABSTRACT | PDF Xplore |
| 2007 | Automatic extraction methodology for accurate measurement of effective channel length on 65nm MOSFET technology and below D. Fleury, A. Cros, K. Romanjek1, D. Roy, F. Perrier1, B. Dumont1, H. Brut STMicroelectronics, Crolles, France 1NXP Semiconductors, Crolles, France DOI: 10.1109/ICMTS.2007.374461 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | A 1 Mbit SRAM test structure to analyze local mismatch beyond 5 sigma variation T. Fischer, C. Otte, D. Schmitt-Landsiedel, E. Amirante1, A. Olbrich1, P. Huber1, M. Ostermayr1, T. Nirschl1, J. Einfeld1 Institute for Technical Electronics, Technical University Munich, Munich, Germany 1Infineon Technologies, Neubiberg, Germany DOI: 10.1109/ICMTS.2007.374456 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Quantitative analysis of Joule heating in surface micromachined Greek cross test structures S. Enderling, S. Smith, J. T. M. Stevenson, A. J. Walton Institute of Integrated Micro and Nano Systems, School of Engineering and Electronics, Scottish Microelectronics Centre, University of Edinburgh, UK DOI: 10.1109/ICMTS.2007.374487 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Understanding the Carbon Impact on Si/SiGe:C HBT Base Current Mismatch S. Danaie, M. Marin, G. Ghibaudo1, J. -C. Vildeuil, S. Chouteau2, I. Sicard, A. Monroy Central R & D, STMicroelectronics, Crolles, France 1IMEP/INPG-Minatec, Grenoble, France 2STMicroelectronics, Central R&D, 850 rue Jean Monnet, F-38926 Crolles, France DOI: 10.1109/ICMTS.2007.374460 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | FUSI Specific Yield Monitoring Enabling Improved Circuit Performance and Fast Feedback to Production T. Chiarella, M. Rosmeulen, H. Tigelaar1, C. Kerner, A. Nackaerts, J. Ramos, A. Lauwers, A. Veloso, M. Jurczak, A. Rothschild, L. Witters, H. Yu, J. A. Kittl, R. Verbeeck, M. de Potter, I. Debusschere, P. Absil, S. Biesemans, T. Hoffmann IMEC, Leuven, Belgium 1IMEC, Philips Research DOI: 10.1109/ICMTS.2007.374450 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Extraction of Self-Heating Free I-V Curves Including the Substrate Current of PD SOI MOSFETs Q. Chen, Z. -Y. Wu, R. Y. K. Su, J. -S. Goo, C. Thuruthiyil, M. Radwin, N. Subba, S. Suryagandh, T. Ly, V. Wason, J. X. An, A. B. Icel Advanced Micro Devices, Inc., Sunnyvale, CA, USA DOI: 10.1109/ICMTS.2007.374498 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | A Novel RF-WAT Test Structure for Advanced Process Monitoring in SOC Applications D. C. Chen, R. Lee, Y. C. Liu, M. C. Tang, G. Chiang, A. Kuo, C. S. Yeh, S. C. Chien, S. W. Sun Central R&D Division, United Microelectronics Corporation Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2007.374492 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | From MOSFET Matching Test Structures to Matching Data Utilization: Not an Ordinary Task A. Cathignol, S. Bordez1, K. Rochereau2, G. Ghibaudo3 STMicroelectronics, Crolles, FR 1STMicroelectronics, Crolles, France 2NXP semiconductors, Crolles, France 3INPG, IMEP, Grenoble, France DOI: 10.1109/ICMTS.2007.374490 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Improved Test Structure for Thermnal Resistance Scaling Study in Power Devices A. Canepari, G. Bertrand, A. Giry, M. Minondo, S. Ortolland, H. Jaouen, B. Szelag, J. Mourier, J. -P. Chante1 STMicroelectronics, Crolles, France 1INSA Lyon, Villeneuve d'Ascq, France DOI: 10.1109/ICMTS.2007.374488 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Automated on-wafer characterization in micro-machined resonators: towards an integrated test vehicle for bulk acoustic wave resonators (FBAR) H. Campanella, P. Nouet1, P. de Paco2, A. Uranga3, N. Barniol3, J. Esteve Centro Nacional de Microelectrónica CNM-CSIC, Campus UAB, Bellaterra, Spain 1UMR-UM2-CNRS, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier LIRMM, Montpellier, France 2Telecommunications Engineering Department, Universitat Autònoma Barcelona, Bellaterra, Spain 3Electronics Engineering Department, Universitat Authnòma de Barcelona, Bellaterra, Spain DOI: 10.1109/ICMTS.2007.374474 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | A Continuous Model for MOSFET VT Matching Considering Additional Length Effects S. Bordez, A. Cathignol, K. Rochereau1 STMicroelectronics, Crolles, France 1NXP Semiconductors, Crolles, France DOI: 10.1109/ICMTS.2007.374489 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Accurate Inductance De-embedding Technique for Scalable Inductor Models V. Blaschke, J. Victory Jazz Semiconductor, Newport Beach, CA, USA DOI: 10.1109/ICMTS.2007.374493 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | A unified model for integrated resistors in CMOS technologies I. Aureli, D. Ventrice, C. Codegoni, P. Fantini STMicroelectronics, NVMTD-FTM, Advanced R and D, Agrate-Brianza, Italy DOI: 10.1109/ICMTS.2007.374497 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Coupling on-wafer measurement errors and their impact on calibration and de-embedding up to 110 GHz for CMOS millimeter wave characterizations C. Andrei, D. Gloria1, F. Danneville, P. Scheer1, G. Dambrine Institut dE28099Electronique, de Microélectronique et de Nanotechnologie, Villeneuve d'Ascq, France 1STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2007.374494 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Study of Test Structures for Use as Reference Materials for Optical Critical Dimension Applications R. A. Allen, H. J. Patrick1, M. Bishop2, T. A. Germer3, R. Dixson4, W. F. Guthrie5, M. W. Cresswell Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1KT Consulting, Inc., Antioch, CA, USA 2International SEMATECH Manufacturing Initiative, Austin, TX, USA 3Optical Technology Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 4Precision Engineering Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 5Statistical Engineering Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2007.374448 HOVER FOR ABSTRACT | PDF Xplore | |
| 2007 | Rapid Characterization of Threshold Voltage Fluctuation in MOS Devices K. Agarwal, S. Nassif, F. Liu, J. Hayes, K. Nowka IBM, Corporation, Austin, TX, USA DOI: 10.1109/ICMTS.2007.374458 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Impact of GHz disturbances on DC parametric measurements H. P. Tuinhout, P. G. M. Baltus1 Philips Research, Eindhoven, Netherlands 1Philips Semiconductors ICRF, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2006.1614278 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Specific contact resistance measurements of metal-semiconductor junctions N. Stavitski, M. J. H. van Dal1, R. A. M. Wolters, A. Y. Kovalgin, J. Schmitz MESA Institute for Nanotechnology, University of Twente, Enschede, Netherlands 1Philips Research Leuven, IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.2006.1614265 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | MEMS test structure for measuring thermal conductivity of thin films L. La Spina, N. Nenadovic1, A. W. van Herwaarden2, H. Schellevis, W. H. A. Wien, L. K. Nanver Laboratory of Electronic Components, Technology & Materials,ECTM,DIMES, Delft University of Technnology, Delft, Netherlands 1Philips Semiconductors CTO, Nijmegen, Netherlands 2Xensor Integration, Delft, Netherlands DOI: 10.1109/ICMTS.2006.1614291 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Comparison of optical and electrical measurement techniques for CD metrology on alternating aperture phase-shifting masks S. Smith, A. Tsiamis, M. McCallum, A. C. Hourd, J. T. M. Stevenson, A. J. Walton School of Engineering and Electronics, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2006.1614287 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Design and fabrication of a copper test structure for use as an electrical critical dimension reference B. J. R. Shulver, A. S. Bunting, A. M. Gundlach, L. I. Haworth, A. W. S. Ross, A. J. Snell, J. T. M. Stevenson, A. J. Walton, R. A. Allen1, M. W. Cresswell1 Institute for Integrated Micro and Nano Systems, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MA, USA DOI: 10.1109/ICMTS.2006.1614288 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | -1/+0.8°C error, accurate temperature sensor using 90nm 1V CMOS for on-line thermal monitoring of VLSI circuits M. Sasaki, M. Ikeda, K. Asada VLSI Design and Education Center VDEC, University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2006.1614264 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | New test structures for extraction of base sheet resistance in BiCMOS technology C. Raya, F. Pourchon1, D. Celi1, M. Laurens1, T. Zimmer Laboratoire IXL, Université Bordeaux 1, Talence, France 1Central R&D, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2006.1614270 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | High frequency mismatch characterization on 170GHz HBT NPN bipolar device A. Perrotin, D. Gloria, S. Danaie, F. Pourchon, M. Laurens Central R&D, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2006.1614297 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | A comprehensive model to accurately calculate the gate capacitance and the leakage from DC to 100 MHz for ultra thin dielectrics L. Pantisano, J. Ramos, E. San Andres Serrano1, P. J. Roussel, W. Sansen2, G. Groeseneken IMEC, Leuven, Belgium 1Dpto. Fäsica Aplicada III, Fac. Ciencias Fäsicas, Universidad Complutense de Madrid, Madrid, Spain 2KU Leuven ESAT, Leuven, Belgium DOI: 10.1109/ICMTS.2006.1614308 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width T. Ohzone, E. Ishii, T. Morishita, K. Komoku, T. Matsuda1, H. Iwata1 Department of Communication Engineering, Okayama Prefectural University, Soja, Okayama, Japan 1Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.2006.1614301 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Characterisation of advanced multilayer de-embedding structures up to 50 GHz incorporating a novel validation standard J. A. O'Sullivan, K. G. McCarthy, P. J. Murphy Department of Electrical and Electronic Engineering, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.2006.1614276 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Analogue characterization of horizontal bars capacitors for smart power applications Zhenqiu Ning, H. . -X. Delecourt, L. De Schepper, D. Tack, B. Desoete, R. Gillon AMI Semiconductor Belgium bvba, Oudenaarde, Belgium DOI: 10.1109/ICMTS.2006.1614306 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | 1/f gate tunneling current noise model of ultrathin oxide MOSFETs F. Martinez, S. Soliveres, C. Leyris, M. Valenza IES-CEM, Universite Montpellier II-UMR CNRS 55, Montpellier, France DOI: 10.1109/ICMTS.2006.1614302 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Dielectric relaxation characterization and modeling in large frequency and temperature domain: application to 5fF/µm2 Ta2O5 MIM capacitor J. . -P. Manceau, S. Bruyere1, E. Picollet1, M. Minondo1, C. Grundrich1, D. Cottin1, M. Bely1 LEMD (CNRS and UJF), Grenoble, France 1STMicroelectronics Private Limited, Crolles, France DOI: 10.1109/ICMTS.2006.1614303 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Test structures for the characterisation of MEMS and CMOS integration technology H. Lin, A. J. Walton, C. C. Dunarc1, J. T. M. Stevenson, A. M. Gundlach, S. Smith, A. S. Bunting Institute for Integrated Micro and Nano Systems, University of Edinburgh, UK 1Sch. of Eng. & Electron., Edinburgh Univ., UK DOI: 10.1109/ICMTS.2006.1614292 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Test structure design for measuring electron and hole mobilities at very high injection levels G. D. Licciardo Department of Information and Electrical Engineering, University of Salerno, Fisciano, Italy DOI: 10.1109/ICMTS.2006.1614300 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Test structures for study of electron transport in nickel silicide features with line widths between 40 nm and 160 nm Bin Li, Li Shi, JiPing Zhou1, P. S. Ho1, R. A. Allen, M. W. Cresswell Microelectronics Research Center, University of Texas, Austin, Austin, TX, USA 1NA DOI: 10.1109/ICMTS.2006.1614266 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Novel test structures for on-chip characterization of coupling capacitance variation by in- and anti-phase crosstalk in multi-level metallization Hi-Deok Lee, Hee-Hwan Ji, In-Sik Han, Han-Soo Joo, Dae-Mann Kim1, Sung-Hyung Park, Heui-Seung Lee, Won-Joon Ho, Dae-Byung Kim, Ihl-Hyun Cho, Sang-Young Kim, Sung-Bo Hwang, Jeong-Gon Lee, Jin-Won Park Department of Elec. Engi, Chungnam National University, Daejeon, South Korea 1Computational Sciences, Korea Institute of Advanced Study, Seoul, South Korea DOI: 10.1109/ICMTS.2006.1614307 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Measurement method for transient programming current of 1T1R phase-change memory K. Kurotsuchi, N. Takaura, N. Matsuzaki, Y. Matsui, O. Tonomura, Y. Fujisaki, N. Kitai1, R. Takemura, K. Osada, S. Hanzawa, H. Moriya, T. Iwasaki, T. Kawahara, M. Terao, M. Matsuoka, M. Moniwa Central Research Laboratory, Hitachi and Limited, Tokyo, Japan 1Hitachi ULSI Systems Company Limited, Tokyo, Japan DOI: 10.1109/ICMTS.2006.1614272 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | A new polysilicon resistor model considering geometry dependent voltage characteristics for the deep sub-micron CMOS process Seok Yong Ko, Jin Soo Kim, Gwang Hyeon Lim, Sung Ki Kim DongbuAnam Semiconductor, Inc., Bouchon, Kyunggi, South Korea DOI: 10.1109/ICMTS.2006.1614268 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software M. Karthikeyan, S. Fox, W. Cote, G. Yeric1, M. Hall1, J. Garcia2, B. Mitchell2, E. Wolf3, S. Agarwal1 IBM Systems and Technology Group, Hopewell Junction, NY, USA 1Synopsys, Inc., Austin, TX, USA 2Synopsys, Inc., Dallas, TX, USA 3Synopsys, Inc., Marlborough, MA, USA DOI: 10.1109/ICMTS.2006.1614284 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Scribe characterization vehicle test chip for ultra fast product wafer yield monitoring C. Hess, A. Inani, Y. Lin, M. Squicciarini, R. Lindley1, N. Akiya PDF Solutions, Inc., San Jose, CA, USA 1PDF Solutions, Inc., San Diego, CA, USA DOI: 10.1109/ICMTS.2006.1614285 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Characterization of dielectric charging in RF MEMS capacitive switches R. W. Herfst, H. G. A. Huizing, P. G. Steeneken, J. Schmitz1 Philips Research Laboratories, Eindhoven, Netherlands 1MESA Research Institute, Chair of Semiconductor Components, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS.2006.1614290 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Test structures and measurement of gate sidewall junction capacitance in MOSFETs N. Hasegawa, S. Yamaura, T. Mori, S. Yamaguchi1 Fujitsu Laboratories Limited, Kawasaki, Japan 1Fujitsu Laboratories Limited, Akiruno, Tokyo, Japan DOI: 10.1109/ICMTS.2006.1614269 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | A bulk knife-edged as-deposition self-patterning structure for Greek-cross and organic thin film transistors T. Harada, K. Ito, T. Shibata1, Y. Mita School of Electronics Engineering, University of Tokyo, Japan 1School of Frontier Sciences, University of Tokyo, Japan DOI: 10.1109/ICMTS.2006.1614293 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Impact of pad de-embedding on the extraction of interconnect parameters Sangwook Han, Jooyong Kim, D. P. Neikirk Microelectronics Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, Austin, TX, USA DOI: 10.1109/ICMTS.2006.1614279 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Ring-gate MOSFET test structures for measuring surface-charge-layer sheet resistance on high-resistivity-silicon substrates S. B. Evseev, L. K. Nanver, S. Milosavljevic Laboratory of ECTM, DIMES, Delft University of Technnology, Delft, Netherlands DOI: 10.1109/ICMTS.2006.1614263 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | On the passivation of interface states in SONOS test structures: impact of device layout and annealing process F. Driussi, L. Selmi, N. Akil, M. J. van Duuren, R. van Schaijk DIEGM, University of Udine, Udine, Italy DOI: 10.1109/ICMTS.2006.1614274 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Field-configurable test structure array (FC-TSA): enabling design for monitor, model and manufacturability K. Y. Y. Doong, J. Bordelon1, Keh-Jeng Chang2, L. J. Hung, C. C. Liao, S. C. Lin, R. S. Ho, S. Hsieh, K. L. Young Science-based Industrial Park, Taiwan Semiconductor Manufacturing Corporation, Shin-Chu, Taiwan 1Science-based Industrial Park, Stratosphere Solutions, Inc., Sunnyvale, CA, USA 2Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2006.1614283 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Impact of emitter resistance mismatch on base and collector current matching in bipolar transistors S. Danaie, A. Perrotin, G. Ghibaudo1, J. . -C. Vildeuil, G. Morin, M. Laurens Central R&D, STMicroelectronics, Crolles, France 1IMEP/CNRS, Grenoble, France DOI: 10.1109/ICMTS.2006.1614295 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Investigation of lateral charge distribution of 2-bit SONOS memory devices using physically separated twin SONOS structure Byung Yong Choi, Choong-Ho Lee1, Yong Kyu Lee2, Hyungcheol Shin, Jong Duk Lee, Byung-Gook Park, Dong-Won Kim1, Suk-Kang Sung1, Se Hoon Lee1, Byung-Kyu Cho1, Tae-Yong Kim1, Eun Suk Cho1, Jong Jin Lee1, Donggun Park1 ISRC and School of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea 1Device Research Team, Semiconductor Research Center, Samsung Electronics Company Limited, Yongin si, Gyeonggi, South Korea 2Department of Electrical Engineering, University of Stanford, Stanford, CA, USA DOI: 10.1109/ICMTS.2006.1614273 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | High-frequency measurements of the mismatch on the Y-parameters of high-speed SiGe:C HBTs L. J. Choi, R. Venegas, S. Decoutere IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.2006.1614296 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics T. Chiarella, J. Ramos, A. Nackaerts, S. Demuynck, S. Verhaegen, R. Verbeeck, M. de Potter de ten Broeck, C. Kerner, T. Hoffmann, M. Van Hove, I. Debusschere, S. Biesemans IMEC vzw, Leuven, Belgium DOI: 10.1109/ICMTS.2006.1614282 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Improved methodology for better accuracy on transistors matching characterization A. Cathignol, K. Rochereau1, S. Bordez, G. Ghibaudo2 STMicroelectronics Private Limited, Crolles, France 1Philips semiconductors, Crolles, France 2IMEP, Grenoble, France DOI: 10.1109/ICMTS.2006.1614298 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | Analysis and modeling of substrate impedance network in RF CMOS E. Bouhana, P. Scheer1, S. Boret1, D. Gloria1, G. Dambrine, M. Minondo1, H. Jaouen1 I.E.M.N, Villeneuve d'Ascq, France 1STMicroelectronics Private Limited, Crolles, France DOI: 10.1109/ICMTS.2006.1614277 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | | Ring oscillator based technique for measuring variability statistics M. Bhushan, M. B. Ketchen1, S. Polonsky1, A. Gattiker2 IBM Systems and Technology Group, Poughkeepsie, NY, USA 1IBM Thomson J.Watson Research Center, Yorktown Heights, NY, USA 2IBM Research, Austin, TX, USA DOI: 10.1109/ICMTS.2006.1614281 HOVER FOR ABSTRACT | PDF Xplore |
| 2006 | Impact of neighbor components heating on power transistor electrical behavior H. Beckrich, S. Ortolland1, D. Pache1, D. Celi1, D. Gloria1, T. Zimmer Laboratoire IXL, Université Bordeaux 1, Talence, France 1STMicroelectronics Private Limited, Crolles, France DOI: 10.1109/ICMTS.2006.1614304 HOVER FOR ABSTRACT | PDF Xplore | |
| 2006 | C-V test structures for metal gate CMOS R. G. Bankras, M. P. J. Tiggelman1, M. Adi Negara2, G. T. Sasse1, J. Schmitz1 ASM International N. V., Almere, Netherlands 1MESA Institute for Nanotechnology, Group Semiconductor Components, University of Twente, Enschede, Netherlands 2Tyndall National Institute, Cork, Ireland DOI: 10.1109/ICMTS.2006.1614309 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Characterization and model of on-chip flicker noise with deep Nwell (DNW) isolation for 130nm and beyond SOC M. T. Yang, D. C. W. Kuo, C. W. Kuo, Y. J. Wang, P. P. C. Ho, T. J. Yeh, S. Liu Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2005.1452242 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Measurement of inner-chip variation and signal integrity by a 90-nm large-scale TEG [test element group] M. Yamamoto, Y. Hayasi1, H. Endo1, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan 1Hitachi ULSI Systems Company Limited, Tokyo, Japan DOI: 10.1109/ICMTS.2005.1452265 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | New applications of cross-talk-based capacitance measurements [CMOS ICs] L. Vendrame, L. Bortesi, A. Bogliolo1 STMicroelectranics, FTM Research and Development, Agrate-Brianza, Italy 1STI, University of Urbino, Urbino, Italy DOI: 10.1109/ICMTS.2005.1452283 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | EOT measurement for ultra-thin gate dielectrics using LC resonance circuit [MOS devices] A. Teramoto, M. Komura1, R. Kuroda1, K. Watanabe1, S. Sugawa1, T. Ohmi New Industry Creation Hatchery Center, Tohoku University, Sendai, Japan 1Graduate School of Engineering, Tohoku University, Aoba-ku, Sendai, Japan DOI: 10.1109/ICMTS.2005.1452271 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Physical meaning of σ/ value estimated with VTH-mismatch evaluation circuit K. Terada, T. Yamauchi, A. Ueki Faculty of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan DOI: 10.1109/ICMTS.2005.1452254 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Novel realistic short structure construction for parasitic resistance de-embedding and on-wafer inductor characterization J. Tao, P. Findley, G. A. Rezvani RF Micro Devices, Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2005.1452260 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Improved test structures for the electrical measurement of feature size on an alternating aperture phase-shifting mask S. Smith, A. J. Walton, M. McCallum1, A. C. Hourd2, J. T. M. Stevenson, A. W. S. Ross School of Engineering and Electronics, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1Nikon Cort, Nikon Precision Europe, Livingston, UK 2Eastfield Industrial Estate, Compugraphics International Limited, Glenrothes, Fife, UK DOI: 10.1109/ICMTS.2005.1452205 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | On-wafer radiation pattern measurements of integrated antennas on standard BiCMOS and glass processes for 40-80GHz applications N. Segura, S. Montusclat1, C. Person, S. Tedjini2, D. Gloria1 ENST Bretagne-UBO, LEST UMR 6165 GET, Brest, France 1Central Research and Development, Q-TPS Laboratory, STMicroelectronics, Crolles, France 2ESISAR/LCIS, Valence, France DOI: 10.1109/ICMTS.2005.1452238 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Parameter variation on chip-level U. Schaper, J. Einfeld, A. Sauerbrey Communication Corporate Logic, Infineon Technologies, Munich, Germany DOI: 10.1109/ICMTS.2005.1452250 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Charge pumping at radio frequencies [MOSFET device interface state density measurement] G. T. Sasse, H. de Vries, J. Schmitz MESA Research Institute, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS.2005.1452273 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Substrate isolation in 0.18um CMOS technology G. A. Rezvani, Jon Tao RF Micro Devices, Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2005.1452244 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Multi-purpose EM test structure with electrical verification of the failure spot demonstrated using SWEAT for fast wafer level reliability monitoring A. Pietsch, A. Martin, J. Fazekas Central Reliability Methodology Department, Infineon Technologies, Munich, Germany DOI: 10.1109/ICMTS.2005.1452232 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | RF monitoring test structures for advanced RF technologies working up to 100GHz with less than 80µm width A. Perrotin, D. Gloria Central Research and Development, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2005.1452264 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | A novel mobility-variation-free extraction technique of capacitance coupling coefficient for stacked flash memory cell T. Okagaki, M. Tanizawa, M. Fujinaga, T. Kunikiyo, H. Yuki, K. Ishikawa, Y. Nishikawa, T. Eimori, M. Inuishi, Y. Oji Renesas Technology Corporation, Hyogo, Japan DOI: 10.1109/ICMTS.2005.1452270 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | A test structure to measure sheet resistances of highly-doped-drain and lightly-doped-drain in CMOSFET T. Ohzone, K. Okada, T. Morishita, K. Komoku, T. Matsuda1, H. Iwata1 Department of Communication Engineering, Okayama Prefectural University, Soja, Okayama, Japan 1Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.2005.1452224 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Verification of layout efficient shield-based de-embedding techniques for on-wafer HBT characterisation up to 30 GHz J. A. O'Sullivan, K. G. McCarthy, A. C. Murphy1, P. J. Murphy Dept. of Electrical and Electronic Engineering, University College Cork, Cork, Ireland 1Freescale Semiconductor, Cork, Ireland DOI: 10.1109/ICMTS.2005.1452241 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Impact of mask alignment on the tunneling field effect transistor (TFET) T. Nirschl, U. Schaper, J. Einfeld, S. Henzler, M. Sterkel1, J. Singer, M. Fulde1, W. Hansch1, G. Georgakos, D. Schmitt-Landsiedell2 Infineon Technologies AG, Munich, Germany 1Institute for Technical Electronics, Technical University, Munich, Germany 2NA DOI: 10.1109/ICMTS.2005.1452216 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | A simple and accurate capacitance ratio measurement technique for integrated circuit capacitor arrays Zhenqiu Ning, L. De Schepper, H. . -X. Delecourt, R. Gillon, M. Tack AMI Semiconductor Belgium bvba, Oudenaarde, Belgium DOI: 10.1109/ICMTS.2005.1452251 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | A self heating test structure using poly resistors and P+/N diodes to characterize anomalous charge transfers in embedded flash memories P. Mora, P. Waltz, S. Renard, P. Candelier STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2005.1452219 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | A study of 90nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure A. Mizumura, T. Ohishi, N. Yokoyama1, M. Nonaka1, S. Tanaka1, H. Ammo Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporation, Atsugi, Kanagawa, Japan 1Nagasaki Technology Center, Sony Semiconductor Kyusyu Corporation, Isahaya, Nagasaki, Japan DOI: 10.1109/ICMTS.2005.1452215 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | A test structure for spatial analysis of hot-carrier-induced photoemission in n-MOSFET T. Matsuda, T. Tanaka, H. Iwata, T. Ohzone1, K. Yamashita2, N. Koike2, K. Tatsuuma2 Department of Electronics and Informatics, Toyama Prefectural University Kurokawa, Kosugi-machi, Imizu-gun, Toyama, Japan 1Faculty of Computer Science and System Engineering, Okayama Prefectural University, Soja-Shi, Okayama, Japan 2ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electric Ind. Co., Ltd., Kyoto, Japan DOI: 10.1109/ICMTS.2005.1452217 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Assessment of a 90nm PMOS NBTI in the form of products failure rate H. Masuda, D. G. Pierce1, K. Nishitsuru2, K. Machida3 Semiconductor Technology Academic Research Center, Yokohama, Japan 1Sandia Technologies, Inc., Albuquerque, NM, USA 2Agilent Technologies International Japan Limited, Hachioji, Tokyo, Japan 3Mathematical Systems Institute, Inc., Tokyo, Japan DOI: 10.1109/ICMTS.2005.1452231 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | RF-ESD design and measurement of CMOS LNAs: a comparison between diode and inductive protection P. Leroux, M. Steyaert1 Katholieke Hogeschool Kempen, Belgian Nuclear Research Centre, Geel, Belgium 1ESAT-MICAS, Leuven, Belgium DOI: 10.1109/ICMTS.2005.1452256 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Simple modeling expressions for substrate network of on-chip inductors I. C. H. Lai, M. Fujishima School of Frontier Sciences, University of Tokyo, Japan DOI: 10.1109/ICMTS.2005.1452240 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | | High speed test structures for in-line process monitoring and model calibration [CMOS applications] M. Ketchen, M. Bhushan1, D. Pearson IBM Research Center, Yorktown Heights, NY, USA 1IBM S and TG, Yorktown Heights, NY, USA DOI: 10.1109/ICMTS.2005.1452212 HOVER FOR ABSTRACT | PDF Xplore |
| 2005 | 90nm CMOS technology characterization at transfer and ramp A. Kelleher, D. Gourley, A. M. Holmes, T. Hepburn, C. Farrell, R. Groves, T. Taskin, J. McMillan, W. Rawlins Intel (Ireland) Limited, Kildare, Ireland DOI: 10.1109/ICMTS.2005.1452208 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | A novel test fixture with enhanced signal port isolation capability for on-wafer microwave measurements T. Kaija, E. O. Ristolainen Institute of Electronics, Tampere University of Technology, Tampere, Finland DOI: 10.1109/ICMTS.2005.1452257 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Test structures for the characterization of deep trench isolation [The following paper has been withdrawn by the authors] S. Hausser, R. Albus1, H. Schligtenhorst Philips Semiconductors GmbH, Boeblingen 1Philips Semiconductors GmbH, Boeblingen, Germany DOI: 10.1109/ICMTS.2005.1452209 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Recent trends in reliability assessment of advanced CMOS technologies G. Groeseneken, R. Degraeve, B. Kaczer, P. Roussel IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.2005.1452230 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | An improved LDMOS transistor model that accurately predicts capacitance for all bias conditions S. F. Frere, P. Moens1, B. Desoete1, Wojciechowski D1, A. J. Walton School of Engineering and Electronics, SMC, University of Edinburgh, Edinburgh, UK 1AMI Semiconductor Belgium BVBa, Oudenaarde, Belgium DOI: 10.1109/ICMTS.2005.1452226 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Design and implementation of an ultra high precision parametric mismatch measurement system T. Ewert, H. Tuinhoutt1, N. Wils1, J. Olsson Uppsala University, Ångström Laboratory, Sweden 1philips Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2005.1452249 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Suspended Greek cross test structures for measuring the sheet resistance of non-standard cleanroom materials S. Enderling, C. L. Brown1, S. Smith, M. H. Dicks, J. T. M. Stevenson, A. W. S. Ross, M. Mitkova1, M. N. Kozicki1, A. J. Walton School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK 1Center for Solid State Electronics Research, Arizona State University, Tempe, AZ, USA DOI: 10.1109/ICMTS.2005.1452202 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances R. Difrenza, K. Rochereau1, T. Devoivre, B. Tavel1, B. Duriez1, D. Roy, S. Jullian1, A. Dezzani, R. Boulestin, P. Stolk1, F. Arnaud STMicroelectronics, Crolles, France 1Philips Semiconductors, Crolles, France DOI: 10.1109/ICMTS.2005.1452247 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Mismatch characterisation of chip interconnect resistance J. Deveugele, Libin Yao, M. Steyaert, W. Sansen Katholieke Universiteit Leuven, Leuven, Belgium DOI: 10.1109/ICMTS.2005.1452259 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | New extraction method for gate bias dependent series resistance in nanometric double gate transistors A. Cros, S. Harrison, R. Cerutti, P. Coronel, G. Ghibaudo1, H. Brut STMicroelectronics, Crolles, France 1IMEP, Grenoble, France DOI: 10.1109/ICMTS.2005.1452225 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Experimental analysis of a Ge-HfO2-TaN gate stack with a large amount of interface states J. A. Croon, B. Kaczer, G. S. Lujan1, S. Kubicek, G. Groeseneken1, M. Meuris IMEC, Leuven, Belgium 1ESAT, Katholieke Universiteit Leuven, Belgium DOI: 10.1109/ICMTS.2005.1452261 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Comparison of SEM and HRTEM CD measurements extracted from test-structures having feature linewidths from 40 nm to 240 nm M. W. Cresswell, B. Park, R. A. Allen, W. F. Guthrie1, R. G. Dixson2, W. M. Tan, C. E. Murabito3 Semiconductor Electronics Division, Electronics and Electrical Engineering Laboratory, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Statistical Engineering Division, Information Technology Laboratory, National Institute for Standards and Technology, Gaithersburg, MD, USA 2Precision Engineering Division, Manufacturing Engineering Laboratory, National Institute for Standards and Technology, Gaithersburg, MD, USA 3NA DOI: 10.1109/ICMTS.2005.1452204 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Speed - accuracy trade-off for measurement and characterization of the matching performance of SiGe:C HBTs, applied to a 200 GHz technology L. J. Choi, R. Venegas, S. Decoutere IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.2005.1452248 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | A novel CBCM method free from charge injection induced errors: investigation into the impact of floating dummy-fills on interconnect capacitance Y. W. Chang, H. W. Chang1, T. C. Lu1, Y. King2, W. Ting1, J. Ku1, C. Y. Lu1 Nstitute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan 1Technology Development Center, Macronix International Co., Ltd, Hsinchu, Taiwan 2Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2005.1452275 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Accelerated life time estimation of electrostatic microactuators B. Caillard, Y. Mita1, Y. Fukuta2, T. Shibata1, H. Fujita2 LIMMS, IIS, CNRS, Shibata-Mita Laboratory, Department Electl Engineering, University of Tokyo, Bunkyo, Tokyo, Japan 1Shibata-Mita Laboratory, Department Electl Engineering, University of Tokyo, Bunkyo, Tokyo, Japan 2CIRMM, IIS, Shibata-Mita Laboratory, Department Electl Engineering, University of Tokyo, Bunkyo, Tokyo, Japan DOI: 10.1109/ICMTS.2005.1452234 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | A failure analysis test structure for deep sub-micron CMOS copper interconnect technologies A. Cabrini, D. Cantarelli1, P. Cappelletti2, R. Casiraghi2, D. Iezzi2, A. Maurelli2, M. Pasotti2, P. L. Rolandi2, G. Torelli Department of Electronics, University of Pavia, Agrate-Brianza, Milan, Italy 1Central R&D, STMicroelectronics, Agrate Brianza (MI), Italy 2Central R&D, STMicroelectronics, Agrate-Brianza, Agrate Brianza (MI), Italy DOI: 10.1109/ICMTS.2005.1452279 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Capacitance characterization in integrated circuit development: the intimate relationship of test structure design, equivalent circuit and measurement methodology G. A. Brown Sematech Inc., Austin, TX, USA DOI: 10.1109/ICMTS.2005.1452268 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Design and characterization of a post-processed copper heat sink for smart power drivers [lateral nDMOS drivers] G. Van den bosch, T. Webers, E. Driessens, B. Elattari, D. Wojciechowski1, P. Gassot1, P. Moens1, G. Groeseneken IMEC, Leuven, Belgium 1AMI Semiconductor Belgium BVBa, Oudenaarde, Belgium DOI: 10.1109/ICMTS.2005.1452210 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Extraction of time dependent data from time domain reflection transmission line pulse measurements [ESD protection design] R. A. Ashton White Mountain Laboratories, Phoenix, AZ, USA DOI: 10.1109/ICMTS.2005.1452278 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design N. D. Arora, Li Song, S. Shah, A. Sinha, V. Chang Cadence Design Systems, San Jose, CA, USA DOI: 10.1109/ICMTS.2005.1452281 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | A new method for precise evaluation of dynamic recovery of negative bias temperature instability S. Aota, S. Fujii1, Z. W. Jin, Y. Ito2, K. Utsumi, E. Morifuji, S. Yamada, F. Matsuoka, T. Noguchi System LSX Division I, Semiconductor Company, Toshiba Corporation, Yokohama, Kanagawa, Japan 1Agilent Technologies International Japan Limited, Yokohama, Kanagawa, Japan 2Test System Development Department, Toshiba Microelectronics Corporation, Yokohama, Kanagawa, Japan DOI: 10.1109/ICMTS.2005.1452262 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Extraction of critical dimension reference feature CDs from new test structure using HRTEM imaging R. A. Allen, A. Hunt1, C. E. Murabito, B. Park, W. F. Guthrie2, M. W. Cresswell Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Accurel Systems International Corporation, Sunnyvale, CA, USA 2Statistical Engineering Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2005.1452203 HOVER FOR ABSTRACT | PDF Xplore | |
| 2005 | Test structure for performance evaluation of 3 dimensional FinFETs Young Joon Ahn, Hye Jin Cho, Hee Soo Kang, Choong-Ho Lee, Chul Lee, Jae-man Yoon, Tae Yong Kim, Eun Suk Cho, Suk-kang Sung, Donggun Park, Kinam Kim, Byung-Il Ryu Device Research Team, Research and Development center, Samung Electronics Company, Yongin si, Gyeonggi, South Korea DOI: 10.1109/ICMTS.2005.1452221 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Transistor test structures for leakage current analysis of partial SOI Kyoung Hwan Yeo, Chang Woo Oh, Sung-Min Kim, Min-Sang Kim, Sung-Young Lee, Ming Li, Hye-Jin Cho, Eun-Jung Yoon, Sung-Hwan Kim, Jeong-Dong Choe, Dong-Won Kim, Donggun Park, Kinam Kim Advanced Technology Development Team, R&D Center, Samsung Electronics Company Limited, Yongin si, Gyeonggi, South Korea DOI: 10.1109/ICMTS.2004.1309488 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Characterization and model of 4-terminal RF CMOS with bulk effect M. T. Yang, Y. J. Wang, T. J. Yeh, P. P. C. Ho, Y. T. Chia, K. L. Young Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309477 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Development of a 90 nm large-scale TEG for evaluation and analysis of signal integrity, yield and variation M. Yamamoto, Y. Hayasi1, H. Endo1, H. Masuda Semiconductor Technology Academic Research Center (STARC), Kouhoku-ku, Yokohama, Japan 1Hitachi ULSI Systems Co., Ltd, Tokyo, Japan DOI: 10.1109/ICMTS.2004.1309309 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Direct extraction methodology for geometry-scalable RF-CMOS models S. P. Voinigescu, M. Tazlauanu1, P. C. Ho2, M. T. Yang2 ECE Department, University of Toronto, Toronto, ONT, Canada 1Quake Technologies, Inc., Ottawa, ONT, Canada 2Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309486 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Measuring the span of stress asymmetries on high-precision matched devices H. P. Tuinhout, A. Bretveld1, W. C. M. Peters2 Philips Research, Eindhoven, Netherlands 1Philip Consumer Electronics IC-Laboratory, Eindhoven, Netherlands 2Philips Semiconductors, Nijmegen, Netherlands DOI: 10.1109/ICMTS.2004.1309463 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | | Test chip for the development and evaluation of test structures for measuring stress in metal interconnect J. G. Terry, S. Smith, A. J. Walton, A. M. Gundlach, J. T. M. Stevenson, A. B. Horsfall1, K. Wang1, J. M. M. dos Santos1, S. M. Soare2, N. G. Wright1, A. G. O'Neill1, S. J. Bull2 Institute for Integrated Micro and Nano Systems, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1School of Electrical, Electronic and Computer Engineering, University of Newcastle, Newcastle, UK 2School of Chemical Engineering and Advanced Materials, University of Newcastle, Newcastle, UK DOI: 10.1109/ICMTS.2004.1309304 HOVER FOR ABSTRACT | PDF Xplore |
| 2004 | Further study of VTH-mismatch evaluation circuit K. Terada, K. Fukeda Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan DOI: 10.1109/ICMTS.2004.1309470 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | New device structure for 18-V, high-performance SOI complementary bipolar LSIs using array transistors and flexible U-grooves Y. Tamaki, K. Tsuji1, O. Ohtani2, H. Nonami, T. Tomatsuri, E. Yoshida, M. Hamamoto, N. Nakazato3 Device Development Center, Hitachi Ltd., Tokyo, Japan 1Hitachi ULSI Systems Company Limited, Ome, Tokyo, Japan 2Renesas Eastern Japan Semiconductor, Inc., Takasaki, Gunma, Japan 3Mechanical Engineering Research Laboratory, Hitachi Ltd., Tsuchiura, Ibaraki, Japan DOI: 10.1109/ICMTS.2004.1309468 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Error evaluation of C-V characteristic measurements in ultra-thin gate dielectrics H. Suto, S. Inaba, K. Ishimaru SoC Research & Development Center, Toshiba Corporation Semiconductor Company, Yokohama, Kanagawa, Japan DOI: 10.1109/ICMTS.2004.1309483 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Test structures for CD and overlay metrology on alternating aperture phase-shifting masks S. Smith, M. McCallum1, A. J. Walton, J. T. M. Stevenson, P. D. Harris1, A. W. S. Ross, A. C. Hourd2, L. Jiang School of Engineering and Electronics, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1Nikon Precision Europe, West Lothian, UK 2Compugraphics International Limited, Glenrothes, Fife, UK DOI: 10.1109/ICMTS.2004.1309296 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Varactor modeling methodology for simulation of the VCO tuning sensitivity D. Siprak, A. Roithrneier1 Infineon Technologies AG, CL TD SIM PXI, Munich, Germany 1NA DOI: 10.1109/ICMTS.2004.1309494 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | An accurate and scalable differential inductor design kit [RFIC applications] C. B. Sia, K. W. Chan, C. Q. Geng, W. Yang, K. S. Yeo1, M. A. Do1, J. G. Ma1, S. Chu2, K. W. Chew2 Advanced RFIC (S) Private Limited, Singapore 1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 2Chartered Semiconductor Manufacturing Private Limited, Singapore DOI: 10.1109/ICMTS.2004.1309303 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | A novel RFCMOS process monitoring test structure C. B. Sia, B. H. Ong1, K. M. Lim, K. S. Yeo1, M. A. Do1, J. G. Ma1, T. Alam2 Advanced RFIC (S) Private Limited, Singapore 1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 2Cascade Microtech, Inc., OR, USA DOI: 10.1109/ICMTS.2004.1309299 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | An accurate measurement and extraction method of gate to substrate overlap capacitance [MOSFETs] M. Shimasue, Y. Kawahara, T. Sano, H. Aoki MODECH, Inc., Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.2004.1309498 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | A new analytical inductance extraction technique of on-wafer spiral inductors H. Shima, T. Matsuoka, K. Taniguchi Department of Electronics and Information Systems, Osaka University, Suita, Osaka, Japan DOI: 10.1109/ICMTS.2004.1309495 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Leakage current correction in quasi-static C-V measurements J. Schmitz, M. H. H. Weusthof, A. J. Hof MESA Research Institute, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS.2004.1309475 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability S. Saxena, S. Minehane, J. Cheng, M. Sengupta, C. Hess, M. Quarantelli, G. M. Kramer, M. Redford PDF Solutions, Inc.orporated, Richardson, TX, USA DOI: 10.1109/ICMTS.2004.1309492 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | From analog to RF design [review] W. Sansen ESAT-MICAS, Katholieke Universiteit Leuven, Leuven, Belgium DOI: 10.1109/ICMTS.2004.1309298 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Characterization & modeling of low electric field gate-induced-drain-leakage [MOSFET] D. Rideau, A. Dray, F. Gilibert, F. Agut, L. Giguerre1, G. Gouget, M. Minondo, A. Juge STMicroelectronics, Central R&D, Device Modeling, Crolles, France 1Philips, Central R&D, Device Modeling, Crolles, France DOI: 10.1109/ICMTS.2004.1309469 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | New test structure for high resolution leakage current and capacitance measurements in CMOS imager applications F. Odiot, H. Brut, J. Hurwitz1, L. Grant1, B. Dunne2, J. M. Moragues2 Central R&D, STMicroelectronics, Crolles, France 1Imaging Division, STMicroelectronics, Edinburgh, UK 2STMicroelectronics, Rousset, France DOI: 10.1109/ICMTS.2004.1309490 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Test structure for fixing OPC of 200 nm pitch via chain using inner and outer dummy via array T. Nasuno, Y. Matsubara, A. Minami, N. Uchida, H. Kobayashi, H. Aoyama, H. Tsuda, K. Tsujita, W. Wakamiya, N. Kobayashi Research Department2, Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.2004.1309295 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | On-chip di/dt detector circuit for power supply line T. Nakura, M. Ikeda, K. Asada Department of Electronic Engineering, University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.2004.1309294 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Variation status in 100nm CMOS process and below K. Nagase, S. I. Ohkawa, M. Aoki, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan DOI: 10.1109/ICMTS.2004.1309491 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Evaluating high leakage effects of low VTH circuits using high VTH devices T. Miyazaki, T. Sakurai Institute of Industrial Science, University of Tokyo, Meguro-ku, Tokyo, Japan DOI: 10.1109/ICMTS.2004.1309487 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Test circuits for extracting sub-100nm MOSFET technology variations with the MOSFET model HiSIM A. Miura-Mattausch, S. Matsumoto, K. Mizoguchi, D. Miyawaki, F. J. Mattausch, S. Itoh1, K. Morikawa1 Department of Electrical Engineering, Hiroshima University, Higashihiroshima, Japan 1Semiconductor Technology Academic Research Center, Japan DOI: 10.1109/ICMTS.2004.1309493 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Gate-last MISFET structures and process for high-k and metal gate MISFETs characterization T. Matsuki, K. Torii, T. Maeda, H. Syoji, K. Kiyono, Y. Akasaka, K. Hayashi, N. Kasai, T. Arikado Semiconductor Leading Edge Technologies, Inc., Ibaraki-ken, Japan DOI: 10.1109/ICMTS.2004.1309310 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | A test structure for two-dimensional analysis of MOSFETs by hot-carrier-induced photoemission T. Matsuda, A. Muramatsu, H. Iwata, T. Ohzone1, K. Yamashita2, N. Koike2, K. Tatsuuma2 Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan 1Faculty of Computer Science and System Engineering, Okayama Prefectural University, Soja, Okayama, Japan 2ULSI Process Technology Development Center, Semiconductor Company, Matsushita Elecrric Indusrrial Company Limited, Minami, Kyoto, Japan DOI: 10.1109/ICMTS.2004.1309474 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Device characterizations and physical models of strained-Si channel CMOS T. Maeda, T. Numata1, T. Mizuno2, K. Usuda2, A. Tanabe2, T. Tezuka2, S. Nakaharai2, J. Koga2, T. Irisawa2, Y. Moriyama2, N. Hirashita2, N. Sugiyama2, S. Takagi2 University of Tokyo, Kawasaki, Japan 1MIRAI-ASET, MIRAI-AIST, Kawasaki, Japan 2Kawasaki, Japan DOI: 10.1109/ICMTS.2004.1309466 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | A test structure to verify the robustness of silicided N+/P+ interface Cheng-Yao Lo, Shyue-Shyh Lin, Wei-Ming Chen, Yuh-Jier Mii Advanced Logic-1, Logic Technology Division, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309473 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | An impedance-phase angle (Z-theta) method for capacitance extraction of ultra-thin gate dielectrics at intermediate frequency [MOS devices] J. Lin, Chien-Hwa Chang, S. Prasad, W. Loh Characterization and Reliability, LSI Logic Corporation, Milpitas, CA, USA DOI: 10.1109/ICMTS.2004.1309497 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | An accurate RF CMOS gate resistance model compatible with HSPICE H. W. Lin, S. S. Chung, S. C. Wong1, G. W. Huang2 Department of Electronic Engineering, National Chiao Tung University, Taiwan 1Ali Corporation, Taipei, Taiwan 2National Nano Device Laboratory, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309484 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Implementing laser based failure analysis methodologies using test vehicles D. Lewis, V. Pouget, F. Beaudoin1, T. Beauchene, G. Haller2, R. Desplat3, P. Perdu3, P. Fouillat IXL Laboratory, Talence, France 1Thales Microelectronics, Toulouse, France 2STMicroelectronics, Rousset, France 3CNES, Toulouse, France DOI: 10.1109/ICMTS.2004.1309482 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Merits and limitations of circular TLM structures for contact resistance determination for novel III-V HBTs J. H. Klootwijk, C. E. Timmering Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2004.1309489 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | An array cell transistor test structure for the leakage current analysis of stacked capacitor DRAMs with diagonal cell scheme Young Pil Kim, Beom Jun Jin, Gi-Sung Yeo, Sun-Ghil Lee, Siyoung Choi, Uin Chung, Joo Tae Moon, Sang U Kim Serniconductor R&D Center, Sarrisung Electronics Company Limited, Yongin si, South Korea DOI: 10.1109/ICMTS.2004.1309467 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Test structures to verify ESD robustness of on-glass devices in LTPS technology Ming-Dou Ker, Chih-Kang Deng, Sheng-Chieh Yang1, Yaw-Ming Tasi1 Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 1Advanced Technology Research Center, Toppoly Optoelectronics Corporation, Miaoli, Taiwan DOI: 10.1109/ICMTS.2004.1309293 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Characterization on ESD devices with test structures in silicon germanium RF BiCMOS process Ming-Dou Ker, Woei-Lin Wu, Chyh-Yih Chang1 Nanoelectronics & Gigascale Systems Laboratory, National Chiao-Tung University, Hsinchu, Taiwan 1Product and ESD Engineering Department, Industrial Technology Research Institute, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309292 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | A novel method to obtain 3-port network parameters from 2-port measurements [MOSFET example] A. Jha, J. M. Vasi, S. C. Rustagi1, M. B. Patil Department of Electrical Engineering, IIT Bombay, Mumbai, India 1Institute of Microelectronics, Singapore DOI: 10.1109/ICMTS.2004.1309302 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Experimental measurements and extraction of the silicide/silicon interface resistance for designing high performance MOS transistor Jae-Hun Jeong, Hoon Lim, Soon-Moon Jung, Joon Bum Park, Jae Kyun Park, Kinam Kim Advanced Technology Development Team, Samsung Electronics Co., Ltd, Kiheung-Eup, Yongin-City, Kyungki-Do, Korea (ROK) DOI: 10.1109/ICMTS.2004.1309496 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Optimal frequency range selection for full C-V characterization above 45MHz for ultra thin (1.2-nm) nitrided oxide MOSFETs W. Jeamsaksiri, A. Mercha, J. Ramos, S. Decoutere, F. N. Cubaynes1 Inter University Micro Electronics Center, Leuven, Belgium 1Philips Research Leuven, Leuven, Belgium DOI: 10.1109/ICMTS.2004.1309500 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Design and measurements of test element group wafer thinned to 10 µm for 3D system in package A. Ikeda, T. Kuwata, S. Kajiwara, T. Fujimura, H. Kuriyaki, R. Hattori, H. Ogi1, K. Hamaguchi1, Y. Kuroki Graduate School of Information Science and Electrical Engineering, Department of Electronics, Kyushu University, Fukuoka, Japan 1Hara Seiki Industry Company Limited, Minamata, Kumamoto, Japan DOI: 10.1109/ICMTS.2004.1309471 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Method of and test structures for measuring intra-layer coupling capacitance based on charge based capacitance measurement technique [IC interconnections] Kai-Ye Huang, Chuan-Jane Chao Winbond Electronics Corporation, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309480 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Optimization of 2.14 um2 6T-SRAM cell by using cell-like test structures S. Hsieh, R. F. Tsui, W. Lin, J. J. Liaw, K. Y. Doong, C. . -M. M. Wu Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan, R. O. C. DOI: 10.1109/ICMTS.2004.1309481 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Impact of pocket implant on MOSFET mismatch for advanced CMOS technology J. Mc Ginley, O. Noblanc1, C. Julien2, S. Parihar1, K. Rochereau1, R. Difrenza2, P. Llinares1 Philips Semiconductors, Crolles Cedex, France 1STMicroelectronics, Crolles Cedex, France 2Motorola Inc., Crolles Cedex, France DOI: 10.1109/ICMTS.2004.1309464 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | A new test circuit for the matching characterization of npn bipolar transistors J. Einfeld, U. Schaper, U. Kollmer, P. Nelle1, J. Englisch1, M. Stecher1 Corporate Logic, Infineon Technologies, Munich, Germany 1Automotive & Industrial, Infineon Technologies, Munich, Germany DOI: 10.1109/ICMTS.2004.1309465 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Electrical characterization of model-based dummy feature insertion in Cu interconnects K. Y. Y. Doong, K. . -C. Lin1, T. . -C. Tseng, Y. C. Lu, S. C. Lin, L. J. Hung, P. S. Ho, S. Hsieh, K. L. Young, M. S. Liang Taiwan Semiconductor Manufacturing Corporation, Shin-Chu, Taiwan 1Taiwan Semiconductor Manufacturing Corp. Shinchu Taiwan, Shinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309307 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | A test chip to characterise P-MOS transistors produced using a novel organometallic material M. H. Dicks, G. M. Broxton1, J. Thomson2, J. Lobban2, A. M. Gundlach, J. T. M. Stevenson, A. J. Walton Institute for Integrated Micro and Nano Systems, Scottish Microelectronics Centre, School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK 1Electronic Engineering & Physics Division, University of Dundee, Dundee, UK 2Division of Physical and Inorganic Chemistry, University of Dundee, Dundee, UK DOI: 10.1109/ICMTS.2004.1309476 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | High frequency test structures definition for the study of flip-chip process effects on inductor coupling in a BiCMOS process C. Clement, B. Van Haaren, D. Gloria ST Microelectronics, Central R&D, Crolles, France DOI: 10.1109/ICMTS.2004.1309478 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Process and device reliability characterization techniques for advanced CMOS technology: the issues and methodologies S. S. Chung Department of Electmnic Engineering, National Chiao Tung University, Taiwan DOI: 10.1109/ICMTS.2004.1309308 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | MOSFET drain and induced-gate noise modeling and experimental verification for RF IC design Chih-Hung Chen, Feng Li, Yuhua Cheng1 Department of Electrical and Computer Engineering, McMaster University, Hamilton, ONT, Canada 1Skyworks Solutions, Inc., Irvine, CA, USA DOI: 10.1109/ICMTS.2004.1309300 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Flicker noise characterization of Co-silicide/SiGe contacts using TLM test structures Kun-Ming Chen, Guo-Wei Huang National Nano Device Laboratories, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2004.1309472 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Development and extraction of high-frequency SPICE models for metal-insulator-metal capacitors W. Z. Cai, S. C. Shastri, M. Azam, C. Hoggatt, G. H. Loechelt, G. M. Grivna, Y. Wen, S. Dow Silicon IC Technology Development, ON Semiconductor Corporation, Phoenix, AZ, USA DOI: 10.1109/ICMTS.2004.1309485 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Accuracy improvement of the "Single Pattern Driver" method for the characterization of interconnect capacitance in the context of nanometer technology development H. Brut, S. Martin, B. Froment STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2004.1309501 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | A novel measurement method of the spatial carrier lifetime profile based on the OCVD technique S. Bellone, G. D. Licciardo, H. C. Neitzert Depart of Information Engineering and Electrical Engineering, University of Salerno, Fisciano, Salerno, Italy DOI: 10.1109/ICMTS.2004.1309311 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Transmission line pulse measurements: a tool for developing ESD robust integrated circuits R. A. Ashton White Mountain Laboratories, Phoenix, AZ, USA DOI: 10.1109/ICMTS.2004.1309291 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Test chip characterization of X architecture diagonal lines for SoC design N. D. Arora, L. Song, S. Shah, K. Joshi, K. Thumaty, A. Fujimura, J. P. Schoellkopf1, H. Brut1, M. Smayling2, T. Nagata2 Cadence Design Systems, Inc., San Jose, CA, USA 1STMicroelectronics, Crolles, France 2Applied Materials, Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS.2004.1309305 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Design guide and process quality improvement for treatment of device variations in an LSI chip M. Aoki, S. Ohkawa, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan DOI: 10.1109/ICMTS.2004.1309479 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | Recent developments in producing test-structures for use as critical dimension reference materials R. A. Allen, R. Patel, M. W. Cresswell, C. E. Murabito, B. Park, M. D. Edelstein, L. W. Linholm Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2004.1309297 HOVER FOR ABSTRACT | PDF Xplore | |
| 2004 | A novel test-structure for detail interconnect fabric diagnosis for 90nm process S. Akutsu, N. Ishihara1, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan 1Fuji Research Institute Company, Tokyo, Japan DOI: 10.1109/ICMTS.2004.1309306 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Test structures for analyzing the mechanisms of wafer chemical contaminant removal J. Yan, H. J. Barnaby1, B. Vermiere2, T. Peterson, F. Shadman Chemical & Environmental Engineering, University of Arizona Tucson, Tucson, AZ, USA 1Electrical & Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA 2Ridgetop Group, Inc., Tucson, AZ, USA DOI: 10.1109/ICMTS.2003.1197463 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Development of a large-scale TEG for evaluation and analysis of yield and variation M. Yamamoto, H. Endo1, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan 1Hitachi ULSI Systems Company Limited, Tokyo, Japan DOI: 10.1109/ICMTS.2003.1197376 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | New evaluation method for reliability of poly-Si thin film transistors using pico-second time-resolved emission microscope Y. Uraoka, N. Hirai1, H. Yano, T. Hatayama, T. Fuyuki Materials Science, Nara Institute of Science and Technology, Ikoma, Nara, Japan 1Hamamatst Photonics, Ikoma, Nara, Japan DOI: 10.1109/ICMTS.2003.1197457 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Current mirror test structures for studying adjacent layout effects on systematic transistor mismatch H. P. Tuinhout, A. Bretveld1, W. C. M. Peters2 Philips Research, Eindhoven, Netherlands 1Philips Consumer Electronics IC-Laboratories, Eindhoven, Netherlands 2Philips Semiconductors, Nijmegen, Netherlands DOI: 10.1109/ICMTS.2003.1197465 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Evaluation of mobility in the MOSFET with high leakage current O. Tonomura, Y. Shimamoto, K. Torii, M. Hiratani, S. Saito, J. Yugami Central Research Laboratory Hitachi, Ltd., Tokyo, Japan DOI: 10.1109/ICMTS.2003.1197407 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | A test circuit for measuring MOSFET threshold voltage mismatch K. Terada, M. Eimitsu Faculty of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan DOI: 10.1109/ICMTS.2003.1197466 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | An improved SPICE model for ferroelectric liquid crystal microdisplays S. Smith, A. J. Walton, I. Underwood, C. Miremont, D. G. Vass1, W. J. Hossack1, M. Birch2, A. Maartney3, R. Nicol4 School of Engineering and Electronics, The University of Edinburgh, Edinburgh, U.K 1Department of Physics and Astronomy, The University of Edinburgh, Edinburgh, U.K 2CRL Opto Ltd., Dalgety Bay, Dunfermline, U.K 3NA 4MicroVue Limited, Dalgety Bay, Dunfermline, U.K DOI: 10.1109/ICMTS.2003.1197438 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Study on STI mechanical stress induced variations on advanced CMOSFETs Y. M. Sheu, K. Y. Y. Doong1, C. H. Lee1, M. J. Chen, C. H. Diaz1 Department of Electronics Engineering, SBIP, National Chiao Tung University, Hsinchu, Taiwan 1Taiwan Semiconductor Manufacturing Company Limited, Taiwan DOI: 10.1109/ICMTS.2003.1197462 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Test structure design considerations for RF-CV measurements on leaky dielectrics J. Schmitz, F. N. Cubaynes1, R. J. Havens2, R. de Kort2, A. J. Scholten2, L. F. Tiemeijer2 Philips Research Leuven, University of Twente, Netherlands 1Philips Research Leuven, Leuven, Belgium 2Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2003.1197458 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | BSIM3 RF models for MOS transistors: a novel technique for substrate network extraction S. C. Rustagi, Huailin Liao, Jinglin Shi, Yong Zhong Xiong Institute of Microelectronics, Singapore DOI: 10.1109/ICMTS.2003.1197427 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | An electrical monitor of deep trench depth T. Roggenbauer, V. Khemka, V. Parthasarathy, I. Puchades, R. Zhu Motorola SPS, Chandler, AZ, USA DOI: 10.1109/ICMTS.2003.1197363 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Series resistance estimation and C(V) measurements on ultra thin oxide MOS capacitors D. Rideau, P. Scheer, D. Roy, G. Gouget, M. Minondo, A. Juge STMicroelectronics, Central Research and Development, Device Modeling, Crolles, France DOI: 10.1109/ICMTS.2003.1197460 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Characterization and modeling of MOSFET mismatch of a deep submicron technology M. Quarantelli, S. Saxena, N. Dragone, J. A. Babcock, C. Hess, S. Minehane, S. Winters, Jianjun Chen, H. Karbasi, C. Guardiani PDF Solutions, Inc.orporated, San Jose, CA, USA DOI: 10.1109/ICMTS.2003.1197468 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Impact of gate current on first order parameter extraction in sub-0.1 µm CMOS technologies N. Planes, A. Dray, E. Robilliart, H. Brut Central Research and Development, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2003.1197433 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | The negative capacitance effect on the C-V measurement of ultra thin gate dielectrics induced by the stray capacitance of the measurement system Y. Okawa, H. Norimatsu, H. Suto1, M. Takayanagi1 Hachioji Semiconductor Parametric Test Division, Agilent Technology International, Hachioji, Tokyo, Japan 1SoC Research and Development Center, Semiconductor Company, Toshiba Corporation, Japan DOI: 10.1109/ICMTS.2003.1197461 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Analysis and characterization of device variations in an LSI chip using an integrated device matrix array S. Ohkawa, M. Aoki, H. Masuda Semiconductor Technology Academic Research Center, Yokohama, Japan DOI: 10.1109/ICMTS.2003.1197386 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Test structures for quantum efficiency characterization for silicon image sensors F. Odiot, J. Bonnouvrier, C. Augier, J. M. Raynor1 ST Microelectronics, Central Research and Development Laboratory, Crolles, France 1Imaging Division, STMicroelectronics, Edinburgh, UK DOI: 10.1109/ICMTS.2003.1197366 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Polysilicon resistive heated scribe lane test structure for productive wafer level reliability monitoring of NBTI W. Muth, A. Martin, J. von Hagen, D. Smeets, J. Fazekas Infineon Technologies, Munich, Germany DOI: 10.1109/ICMTS.2003.1197440 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | A combined test structure with ring oscillator and inverter chain for evaluating optimum high-speed/low-power operation T. Matsuda, H. Iwata, T. Ohzone1, K. Yamashita2, N. Koike2, K. Tatsuuma2 Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan 1Faculty of Computer Science and System Engineering, Okayama Prefectural University, Soja, Okayama, Japan 2WLSI Process Technology Development Center, Semiconductor Company, Matsushita Elecrric Indusrrial Company Limited, Minami, Kyoto, Japan DOI: 10.1109/ICMTS.2003.1197390 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | | An integrated test chip for the complete characterization and monitoring of a 0.25µm CMOS technology that fits into five scribe line structures 150µm by 5000µm R. Lefferts, C. Jakubiec Accelerant Networks, Inc., Beaverton, OR, USA DOI: 10.1109/ICMTS.2003.1197382 HOVER FOR ABSTRACT | PDF Xplore |
| 2003 | A new technique to extract intrinsic and extrinsic base-collector capacitances of bipolar transistors using Y-parameter equations Seonghearn Lee Department of Electronic Engineering, Hankuk University of Foreign Studies, Yongin si, Gyeonggi, South Korea DOI: 10.1109/ICMTS.2003.1197431 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Improvement of poly emitter n-p-n transistor matching in a 0.6 micron mixed signal technology G. Lau, W. Einbrodt, W. Sieber X-FAB Semiconductor Foundries AG, Erfurt, Germany DOI: 10.1109/ICMTS.2003.1197467 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Reliable extraction of interface states from charge pumping method in ultra-thin gate oxide MOSFETs H. C. Lai, N. K. Zous, W. J. Tsai, T. C. Lu, Tahui Wang1, Y. C. King, Sam Pan Advance Device Engineering Department Si-Laboratory, Macronix International Company Limited, Hsinchu, Taiwan 1Institute of Electronics Engineering, National Tsing Hua University, Taiwan DOI: 10.1109/ICMTS.2003.1197421 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Substrate resistance modeling for noise coupling analysis S. Kristiansson, S. P. Kagganti1, T. Ewert2, F. Ingvarson, J. Olsson2, K. O. Jeppson Solid State Elcctronics Laboratory, Department of Microelectronics, Chalmers University of Technology, Gothenburg, Sweden 1Solid State Electronics Laboratory, Department of Microelectronics, Chalmers University of Technology, Gothenburg, Sweden 2ängström Laboratory, Solid State Electronics, University of Uppsala, Uppsala, Sweden DOI: 10.1109/ICMTS.2003.1197429 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's Ming-Dou Ker, Jeng-Jie Peng1, Hsin-Chin Jiang1 Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Taiwan 1ESD Protection Technology Department, SoC Technology Center, Industrial Technology and Research Institute, Taiwan DOI: 10.1109/ICMTS.2003.1197455 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Optimisation of integrated RF varactors on a 0.35 µm BiCMOS technology S. C. Kelly, J. A. Power, M. O'Neill Analog Devices, Inc., Limerick, Ireland DOI: 10.1109/ICMTS.2003.1197426 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Scalable ground-shielded open fixture applied to de-embedding techniques T. Kaija, E. Ristolainen Institute of Electronics, Tampere University of Technology, Tampere, Finland DOI: 10.1109/ICMTS.2003.1197406 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Test time reduction methods for yield test structures C. Hess, H. Read, J. Ren, L. H. Weiland, Jianjun Cheng1, Chock Gan1, H. Karbasi1, S. Winters1 PDF Solutions, Inc.orporated, San Jose, CA, USA 1PDF Solutions, Inc.orporated, San Diego, CA, USA DOI: 10.1109/ICMTS.2003.1197384 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | An advanced defect-monitoring test structure for electrical measurements and defect localization Y. Hamamura, T. Kumazawa, K. Tsunokuni1, A. Sugimoto2, H. Asakura2 Production Engineering Research Laboratory, Hitachi and Limited, Yokohama, Japan 1Semiconductor & Integrated Circuits, Hitachi and Limited, Tokyo, Japan 2Device Development Center, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.2003.1197372 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Application of the TRM self-calibration on standard silicon substrates R. Gillon, W. Tatinian, B. Landat1 AMI Semiconductors, Inc., Oudenaarde, Belgium 1AMI Semicond. bvba, Oudenaarde, Belgium DOI: 10.1109/ICMTS.2003.1197425 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Process stress estimation for MEMS RF switches with capacitive test structures L. Ferrario, C. Armaroli, B. Margesin, M. Zen, G. Soncini Microsystems Division, ITC IRST, Trento, Italy DOI: 10.1109/ICMTS.2003.1197369 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Thermal design considerations for Greek cross test structures S. Enderling, M. H. Dicks, S. Smith, J. T. M. Stevenson, A. J. Walton School of Engineering and Electronics, The University of Edinburgh, Edinburgh, U.K. DOI: 10.1109/ICMTS.2003.1197361 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Design and integration of electrical-based dimensional process-window checking infrastructure K. Y. Y. Doong, R. C. J. Wang, J. C. H. Huang1, S. C. Lin, L. J. Hung, S. Z. Lee, K. L. Young Taiwan Semiconductor Manufacturing Corporation, Hsinchu, Taiwan 1Silicon Canvas, Inc., San Jose, USA DOI: 10.1109/ICMTS.2003.1197423 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Impact of grain number fluctuations in the MOS transistor gate on matching performance R. Difrenza, J. C. Vildeuil, P. Llinares, G. Ghibaudo1 STMicroelectronics, Crolles, France 1IMEP, Grenoble, France DOI: 10.1109/ICMTS.2003.1197469 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Use of test structures for characterising a novel photosensitive organometallic material for MOS processes M. H. Dicks, G. M. Broxton1, J. Thomson2, J. Lobban2, J. T. Stevenson, A. J. Walton Scottish Microelectronics Centre, School of Engineering and Electronics, University of Edinburgh, Edinburgh, UK 1Department of Applied Physics and Electronic & Mechanical Engineering, University of Dundee, Dundee, UK 2Division of Physical and Inorganic Chemistry, University of Dundee, Dundee, UK DOI: 10.1109/ICMTS.2003.1197362 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Influence of masking layer stress on anisotropic silicon etching in TMAH solutions M. Decarli, V. Guarnieri1, R. Pal, F. Giacomozzi1, B. Margesin1, M. Zen1 Dept. of Information and Communication Technology, University of Trento, Trento, Italy 1ITC-IRST, Povo, Trento, Italy DOI: 10.1109/ICMTS.2003.1197364 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Test structures and test methodology for developing high voltage ESD protection A. Concannon, V. Vashchenko, M. ter Beek, P. Hopper National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2003.1197456 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Automatic, wafer-level, low frequency noise measurements for the interface slow trap density evaluation J. A. Chroboczek Commissariat à ľEnergie Atomique, Lahoratoire dElectronique et de la Technologie pour ľlnfomatlque, CEA-DRT-LETI, Grenoble, France DOI: 10.1109/ICMTS.2003.1197409 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Fast and precise subthreshold slope method for extracting gate capacitive coupling coefficient in flash memory cells Caleb Yu-Sheng Cho, Ming-Jer Chen, Chiou-Feng Chen1 Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan 1Actran Systems, Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS.2003.1197459 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Evaluation of mechanical properties by electrostatic loading of polycrystalline silicon beams R. Cambie, F. Carli1, C. Combi2 Department of Electrical Engineering, University of Pavia, Italy 1Department of Structural Mechanics, University of Pavia, Italy 2MEMS Development Unit, STMicroelectronics, Milan, Italy DOI: 10.1109/ICMTS.2003.1197368 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | A hybrid table/analytical approach to MOSFET modelling V. Bourenkov, K. G. McCarthy1, A. Mathewson National Microelectronics Research Centre, University College Cork, Ireland 1Department of Electrical and Electronic Engineering, University College Cork, Ireland DOI: 10.1109/ICMTS.2003.1197435 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Measuring the effects of process variations on circuit performance by means of digitally-controllable ring oscillators A. Bassi, A. Veggetti1, L. Croce1, A. Bogliolo2 DI-University of Ferrara, Ferrara, Italy 1STMicroelectronics, Agrate-Brianza, Milan, Italy 2STI-Universita di Urbino, Urbino, Italy DOI: 10.1109/ICMTS.2003.1197464 HOVER FOR ABSTRACT | PDF Xplore | |
| 2003 | Junction-isolated electrical test structures for critical dimension calibration standards R. A. Allen, M. W. Cresswell, L. W. Linholm Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.2003.1197360 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | A robust and production worthy addressable array architecture for deep sub-micron MOSFET's matching characterization S. B. Yeo, J. Bordelon1, S. Chu2, M. F. Li, B. A. Tranchina3, M. Harward1, L. H. Chan2, A. See2 The National University of Singapore, Singapore 1Telcordia Technologies, Inc., USA 2Chartered Semiconductor Mfg. Ltd, Singapore 3TestChip Technologies, Inc DOI: 10.1109/ICMTS.2002.1193201 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | | Design and characterisation of a high precision resistor ladder test structure H. P. Tuinhout, G. Hoogzaad1, M. Vertregt, R. L. J. Roovers, C. Erdmann2 Prof. Holstlaan 4 (WAY41), Philips Research, Eindhoven, Netherlands 1Philips Semiconductors, Delft, Netherlands 2Philips Semiconductors, Caen, France DOI: 10.1109/ICMTS.2002.1193200 HOVER FOR ABSTRACT | PDF Xplore |
| 2002 | A test circuit for measuring standard deviations of MOSFET channel conductance and threshold voltage K. Terada, M. Sumida Faculty of Information Sciences, Hiroshima City University, Asaminami, Hiroshima, Japan DOI: 10.1109/ICMTS.2002.1193172 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Novel charge pumping method without using MOS transistor for SOI wafer inspection T. Takami, H. Yoshida, T. Uchihashi, S. Kishino Department of Electronics, Himeji Institute of Technology, Himeji, Japan DOI: 10.1109/ICMTS.2002.1193194 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Strategies and test structures for improving isolation between circuit blocks D. Szmyd, L. Gambus1, A. Wilbanks2 Philips Semiconductors, Hopewell Junction, NY, United States 1Philips Semiconductors, Caen, France 2Philips Semiconductors, Albuquerque, NM, United States DOI: 10.1109/ICMTS.2002.1193177 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | BSIM4.1 DC parameter extraction on 50 nm n-pMOSFETs D. Souil, G. Guegan, G. Bertrand, O. Faynot, S. Deleonibs1, G. Ghibaudo2 CEA-LETI, Laboratoire d'Electronique et des Technologies de l'Information, Grenoble Cedex 9, France 1NA 2Institut de Microélectronique, d'Electromagnétisme et de Photonique (IMEP), Grenoble Cedex 1, France DOI: 10.1109/ICMTS.2002.1193182 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Test structures for the electrical characterisation of platinum deposited by focused ion beam S. Smith, A. J. Walton, S. Bond, A. W. S. Ross, J. T. M. Stevenson, A. M. Gundlach Department of Electronics and Electrical Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2002.1193189 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Electrical CD characterisation of binary and alternating aperture phase shifting masks S. Smith, M. McCallum1, A. J. Walton, J. T. M. Stevenson Department of Electronics and Electrical Engineering, Scottish Mieroelectronics Centre, University of Edinburgh, Edinburgh, UK 1Xikon Court, Nikon Precision Europe, Livingston, UK DOI: 10.1109/ICMTS.2002.1193162 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Methodology for defect impact studies under conditions of low electrical testing coverage A. Skumanich, E. Ryabova Applied Materials, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2002.1193193 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Metallization proximity studies for copper spiral inductors on silicon C. B. Sia, K. S. Yeo1, Shao-Fu Chu, Z. Zeng, T. H. Lee Chartered Semiconductor Manufacturing Private Limited, Singapore 1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore DOI: 10.1109/ICMTS.2002.1193165 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Test structure for precise statistical characteristics measurement of MOSFETs Y. Shimizu, M. Nakamura, T. Matsuoka, K. Taniguchi Department of Electronics and Information Systems, Osaka University, Suita, Osaka, Japan DOI: 10.1109/ICMTS.2002.1193170 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | A test structure for the design of thermal flow sensors N. Sabate, I. Gracia, J. Santander, C. Cane CSIC, Centre National de Microelectronica, Bellaterra, Spain DOI: 10.1109/ICMTS.2002.1193180 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Wafer-level characterization of EEPROM tunnel oxide using a fast floating-gate technique and a realistic memory cell-based test structure S. Renard, P. Boivin, J. L. Autran1 STMicroelectronics, Zone Industrielle de Rousset, Rousset, France 1L2MP, UMR CNRS 6137, Université Ax-Marseille 1, Bâtiment IRPHE, Marseilles, France DOI: 10.1109/ICMTS.2002.1193187 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Low current application dedicated process characterization method W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella1, B. Majoux1, V. Chowdhury1 LIRMM UMR C5506 CNRS, Université de Montpellier II, Montpellier, France 1STMicroelectronics, Grenoble, France DOI: 10.1109/ICMTS.2002.1193168 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | CV doping profiling of boron out-diffusion using an abrupt and highly doped arsenic buried epilayer C. J. Ortiz, L. K. Nanver, W. D. van Noort, T. L. M. Scholtes, J. W. Slotboom Laboratory of ECTM, DIMES, Delft University of Technnology, Delft, Netherlands DOI: 10.1109/ICMTS.2002.1193176 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | A test structure for spectrum analysis of hot-carrier-induced photoemission from subquarter-micron CMOSFETs S. Odanaka, K. Yamashita, N. Koike1, K. Tatsuuma2 Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan 1Cybermedia Center, Osaka University, Osaka, Japan 2ULSI Process Technology Development Center, Matsushita Electric Ind. Co., Ltd., Kyoto, Japan DOI: 10.1109/ICMTS.2002.1193178 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Compact model development for a new non-volatile memory cell architecture M. O'Shea, D. McCarthy, R. Duane, K. McCarthy1, A. Concannon2, A. Mathewson National Microelectronics Research Centre, Cork, Ireland 1Department of Electrical & Electronic Engineering, University College Cork, Ireland 2National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2002.1193188 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Sensitive measurement method for evaluation of high thermal resistance in bipolar transistors N. Nenadovic, L. K. Nanver, H. Schellevis, D. de Mooij1, V. Zieren1, J. W. Slotboom Laboratory of ECTM, DIMES, Delft University of Technnology, Delft, Netherlands 1Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2002.1193175 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | A combined RG/CF large-signal extraction methodology to improve CMOS SPICE-parameter precision S. Mecking, A. Korbel, E. Paparisto1, U. Langmann Ruhr-Universität Bochum, Elektronische Bauelemente, Bochum, Germany 1Infineon Technologies AG Germany, Bochum, Germany DOI: 10.1109/ICMTS.2002.1193181 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Extraction of the coupling coefficients for the top-floating-gate (TFG) flash EEPROM cell D. McCarthy, M. O'Shea, R. Duane, K. Mccarthy1, A. Concannon2, A. Mathewson National Microelectronics Research Centre, Cork, Ireland 1Department of Electrical & Electronic Engineering, University College Cork, Ireland 2National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.2002.1193186 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Useful numerical techniques for compact modeling C. C. McAndrew Motorola, Inc., Tempe, AZ, USA DOI: 10.1109/ICMTS.2002.1193183 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Influence of probing configuration and data set size for bipolar junction capacitance determination D. Macsweeney, K. G. McCarthy1, L. Floyd2, A. Mathewson2, P. Hurley2, J. A. Power3, S. C. Kelly3 Cypress Semiconductor Corporation, Cork, Ireland 1National Microelectronics Research Centre, University College Cork, Ireland 2Department of Electrical and Electronic Engineering, University College Cork, Ireland 3Analog Devices, Inc., Limerick, Ireland DOI: 10.1109/ICMTS.2002.1193184 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | A novel method to characterize the dielectric and interfacial properties of Ba/sub 0.5/Sr/sub 0.5/TiO3 (BST)/Si by microwave measurement Hang-Ting Lue, Tseung-Yuen Tseng, Guo-Wei Huang1 Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 1National Nano Device Laboratories, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2002.1193179 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Extraction of the base and emitter resistances in bipolar transistors using an accurate base resistance model F. Ingvarson, M. Linder1, K. O. Jeppson Solid State Electronics Laboratory, Department of Microelectronics ED, Chalmers University of Technology, Gothenburg, Sweden 1Department of Electronics, Malardalens Hogskola, Vasteras, Sweden DOI: 10.1109/ICMTS.2002.1193174 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Test structures for a MEMS SiOx/metal process M. Hill, C. O'Mahony, P. J. Hughes, B. Lane, A. Mathewson National Microelectronics Research Centre, Cork, Ireland DOI: 10.1109/ICMTS.2002.1193197 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Passive multiplexer test structure for fast and accurate contact and via fail rate evaluation C. Hess, B. E. Stine, L. H. Weiland, T. Mitchell1, M. Karnett2, K. Gardner1 Philips Semiconductor, San Antonio, TX, USA 1Philips Semiconductors, San Antonio, TX, USA 2PDF Solutions Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.2002.1193190 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits C. Hess, B. E. Stine, L. H. Weiland, K. Sawada1 PDF Solutions, Inc.orporated, San Jose, CA, USA 1Toshiba Corporation, Kawasaki, Japan DOI: 10.1109/ICMTS.2002.1193195 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Impact of probe configuration and calibration techniques on quality factor determination of on-wafer inductors for GHz applications R. J. Havens, L. F. Tiemeijer, L. Garnbus1 Philips Research Laboratories, Eindhoven, The Netherlands 1NA DOI: 10.1109/ICMTS.2002.1193164 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Systematic mismatch in diffusion resistors caused by photolithography S. Hausser, S. Majoni, H. Schligtenhorst, G. Kolwe Philips Semiconductors GmbH, Boeblingen, Germany DOI: 10.1109/ICMTS.2002.1193204 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Extraction method for substrate resistance of RF MOSFETs Jeonghu Han, Minkyu Je, Hyungcheol Shin Department of EECS, KAIST, Taejon, South Korea DOI: 10.1109/ICMTS.2002.1193167 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | New spider-webs test structure and characterization methodology for flash memory tunnel oxide quality T. H. Fan, T. C. Lu, S. Pan Special Device /Modeling Dept, Macronix International Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2002.1193185 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | A new test structure and characterization methodology to identify array leakage path in Mask ROM T. Fan, K. Y. Chan, T. C. Lu, S. Pan Special Device / Modeling Dept., Macronix International Co. Ltd., Hsinchu, Taiwan, R.O.C. DOI: 10.1109/ICMTS.2002.1193169 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Measurement of the linewidth of electrical test-structure reference features by automated phase-contrast image analysis B. A. am Ende, M. W. Cresswell, R. A. Allen, T. J. Headley1, W. F. Guthrie2, L. W. Linholm, E. H. Bogardus3, C. E. Murabito2 Semiconductor Electronics Division, National Institute of Standards and Technology, USA 1Sandia National Laboratories, USA 2Semiconductor Electronics Division, National Institute of Standards and Technology 3International SEMATECH, USA DOI: 10.1109/ICMTS.2002.1193161 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Direct measurement of field transistor threshold voltages using inversion layer fed transistors in deep submicron processes J. N. Ellis Zarlink Semiconductor Limited, Plymouth, Devon, UK DOI: 10.1109/ICMTS.2002.1193192 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | A consistent and scalable PSPICE HFET-Model for DC- and S-parameter-simulation S. Ehrich, R. M. Bertenburg1, M. Agethen1, A. Brennemann1, W. Brockerhoff, F. . -J. Tegude Solid-State Electronics Department, Gerhard-Mercator-University Duisburg, Duisburg, Germany 1IPAG, Duisburg, Germany DOI: 10.1109/ICMTS.2002.1193173 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | An assessment of physical and electrical design rule based statistical process monitoring and modeling (PEDR-SPMM): for foundry manufacturing line of multiple-product mixed-run K. Y. . -Y. Doong, S. Hsieh1, S. C. Lin1, L. J. Hung1, R. J. Wang1, Binson Shen1, J. W. Hisa1, J. C. Guo1, I. C. Chen1, K. L. Young1, C. C. . -H. Hsu Microelectronics Laboratory, Semiconductor Technology & Application Research (STAR) Group, Department of Electrical Engineering, National Tsing Hua University, Taiwan 1Taiwan Semiconductor Manufacturing Corporation, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2002.1193171 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Comparison between matching parameters and fluctuations at the wafer level R. Difrenza, P. Llinares1, S. Taupin1, R. Palla1, C. Garnier1, G. Ghibaudo LPCS, ENSERG, Grenoble, France 1Central R&D, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2002.1193203 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | A comparison of extraction techniques for threshold voltage mismatch J. A. Croon, H. P. Tuinhout1, R. Difrenza2, J. Knol3, A. J. Moonen3, S. Decoutere, H. E. Maes, W. Sansen4 IMEC vzw, Leuven, Belgium 1Philips Research, The Netherlands 2LPCS, ENSERG, Grenoble, France 3Philips Semiconductors, Nijmegen, The Netherlands 4K.U. Leuven, ESAT, Leuven, Belgium DOI: 10.1109/ICMTS.2002.1193202 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | High frequency test structures definition for electromagnetic coupling study between two symmetrical inductors. Electrical modelling of the whole coupling between coils C. Clement, B. Van Haaren, D. Gloria Central Research & Development, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2002.1193166 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Characterisation of microfluidic devices D. C. S. Bien, S. J. N. Mitchell, H. S. Gamble School of Electrical and Electronic Engineering, Queen's University, Belfast, UK DOI: 10.1109/ICMTS.2002.1193198 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Triple-junction colour sensor fully compatible with CMOS technology: results of a test chip G. . -F. Dalla Betta, N. Zorzi, P. Bellutti, M. Boscardin, G. Soncini Divisione Microsistemi, ITC IRST, Trento, Italy DOI: 10.1109/ICMTS.2002.1193199 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Test structures for analyzing radiation effects in bipolar technologies H. J. Barnaby, R. D. Schrimpf1, K. F. Galloway1, D. R. Ball1, R. L. Pease2, P. Fouillat3 Electrical & Computer Engineering Department, University of Arizona Tucson, Tucson, AZ, USA 1Electrical Engineering & Computer Science Department, Vanderbilt University, Nashville, TN, USA 2RLP Research, Inc., Albuquerque, NM, USA 3University of Bordeaux 1, Bordeaux, France DOI: 10.1109/ICMTS.2002.1193196 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Verification structures for transmission line pulse measurements R. A. Ashton Agere Systems, Orlando, FL, USA DOI: 10.1109/ICMTS.2002.1193191 HOVER FOR ABSTRACT | PDF Xplore | |
| 2002 | Test structures for referencing electrical linewidth measurements to silicon lattice parameters using HRTEM R. A. Allen, M. W. Cresswell, C. E. Murabito, W. F. Guthrie, L. W. Linholm, C. H. Ellenwood, E. Hal Bogardus1 Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, Maryland, USA 1Intemational SEMATECH, Austin, Texas, USA DOI: 10.1109/ICMTS.2002.1193163 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Mis-match characterization of 1.8 V and 3.3 V devices in 0.18 µm mixed signal CMOS technology Ta-Hsun Yeh, J. C. H. Lin, Shyh-Chyi Wong, H. Huang, J. Y. C. Sun Logic Technology Development Division, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2001.928641 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Test structure and method for capacitance extraction in multi-conductor systems B. Ward, J. Bordelon, S. Prior, B. Tranchina1, Jiann Liu2 TestChip Technologies, Inc., Plano, TX, USA 12600 Technology Drive, Inc., Plano, Texas 2Science-Based Industrial Park, United Microelectronics Corporation, Hsin-Chu City, Taiwan, R.O.C DOI: 10.1109/ICMTS.2001.928660 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Modeling of non-linear polysilicon resistors for analog circuit design R. Virkus, D. Weiser, K. Green, D. Richardson, G. Westphal Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.2001.928643 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Direct extraction of equivalent circuit model parameters for HBTs R. Uscola, M. Tutt DigitalDNA Laboratories, CST, Motorola, Tempe, AZ, USA DOI: 10.1109/ICMTS.2001.928642 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Determining the inductance of a through-substrate via using multiple on-wafer test approaches R. Uscola, M. Tutt DigitalDNA Laboratories CST, Motorola, Tempe, AZ, USA DOI: 10.1109/ICMTS.2001.928653 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Analysis of hot carrier effects in low temperature poly-Si TFTs using device simulator Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura1, Y. Tsuchihashi1 Materials Science, Nara Institute of Science and Technology, Ikoma, Nara, Japan 1LCD Division, Matsushita Elecrric Indusrrial Company Limited, Nomi, Ishikawa, Japan DOI: 10.1109/ICMTS.2001.928671 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | An accurate discrimination method of gate oxide breakdown positions by a new test structure of MOS capacitors H. Uchida, S. Ikeda, N. Hirashita OKI Electric Industry Company Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.2001.928667 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Impact of transistor noise on high precision parametric matching measurements H. P. Tuinhout, J. H. Klootwijk, W. C. Goeke1, L. K. Stauffer1 Philips Research Laboratories, Eindhoven, Netherlands 1Keithley Instruments, Inc., Cleveland, OH, USA DOI: 10.1109/ICMTS.2001.928662 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Mismatch and flicker noise characterization of tantalum nitride thin film resistors for wireless applications H. Thibieroz, P. Shaner1, Z. C. Butler2 Digital DNA Labs RF/IF, Motorola, Austin, TX, USA 1Transportation Group, Motorola, Mesa, AZ, USA 2Department of Electrical Engineering, Southern Methodist University, Dallas, TX, USA DOI: 10.1109/ICMTS.2001.928663 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Statistical modeling techniques: FPV vs. BPV N. Telang, J. M. Higman Semiconductor Products Sector, Motorola, Inc., Austin, TX, USA DOI: 10.1109/ICMTS.2001.928640 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Evaluation of high-performance SOI complementary BiCMOS devices by using test structures Y. Tamaki, T. Iwasaki1, K. Tsuji2, Y. Chida2, T. Tomatsuri, E. Yoshida, J. Kumazawa, C. Kamada Device Development Center, Hitachi and Limited, Ome, Tokyo, Japan 1Hitachi Research Laboratory, Hitachi and Limited, Hitachi, Ibaraki, Japan 2Hitachi VLSI Engineering Corporation Limited, Ome, Tokyo, Japan DOI: 10.1109/ICMTS.2001.928670 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | A new method for analyzing boron penetration and gate depletion using dual-gate PMOSFETs for high performance G-bit DRAM design N. Takaura, R. Nagai1, H. Asakura2, S. Yamada1, S. Kimura Central Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan 1ELPIDA Memory, Inc., Sagamihara, Kanagawa, Japan 2Device Development Center, Hitachi and Limited, Ome, Tokyo, Japan DOI: 10.1109/ICMTS.2001.928657 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Evaluation of the issues involved with test structures for the measurement of sheet resistance and linewidth of copper damascene interconnect S. Smith, A. J. Walton, A. W. S. Ross, G. K. H. Bodammer, J. T. M. Stevenson Department of Electronics and Electrical Engineering, Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.2001.928661 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | A study of measurement system noise for sensitive soft breakdown triggering J. Schmitz, H. P. Tuinhout Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2001.928645 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | A new approach to characterize substrate losses of on-chip inductors L. Schimpf, B. Benna, D. Proetel Texas Instruments Deutschland GmbH, Freising, Germany DOI: 10.1109/ICMTS.2001.928648 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Evaluation of the impact of mechanical stress on CMOS device mismatch U. Schaper, C. Linnenbank, U. Kollmer, H. Mulatz, T. Mensing, R. Schmidt1, R. Tilgner1, A. R. Thewes2 Infineon Technologies AG, Munich, Germany 1Corp. Frontend, Corp. Backend, Munich, Germany 2Corp. Research, Munich, Germany DOI: 10.1109/ICMTS.2001.928627 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Statistical SPICE analysis of a 0.18 µm CMOS digital/analog technology during process development N. S. Rankin, Chun Ng1, Leang Sern Ee1, F. Boyland1, E. Quek1, Leung Ying Keung1, A. J. Walton, M. Redford1 Scottish Microelectronics Centre, University of Edinburgh, Edinburgh, UK 1Chartered Semiconductor Manufacturing Private Limited, Singapore DOI: 10.1109/ICMTS.2001.928631 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Effects of electrical stress on the frequency performance of 0.18 µm technology NMOSFETs S. Naseh, M. J. Deen, O. Marinov Electrical and Computer Engineering Department, McMaster University, Hamilton, ONT, Canada DOI: 10.1109/ICMTS.2001.928649 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Limitations of the two-frequency capacitance measurement technique applied to ultra-thin SiO2 gate oxides A. Nara, N. Yasuda, H. Satake, A. Toriumi1 Advanced LSI Technology Laboratory Corporate Research & Development Center, Toshiba Corporation, Yokohama, Japan 1University of Tokyo, Japan DOI: 10.1109/ICMTS.2001.928637 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | New length scaling of current gain factor and characterization method for pocket implanted MOSFET's M. Minondo, G. Gouget, A. Juge Central R&D, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.2001.928673 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Oxide thickness dependence of nitridation effects on TDDB characteristics M. K. Mazumder, A. Teramoto, J. Komori, Y. Mashiko ULSI Laboratory, Musubishi Electric Corporation, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.2001.928646 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Comparison of interface trap density measured by capacitance/subthreshold/charge-pumping methods for n-MOSFETs with Si-implanted gate-SiO2 T. Matsuda, R. Takezawa, K. Arakawa, M. Yasuda, T. Ohzone, E. Kameda1 Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan 1Department of Electrical Engineering, Toyama National College of Maritime Technology, Toyama, Japan DOI: 10.1109/ICMTS.2001.928639 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | A novel approach to the estimation of confidence limits for BJT model sets using a bootstrap technique D. MacSweeney, K. G. McCarthy1, L. Floyd, M. Riordan, L. Sattler, A. Mathewson, J. A. Power2, S. C. Kelly2 National Microelectronics Research Centre, University College Cork, Ireland 1Department of Electrical and Electronic Engineering, University College Cork, Ireland 2Analog Devices, Inc., Limerick, Ireland DOI: 10.1109/ICMTS.2001.928636 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | A new test structure for parasitic resistance extraction in bipolar transistors M. Linder, F. Ingvarson1, K. O. Jeppson1, Shi-Li Zhang, J. V. Grahn, M. Ostling Device Technology Laboratory, Department of Electronics, Royal Institute of Technology, Kista, Sweden 1Solid State Electronics Laboratory Department of Microelectronics ED, Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS.2001.928632 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Efficient parameter extraction techniques for a new surface-potential-based MOS model for RF applications Wenzhi Liang, R. Van Langevelde1, K. G. McCarthy2, A. Mathewson National Microelectronics Research Centre, Cork, Ireland 1Philips Research Laboratories, Eindhoven, Netherlands 2Department of Electrical and Electronics Engineering, University College Cork, Ireland DOI: 10.1109/ICMTS.2001.928652 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | An improved transmission line pulsing (TLP) setup for electrostatic discharge (ESD) testing in semiconductor devices and ICs J. C. Lee, R. Young1, J. J. Liou2, G. D. Croft1, J. C. Bernier3 RF Analog SiGe BiCMOS Device Modeling Group, IBM, Burlington, VT, USA 1Technology Development Department, Intersil Corporation, Melbourne, FL, USA 2School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL, USA 3Reliability Engineering Department, Intersil Corporation, Melbourne, FL, USA DOI: 10.1109/ICMTS.2001.928668 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | High frequency MOS transistor matching measurements for the determination of mixer port crosstalk S. Laursen University of Aalborg, Aalborg, Denmark DOI: 10.1109/ICMTS.2001.928629 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | FeRAM retention analysis method based on memory cell read signal voltage measurement H. Koike, K. Amanuma1, T. Miwa, J. Yamada, H. Toyoshima2 Silicon Systems Research Laboratories, System Devices and Fundamental Research, NEC Corporation Limited, Sagamihara, Kanagawa, Japan 1Second System LSI Division, NEC Electron Devices, Sagamihara, Kanagawa, Japan 2ULSI Device Development Division, NEC Electron Devices, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.2001.928634 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Resistor matching characterization for process development using D/A converter S. Katakam, B. Tranchina, J. Bordelon, A. Ramaswamy1, Wooyoung Choi2, S. Chu3 TestChip Technologies, Inc., Dallas, USA 1Sun Microsystems, Inc., USA 2University of Minnesota, USA 3Chartered Semiconductor, Inc., Singapore DOI: 10.1109/ICMTS.2001.928665 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Contact resistance measurement of a 130-nm-diameter poly-Si plug on a lightly doped single diffusion region in giga-bit DRAMs N. Kasai, H. Koga, Y. Takaishi ULSI Device Development Division, NEC Electron Devices, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.2001.928658 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | C-V extraction method for gate fringe capacitance and gate to source-drain overlap length of LDD MOSFET Jae-Rok Kahng, Jang-Won Moon, Jin-Hyoung Kim Memory R&D Division, Hyundai Electronics Industries Company Limited, Incheon, Gyeonggi, South Korea DOI: 10.1109/ICMTS.2001.928638 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Process monitoring and defect characterization of single photon avalanche diodes J. C. Jackson, A. P. Morrison1, P. Hurley, W. R. Harrell2, D. Damjanovic2, B. Lane, A. Mathewson National Microelectronics Research Centre, University College Cork, Ireland 1Department of Electrical and Electronic Engineering, University College Cork, Ireland 2Department of Electrical and Computer Engineering, Clemson University, South Carolina, U.S.A. DOI: 10.1109/ICMTS.2001.928656 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | A procedure for characterizing the BJT base resistance and Early voltages utilizing a dual base transistor test structure F. Ingvarson, M. Linder1, K. O. Jeppson, Shi-Li Zhang1, J. V. Grahn1, M. Ostling1 Solid State Electronics Laboratory, Department of Microelectronics ED, Chalmers University of Technology, Gothenburg, Sweden 1DeviceTechnology Laboratory, Department of Electronics, Royal Institute of Technology, Kista, Sweden DOI: 10.1109/ICMTS.2001.928633 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Effective-channel-length extraction for double-diffused MOSFETs S. Ichikawa, Y. Eshima, K. Terada, T. Matsuki1 Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan 1ULSI Device Development Division, NEC Corporation Limited, Japan DOI: 10.1109/ICMTS.2001.928644 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | A new Leff extraction approach for devices with pocket implants T. S. Hsieh, Y. W. Chang, W. J. Tsai, T. C. Lu Special Device & Modeling Department, Macronix International Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2001.928630 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Use of electrical test structures to characterize trench profiles etched on SOI wafers N. Guillaume, J. Kiihamaki1, J. Karttunen1, H. Kattelus1 Guest Researcher at NIST, George Washington University, Washington D.C., DC, USA 1VTT Electronics, Finland DOI: 10.1109/ICMTS.2001.928655 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | | A new test structure to measure precise location of hot-carrier-induced photoemission peak from gate center of subquarter-micron n-MOSFETs M. Funada, T. Matsuda, T. Ohzone, S. Odanaka1, K. Yamashita2, N. Koike2, K. Tatsumma3 Department of Electronics and Informatics, Toyama Prefectural University, Imizu-gun, Toyama, Japan 1Cybermedia Center, Osaka University, Toyonaka, Osaka, Japan 2ULSI Process Technology Development Center, Matsushita Electronics Corp., Minami-ku, Kyoto, Japan 3NA DOI: 10.1109/ICMTS.2001.928666 HOVER FOR ABSTRACT | PDF Xplore |
| 2001 | A new method for measuring the coupling coefficient of a split-gate flash EEPROM without an additional test structure H. Fujiwara, M. Arimoto, T. Kaida, S. Sudo, K. Kurooka, H. Nagasawa, T. Hiroshima, K. Mameno Microelectronics Research Center, SANYO Electric Company Limited, Gifu, Japan DOI: 10.1109/ICMTS.2001.928635 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Effect of substrate voltage and oxide thickness on NMOSFET matching characteristics for a 0.18 µm CMOS technology R. Difrenza, P. Llinares, E. Granger, H. Brut, G. Ghibaudo1 STMicroelectronics, Crolles, France 1LPCS-ENSERG, Grenoble, France DOI: 10.1109/ICMTS.2001.928628 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | A simple characterization method for MOS transistor matching in deep submicron technologies J. A. Croon, M. Rosmeulen, S. Decoutere, W. Sansen1, H. E. Maes IMEC vzw, Leuven, Belgium 1K.U. Leuven, ESAT, Leuven, Belgium DOI: 10.1109/ICMTS.2001.928664 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Test chip for electrical linewidth of copper-interconnect features and related parameters M. W. Cresswell, N. Arora1, R. A. Allen, C. E. Murabito, C. A. Richter, A. Gupta2, L. W. Linholm, D. Pachura3, P. Bendix3 Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Simplex Solution, Inc., Sunnyvale, CA, USA 2Chartered Semiconductor Manufacturing Private Limited, Milpitas, CA, USA 3LSI Logic, Inc., Milpitas, CA, USA DOI: 10.1109/ICMTS.2001.928659 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Die cracking evaluation and improvement in ULSI plastic package Kuo-Yu Chou, Ming-Jer Chen, Chiu-Cheng Lin1, Yen-Shien Su1, Chin-Shan Hou1, Tong-Cherng Ong1 Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan 1Technology Reliability Physics Department R&D, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2001.928669 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Extraction of the induced gate noise, channel thermal noise and their correlation in sub-micron MOSFETs from RF noise measurements Chih-Hung Chen, M. J. Deen, M. Matloubian1, Yuhua Cheng1 Department of Electrical and Computer Engineering, McMaster University, Hamilton, ONT, Canada 1Conexant Systems, Inc., Newport Beach, CA, USA DOI: 10.1109/ICMTS.2001.928651 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | A general procedure for high-frequency noise parameter de-embedding of MOSFETs by taking the capacitive effects of metal interconnections into account Chih-Hung Chen, M. J. Deen Department of Electrical and Computer Engineering, McMaster University, Hamilton, ONT, Canada DOI: 10.1109/ICMTS.2001.928647 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | A new robust on-wafer 1/f noise measurement and characterization system A. Blaum, O. Pilloud, G. Scalea, J. Victory, F. Sischka1 Motorola, Inc., Geneva, Switzerland 1Agilent Technologies, Inc., Boblingen, Germany DOI: 10.1109/ICMTS.2001.928650 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Test chips for evaluating strong phase shift lithography R. A. Ashton, B. C. Kane1, J. W. Blatchford, D. M. Shuttleworth Agere Systems, Orlando, FL, USA 1Multilink Technology, Somerset, NJ, USA DOI: 10.1109/ICMTS.2001.928654 HOVER FOR ABSTRACT | PDF Xplore | |
| 2001 | Channel width and length dependent flicker noise characterization for n-MOSFETs H. Aoki, M. Shimasue Design Technology Group, Knowledge Seervice, Agilent Technologies International Japan Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.2001.928672 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Reliability evaluation method of low temperature poly-silicon TFTs using dynamic stress Y. Uraoka, T. Hatayama, T. Fuyuki Graduute School of Materials Science, Nara Institute of Science and Technology, Ikoma, Nara, Japan DOI: 10.1109/ICMTS.2000.844424 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | | Characterisation of systematic MOSFET transconductance mismatch H. Tuinhout Philips Res., Eindhoven, Netherlands DOI: 10.1109/ICMTS.2000.844419 HOVER FOR ABSTRACT | PDF Xplore |
| 2000 | Extraction of effective LDMOSFET channel length and its application to the modeling K. Tsuji, K. Terada, M. Minami, K. Tanaka1 Faculty of Information Sciences, Hiroshima City University, Hiroshima, Japan 1Semiconductor Division, NEC Corporation Limited, Kawasaki, Japan DOI: 10.1109/ICMTS.2000.844409 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Characterization of sub-micron MOS transistors, modified using a focused ion beam system D. W. Travis, C. M. Reeves, A. J. Walton, A. M. Gundlach, J. T. M. Stevenson1 Department of Electronics and Electrical Engineering, University of Edinburgh, Edinburgh, UK 1NA DOI: 10.1109/ICMTS.2000.844402 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | On the matching behavior of MOSFET small signal parameters R. Thewes, C. Linnenbank1, U. Kollmer1, S. Burges2, M. DiLeo, M. Clincy, U. Schaper1, R. Brederlow3, R. Seibert4, W. Weber Infineon Technohgies, Corporate Research and Development, Munich, Germany 1CPE SIM, Infineon Technologies 2PS TM 2, Infineon Technologies 3NA 4CPD DAT, Infineon Technologies DOI: 10.1109/ICMTS.2000.844420 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Electromigration test structure designed to identify via failure modes T. S. Sriram Compaq Computer Corporation, Shrewsbury, MA, USA DOI: 10.1109/ICMTS.2000.844423 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Use of test structures for Cu interconnect process development and yield enhancement A. Skumanich, Man-Ping Cai, J. Educato1, D. Yost Applied Materials, Inc., Santa Clara, CA, USA 1NA DOI: 10.1109/ICMTS.2000.844406 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | | A novel approach for precise characterization of long distance mismatch of CMOS-devices U. Schaper, C. Linnenbank, R. Thewes1 Infineon Technologies AG, Corporate Frontends CFE SIM 1Corporate Research CPR 7, Munich, Germany DOI: 10.1109/ICMTS.2000.844422 HOVER FOR ABSTRACT | PDF Xplore |
| 2000 | SPICE sensitivity analysis of a bipolar test structure during process development N. Rankin, A. J. Walton, J. McGinty1, M. Fallon1 Department of Electrical and Electrical Engineering King's Buildings, University of Edinburgh, Edinburgh, UK 1Larkfield Industrial Estate, National Semiconductor (UK) Limited, Greenock, UK DOI: 10.1109/ICMTS.2000.844429 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Select transistor modulated cell array structure test for EEPROM reliability F. Pio, E. Gomiero Ceiltral R&D, STMicroelectronics, Agrate-Brianza, Italy DOI: 10.1109/ICMTS.2000.844434 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | High-spatial-frequency MOS transistor gate length variations in SRAM circuits X. Ouyang, T. Deeter1, C. N. Berglund, R. F. W. Pease, M. A. McCord1 Center for Integrated Systems, University of Stanford, Stanford, CA, USA 1NA DOI: 10.1109/ICMTS.2000.844400 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Fabrication of twin transistors using sidewall masks for evaluating threshold voltage fluctuation M. Okuno, T. Aoyama, S. Nakamura, R. Sugino, H. Arimoto Fujitsu Laboratories Limited, Atsugi, Japan DOI: 10.1109/ICMTS.2000.844401 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | A study on hot-carrier-induced photoemission in n-MOSFETs under dynamic operation T. Ohzone, M. Yuzaki, T. Matsuda, E. Kameda Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan DOI: 10.1109/ICMTS.2000.844408 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | A new extraction method of retention time from the leakage current in 0.23 µm DRAM memory cell Choong-Mo Nam, Sung-Kye Park, Sang-Ho Lee, Jai-Bum Suh, Gyu-Han Yoon, Sung-Ho Jang Refresh Development Team, Memory R& D Division, Hyundai MicroElectronics Company, Limited, Kyoungki, South Korea DOI: 10.1109/ICMTS.2000.844414 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | New method for parameter extraction in deep submicrometer MOSFETs C. Mourrain, B. Cretu1, G. Ghibaudo2, P. Cottin France Telecom CNET Grenoble, Meylan, France 1Laboratory Physiquc des Coinposants à Semiconductcurs, ENSERG, Grenoble, France 2NA DOI: 10.1109/ICMTS.2000.844428 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Physically-based effective width modeling of MOSFETs and diffused resistors C. C. McAndrew, S. Sekine1, A. Cassagnes2, Zhicheng Wu2 Motorola Inc., Tempe, AZ, USA 1NA 2Motorola, Inc., Tempe, AZ, USA DOI: 10.1109/ICMTS.2000.844426 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | An electrical technique for determining MOSFET gate length reduction due to process micro-loading effects in advanced CMOS technology Chunbo Liu, J. Ma, Jeong Choi Intcgroted Dcvice Iczluiulogy, Inc., Santa Clara, CA, USA DOI: 10.1109/ICMTS.2000.844417 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Characterisation of aluminium passivation for TMAH based anisotropic etching for MEMS applications Knut Lian, S. Smith1, N. Rankin1, A. J. Walton2, A. Gundlach1, T. Stevenson1 SensoNor asa, Horten, Norway 1Department of Electronics and Electrical Engineering, University of Edinburgh, Edinburgh, UK 2NA DOI: 10.1109/ICMTS.2000.844433 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Test structure for universal estimation of MOSFET substrate effects at gigahertz frequencies T. E. Kolding RF Integrated Systems & Circuits RKC group, University of Aalborg, Denmark DOI: 10.1109/ICMTS.2000.844415 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Ground-shielded measuring technique for accurate on-wafer characterization of RF CMOS devices T. E. Kolding, O. K. Jensen1, T. Larsen RF Integratecl Systems & Circuits RISC Group, University of Aalborg, Denmark 1NA DOI: 10.1109/ICMTS.2000.844439 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Thermal channel noise of quarter and sub-quarter micron NMOSFET's G. Knoblinger, P. Klein1, U. Baumann2 Infineon Technol. AG, Germany 1INFINCON TECHNOIOGIES AG, Germany 2IMMS DMENAU Germany, MUNICH, Germany DOI: 10.1109/ICMTS.2000.844412 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Characterization of trench isolation for BiCMOS technologies J. H. Klootwijk, G. C. Muda, D. Terpstra Philips Research Laboratory Eindhoven, Eindhoven, Netherlands DOI: 10.1109/ICMTS.2000.844431 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | A new mobility model for circuit simulation in pocket implanted MOSFET's P. Klein, F. Schuler1 Infineon Technologies, Munich, Germany 1Intineon Technologies AG, Munich, Germany DOI: 10.1109/ICMTS.2000.844413 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | A differential floating gate capacitance mismatch measurement technique J. Hunter, P. Gudem1, S. Winters Silicon Technology Scrviccs, Cadence Design Systems, Inc., San Diego, CA, USA 1NA DOI: 10.1109/ICMTS.2000.844421 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Optimization of low-k dielectric (fluorinated SiO2) process and evaluation of yield impact by using BEOL test structures Sunnys Hsieh, K. Y. . -Y. Doong1, Yen-Hsuan Ho2, Sheng-Che Lin2, Binson Shen2, Sing-Mo Tseng2, Yeu-Haw Yang2, C. C. . -H. Hsu1 Worldwide Semicond. Manuf. Corp., Hsinchu, Taiwan 1Microelectronics Laboratory, Semiconductor Teclinology & Application Research Group, Department of Electrical Engineering, National Tsing Hua University, China 2Worldwide Semiconductor Manufacturing Corporation, Hsinchu, Taiwan DOI: 10.1109/ICMTS.2000.844432 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Fast extraction of killer defect density and size distribution using a single layer short flow NEST structure C. Hess, D. Stashower1, B. E. Stine1, G. Verna2, L. H. Weiland1, K. Miyamoto3, K. Inoue3 PDF Solutions Inc., San Jose, CA, USA 1PDF Solutions, Inc.orporated, San Jose, CA, USA 2NA 3Toshiba Corporation, Yokohama, Japan DOI: 10.1109/ICMTS.2000.844405 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Characterization and modeling of LDMOS transistors on a 0.6 µm CMOS technology E. C. Griffith, J. A. Power, S. C. Kelly, P. Elebert1, S. Whiston, D. Bain, M. O'Neill Analog Devices, Raheen Industrial Estate, Limerick, Ireland 1NA DOI: 10.1109/ICMTS.2000.844427 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Thermo-mechanical structures for the optimisation of silicon micromachined gas sensors A. Gotz, I. Gracia1, C. Cane2, M. Lozano2, E. Lora-Tamayo3 Centro Nacional de Microelectron., Bellaterra, Spain 1Centro National de Microelectrónica IMB-CSIC, Bellaterra, Spain 2Consejo Superior de Investigaciones Cientificas, Madrid, Madrid, ES 3NA DOI: 10.1109/ICMTS.2000.844411 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Embedded compact test structure with a comparator for rapid device characteristic measurement J. Goto, S. Kuwabara1, T. Tsujide2 Device Analysis Technology Labs., NEC Corporation Limited, Kawasaki, Japan 1Nihon Denki Kabushiki Kaisha, Minato-ku, Tokyo, JP 2NA DOI: 10.1109/ICMTS.2000.844430 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | A new extraction method of high frequency noise parameters in the temperature range -55/150 deg. for SiGe HBT in BiCMOS process D. Gloria, S. Gellida, G. Morin STMicroelectronics Central Research and Development, Crolles, France DOI: 10.1109/ICMTS.2000.844436 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Comparing high-frequency de-embedding strategies: immittance correction and in-situ calibration R. Gillon, W. Van De Sype1, D. Vanhoenaker2, L. Martens1 Alcatel Microelectronics, Oudenaarde, Belgium 1INTEC, University of Ghent, Ghent, Belgium 2NA DOI: 10.1109/ICMTS.2000.1193989 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | A new test structure to measure metal linewidths using minimum real estate M. Fallen, D. McAlpine1 Analog Process Technol. Dev., Nat. Semicond. UK Ltd., Greenock, UK 1Analog Process Technology Development, National Semiconductor (UK) Limited, Greenock, UK DOI: 10.1109/ICMTS.2000.844394 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Rapid evaluation of the root causes of BJT mismatch P. G. Drennan, C. C. McAndrew1, J. Bates1, D. Schroder2 Motorola Inc., Tempe, AZ, USA 1Motorola, Inc., Tempe, AZ, USA 2Arizona State University, Tempe, AZ, USA DOI: 10.1109/ICMTS.2000.844418 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Addressable failure site test structures (AFS-TS) for process development and optimization K. Y. . -Y. Doong, Sunnys Hsieh1, Sheng-Che Lin1, Binson Shen1, Wang Chien-Jung2, Yen-Hen Ho1, Jye-Yen Cheng1, Yeu-Haw Yang1, K. Miyamoto3, C. C. . -H. Hsu2 Worldwide Semicond. Manuf. Corp., Shinchu, Taiwan 1Worldwide Semiconductor Manufacturing Corporation, Hsinchu, Taiwan 2Microelectronics Laboratory, Semiconductor Technology and Application Research Group, China 3MOS Process Integration technology Dcpartnient, Micro & Custom LSI Division, Toshiba Corporation, Yokohama, Japan DOI: 10.1109/ICMTS.2000.844404 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Characterization of electrical linewidth test structures patterned in [100] silicon-on-insulator for use as CD standards M. W. Cresswell, R. A. Allen, R. N. Ghoshtagore1, N. M. P. Guillaume2, P. J. Shea3, S. C. Everist3, L. W. Linholm Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1NA 2Guest Kesearcher at NIST from George, Washington University, WA, USA 3Sandia National Laboratories, Albuquerque, NM, USA DOI: 10.1109/ICMTS.2000.844393 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Influence of input voltage swing on 0.18 µm NMOS aging estimated by self-stressing testers S. Chetlur, J. Zaneski, L. Mullin, A. Oates1, R. A. Ashton, H. Chew, J. Zhou Lucent Thechnology, Bell Laboratories, Orlando, FL, USA 1NA DOI: 10.1109/ICMTS.2000.844425 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Extraction of the channel thermal noise in MOSFETs Chih-Hung Chen, M. J. Deen, M. Matloubian1, Yuhua Cheng1 Electrical and Computer Engineering, McMaster University, Hamilton, ONT, Canada 1Conexant Systems, Inc., Newport Beach, CA, USA DOI: 10.1109/ICMTS.2000.844403 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Comparison between S-parameter measurements and 2D electromagnetic simulations for microstrip transmission lines on BiCMOS process J. F. Carpentier, S. Gellida1, D. Gloria, G. Morin, H. Jaouen1 Centrai R&D, STMicroelectronics, Crolles, France 1NA DOI: 10.1109/ICMTS.2000.844437 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | A microelectronic test structure for signal integrity characterization in deep submicron technology F. Caignet, S. D. . -B. Dhia1, E. Sicard2 Complexe Sci. de Rangueil, Inst. Nat. des Sci. Appliquees, Toulouse, France 1NA 2Complexe Scientifique de rangueil, INSA-Toulouse, Toulouse, France DOI: 10.1109/ICMTS.2000.844407 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Gate-length dependence of bulk generation lifetime and surface generation velocity measurement in high-resistivity silicon using gated diodes G. . -F. Dalla Betta, G. Verzellesi1, T. Boscardin2, G. U. Pignatel3, L. Bosisio4, G. Soncini2 Divisione Microsistemi, ITC IRST, Italy 1Dipartimento di Scienze dell Ingegneria, Universita di Modena e Reggio Emilia, Italy 2NA 3Dipartmento di Ingegneria dei Materiali, Universita di Trento, Italy 4Dipartimento di Fisica, Universita di Trieste and INFN sezione di Trieste, Italy DOI: 10.1109/ICMTS.2000.844410 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Fowler Nordheim induced light emission from MOS diodes P. Bellutti, G. . -F. Dalla Betta, N. Zorzi, R. Versari1, A. Pieracci2, B. Ricco1, M. Manfredi3, G. Soncini4 ItC IRST Divisone Micrositcmi, Italy 1Dipartimento fi Elottronica Iuformatica C Sistomisttica, Università di Bologna, Bologna, Italy 2NA 3Dipartimento di Fisica e INFM, Università di Parma, Parma, Italy 4Dipartimento di Engegneria dei Materiali, Università di Trento, Trento, Italy DOI: 10.1109/ICMTS.2000.844435 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | On-chip voltage noise monitor for measuring voltage bounce in power supply lines using a digital tester H. Aoki, M. Ikeda, K. Asada1 Department of Electronic Engineering,VLSI Design and Edocntion Center, University of Tokyo, Tokyo, Japan 1NA DOI: 10.1109/ICMTS.2000.844416 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | A novel method for fabricating CD reference materials with 100 nm linewidths R. A. Allen, L. W. Linholm, M. W. Cresswell1, C. H. Ellenwood2 Semiconductor Elcctroriics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1National Institute of Standards and Technology, Gaithersburg, MD, US 2NA DOI: 10.1109/ICMTS.2000.844396 HOVER FOR ABSTRACT | PDF Xplore | |
| 2000 | Characterization of mask alignment offsets using null wire segment holograms and a progressive offset technique S. A. AbuGhazaleh, P. Christie1, S. Smith2, A. M. Gundlach2, J. T. M. Stevenson3, A. J. Walton2 Dept. of Electr. & Comput. Eng., Delaware Univ., Newark, DE, USA 1Department or Electrical and Computcr Engineering, University of Delaware, Newark, DE, USA 2Department of Electronics and Electrical Engineering, University of Edinburgh, Edinburgh, UK 3NA DOI: 10.1109/ICMTS.2000.844395 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | CMOS 1/f noise modelling and extraction of BSIM3 parameters using a new extraction procedure J. C. Vildeuil, M. Valenza, D. Rigaud Centre dElectronique et de Micro-optoélectronique de Montpellier, Universite Montpellier II, Montpellier, France DOI: 10.1109/ICMTS.1999.766244 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Extraction of the trap density at the gate periphery using the gated diode array for giga-bit DRAMs H. Suzuki, M. Kojima, Y. Nara Fujitsu Laboratories Limited, Atsugi, Japan DOI: 10.1109/ICMTS.1999.766228 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Investigation of optical proximity correction (OPC) and non-uniformities on the performance of resistivity and linewidth measurements S. Smith, A. J. Walton, M. Fallon1 Department of Electronics and Electrical Engineering, University of Edinburgh, Edinburgh, UK 1National Semiconductors (Israel) Limited, Greenock, UK DOI: 10.1109/ICMTS.1999.766236 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Analysis of current flow in mono-crystalline electrical linewidth structures S. Smith, I. A. B. Lindsay, A. J. Walton, M. W. Cresswell, L. W. Linholm, R. A. Allen, M. Fallon, A. M. Gundlach Department of Electronics and Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1999.766207 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Identification of plasma induced damage conditions in VLSI designs P. Simon, W. Maly1 Philips Semiconductors, Nijmegen, Netherlands 1Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA DOI: 10.1109/ICMTS.1999.766206 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Geometry modeling method for narrow/short and narrow MOSFETs S. Sekine, M. Sugiyama, N. Saito Computational Technologies Laboratory, Motorola Japan Limited, Sendai, Miyagi, Japan DOI: 10.1109/ICMTS.1999.766229 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | A new test structure for direct extraction of SPICE model parameters for double polysilicon bipolar transistors M. Sanden, Shi-Li Zhang, J. V. Grahn, M. Ostling Department of Electronics, Kungliga Tekniska Högskolan, Kista, Sweden DOI: 10.1109/ICMTS.1999.766211 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | An investigation of on-chip spiral inductors on a 0.6 µm BiCMOS technology for RF applications J. A. Power, S. C. Kelly, E. C. Griffith, M. O'Neill Analog Devices, Raheen Industrial Estate, Limerick, Ireland DOI: 10.1109/ICMTS.1999.766209 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Test structure design for a fast and simple evaluation of carrier mobilities in highly injected regions G. V. Persiano Facoltà di Ingegneria, Università del Sannio, Benevento, Italy DOI: 10.1109/ICMTS.1999.766224 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | | A thermal van der Pauw test structure O. Paul, L. Plattner1, H. Baltes1 Institute for Microsystem Technology, University of Freiburg, Freiburg im Breisgau, Germany 1Physical Electronics Laboratory, ETH Hoenggerberg HPT, Zurich, Switzerland DOI: 10.1109/ICMTS.1999.766216 HOVER FOR ABSTRACT | PDF Xplore |
| 1999 | A capacitance-voltage measurement method for DMOS transistor channel length extraction J. Olsson, R. Valtonen, U. Heinle, L. Vestling, A. Soderbarg, H. Norde The Ångström Laboratory, Solid-state Electronics, University of Uppsala, Uppsala, Sweden DOI: 10.1109/ICMTS.1999.766231 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Identification of MOS oxide defect location with a spatial resolution less than 0.1 µm using photoemission microscope T. Ohzone, M. Yuzaki, T. Matsuda, E. Kameda1 Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan 1Department of Electrical Engineering, Toyama National College of Maritime Technology, Toyama, Japan DOI: 10.1109/ICMTS.1999.766222 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | The fabrication of electrical linewidth structures capable of TEM measurement using standard <100> wafers C. G. Munro, A. M. Gundlach, J. T. M. Stevenson, D. W. Travis, S. Smith, N. S. Rankin, A. J. Walton Edinburgh Microfabrication Facility Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1999.766208 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Test structure for direct extraction of capacitance matrix in VLSI T. Mido, H. Ito, K. Asada Department of Electronic Engineering, (VLSI Design and Education Center (VDEC)), University of Tokyo, Bunkyo, Tokyo, Japan DOI: 10.1109/ICMTS.1999.766243 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Evolution of the Si-SiO2 interface trap characteristics with Fowler-Nordheim injection Y. Maneglia, D. Bauza UMR CNRS 5531, LPCS, ENSERG/INPG, Grenoble, France DOI: 10.1109/ICMTS.1999.766227 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Inclusion of substrate effects in the flyback method for BJT resistance characterisation D. MacSweeney, K. McCarthy, A. Mathewson, J. A. Power1, S. C. Kelly1 National Microelectronics Research Centre, University College Cork, Ireland 1Analog Devices, Inc., Limerick, Ireland DOI: 10.1109/ICMTS.1999.766242 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | A new procedure for extraction of series resistances for bipolar transistors from DC measurements M. Linder, F. Ingvarson1, K. O. Jeppson1, J. V. Grahn, S. . -L. Zhang, M. Ostling Department of Electronics, Device Technology Laboratory, Royal Institute of Technology, Kista, Sweden 1Department of Microelectronics ED, Solid State Electronics Laboratory, Chalmers University of Technology, Gothenburg, Sweden DOI: 10.1109/ICMTS.1999.766233 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | A new extraction method for BSIM3v3 model parameters of RF silicon MOSFETs Seonghearn Lee, Hyun Kyu Yu1 Department of Electronic Engineering, Hankuk University of Foreign Studies, Yongin si, South Korea 1Electronics and Telecommunications Research Institute, Micro-Electronics Technology Laboratory, Taejon, South Korea DOI: 10.1109/ICMTS.1999.766223 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Measurement of VT and Leff using MOSFET gate-substrate capacitance M. M. Lau, C. Y. T. Chiang1, Y. T. Yeow, Z. Q. Yao2 Department of Computer Science and Electrical Engineering, University of Queensland, Brisbane, QLD, Australia 1NA 2Quality Semiconductors Australia, Sydney, Australia DOI: 10.1109/ICMTS.1999.766234 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Simple technique for the measurement of thermal time constants of microbolometer structures P. Lambkin, N. Folan1, B. Lane National Microelectronics Research Centre, Cork, Ireland 1NA DOI: 10.1109/ICMTS.1999.766239 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | On-wafer calibration techniques for giga-hertz CMOS measurements T. E. Kolding RF Integrated Systems & Circuits (RISC) group, University of Aalborg, Aalborg, Denmark DOI: 10.1109/ICMTS.1999.766225 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Automated generation of SPICE characterization test masks and test databases L. Kasel, C. C. McAndrew, P. Drennan, W. F. Davis, R. Ida Motorola, Inc., Tempe, USA DOI: 10.1109/ICMTS.1999.766219 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Test structure for measurement of ion stopping power H. Kanata, Y. Tosaka, H. Ehara, S. Satoh Fujitsu Laboratories Limited, Atsugi, Japan DOI: 10.1109/ICMTS.1999.766240 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Direct parameter extraction techniques for a new poly-Si TFT model B. Iniguez, Z. Xu, T. Fjeldly, M. S. Shur Electrical, Computer and System Engineering Department, Rensselaer Polytechnic Institute, Troy, NY, USA DOI: 10.1109/ICMTS.1999.766247 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Stress and recovery transients in bipolar transistors and MOS structures F. Ingvarson, L. . -A. Ragnarsson, P. Lundgren, K. O. Jeppson Department of Microelectronics, Solid State Electronics Laboratory, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1999.766238 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Implementation of statistical characterisation and design techniques for an industrial 0.5 µm CMOS technology S. Healy, E. Horan, K. McCarthy, A. Mathewson, Zhenqiu Ning1, E. Rombouts, W. Vanderbauwhede, M. Tack National Microelectronics Research Centre, Cork, Ireland 1Alcatel Microelectronics, Oudenaarde, Belgium DOI: 10.1109/ICMTS.1999.766249 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Comparison of sheet-resistance measurements obtained by standard and small-area four-point probing N. M. P. Guillaume, M. W. Cresswell1, R. A. Allen1, S. Everist2, L. W. Linholm1 École Nationale Supérieure d'Electrotechnique, Electronique, Informatique, Toulouse, France 1Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 2Sandia National Laboratories DOI: 10.1109/ICMTS.1999.766217 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | A statistical noise-tolerance analysis and test structure for logic families M. Graziano, G. Masera, G. Piccinini, M. Ruo Roch, M. Zamboni Dip. Elettronica, Politecnico di Torino, Torino, Italy DOI: 10.1109/ICMTS.1999.766218 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Substrate resistance effect on the Fmax parameter of isolated BJT in BiCMOS process D. Gloria, A. Perrotin, J. L. Carbonero, G. Morin Central R&D, STMicroelectronics, Crolles, France DOI: 10.1109/ICMTS.1999.766210 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Improved method for the oxide thickness extraction in MOS structures with ultra-thin gate dielectrics G. Ghibaudo, S. Bruyere1, T. Devoivre2, B. DeSalvo3, E. Vincent2 Phelma, Grenoble, Rhône-Alpes, FR 1NA 2STMicroelectronics, Crolles, France 3URA CNRS ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1999.766226 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Evaluation of test methods and associated test structures for interconnect reliability control S. Foley, J. Molyneaux1, A. Mathewson National Microelectronics Research Centre, University College-Lee Maltings, Cork, Ireland 1Analog Devices, Raheen Industrial Estate, Limerick, Ireland DOI: 10.1109/ICMTS.1999.766237 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | The impact of noise parameter de-embedding on the high-frequency noise modeling of MOSFETs M. J. Deen, Chih-Hung Chen School of Engineering Science, Simon Fraser University, Burnaby, BC, Canada DOI: 10.1109/ICMTS.1999.766212 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | A compact SOI model for fully-depleted and partially-depleted 0.25 µm SIMOX devices Ping Chen, Zhihong Liu, Chune-Sin Yeh, Gang Zhang, K. Nishimura1, M. Shimaya1, T. Komatsu2 BTA Technologies, Inc., Santa Clara, CA, USA 1NTT Systems Electronics Laboratories, Atsugi, Japan 2NTT Advanced Technology Corporation, Musashino, Japan DOI: 10.1109/ICMTS.1999.766248 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Contribution to the characterization of the hump effect in MOSFET submicronic technologies H. Brut, R. M. D. A. Velghe1 Crolles Centre Commun, Central R&D-Modeling and Characteaizatioa, STMicroelectronics, Crolles, France 1Crolles Centre Commun, Central R&D-Modeling and Characteaizatioa, Philips Semiconductors, Crolles, France DOI: 10.1109/ICMTS.1999.766241 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Study of low frequency noise in the 0.18 µm silicon CMOS transistors T. Boutchacha, G. Ghibaudo1, B. Belmekki Laboratoire d'Analyse des Composants A Semiconducteurs, Institut d'Electronique, USTO, Algeria 1Laboratoire de Physique des Composants ä¡ Semiconducteurs, URA CNRS, ENSERG INPG, Grenoble, France DOI: 10.1109/ICMTS.1999.766221 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Comparison of micro-electronic test structures for noise measurement verification S. Van den Bosch, W. De Ketalaere1, L. Martens University of Gent, IMEC, Gent, Belgium 1NA DOI: 10.1109/ICMTS.1999.766213 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | A high density matched hexagonal transistor structure in standard CMOS technology for high speed applications A. Van den Bosch, M. Steyaert1, W. Sansen1 ESAT, Katholieke Univ., Leuven, Heverlee, Belgium 1ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1999.766245 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | A simple physical extraction method for RD-RS of asymmetric MOSFETs A. Blaum, J. Victory, C. C. McAndrew1 Advanced Circuit Research Lab-Europe, Motorola, Inc., Geneva, Switzerland 1Modeling Technology Laboratory, Motorola, Inc., Tempe, MD, USA DOI: 10.1109/ICMTS.1999.766232 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | A special test structure for the measurement of the injection dependent series resistance of power diodes S. Bellone, S. Daliento1, A. Sanseverino1 DILIE-Department of Electrical Engineering & Computer Science, University of Salerno, Italy 1Department of Electronics and Telecommunications Engineering, University of Napoli Federico II, Italy DOI: 10.1109/ICMTS.1999.766220 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Measurement of N-well sheet resistance under p+ diffusion and p channel gate R. A. Ashton Bell Laboratories, Lucent Technologies, Inc., Orlando, FL, USA DOI: 10.1109/ICMTS.1999.766214 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | 3D characterization of RF power transistors T. Arnborg, T. Johansson Ericsson Components AB, Kista, Sweden DOI: 10.1109/ICMTS.1999.766230 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Sheet and line resistance of patterned SOI surface film CD reference materials as a function of substrate bias R. A. Allen, E. M. Vogel, L. W. Linholm, M. W. Cresswell Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1999.766215 HOVER FOR ABSTRACT | PDF Xplore | |
| 1999 | Null holographic test structures for the measurement of overlay and its statistical variation S. A. AbuGhazeleh, P. Christie1, V. Agrawal1, J. T. M. Stevenson2, A. J. Walton2, A. M. Gundlach2, S. Smith2 Dept. of Electr. & Comput. Eng., Delaware Univ., Newark, DE, USA 1Department of Electrical and Computer Engineering, University of Delaware, Newark, DE, USA 2Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1999.766235 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | A new variational method to determine effective channel length and series resistance of MOSFET's K. Yamaguchi, H. Amishiro, M. Yamawaki, S. Asai ULSI Laboratory, Mitsubishi Electric Corporation, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1998.688054 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Test structures to characterise a novel circuit fabrication technique that uses offset lithography A. J. Walton, J. T. M. Stevenson, M. Fallon1, P. S. A. Evans2, B. J. Ramsey2, D. Harrison2 Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK 1National Semiconductor Larkfield Industrial Estate, Greenock, UK 2Department of Design, Brunei University, Egham, Surrey, UK DOI: 10.1109/ICMTS.1998.688032 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Current status and issues of X-ray mask S. Uchiyama NTT Systems Electronics Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1998.688038 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | A prediction method of oxide breakdown caused by defects in SiO2 films H. Uchida, N. Hirashita VLSI Research and Development Center, OKI Electric Industry Company Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.1998.688062 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Measurement of lithographical proximity effects on matching of bipolar transistors H. P. Tuinhout, W. C. M. Peters1 Philips Research Laboratory, Netherlands 1Philips Semiconductors Nijmegen, Netherlands DOI: 10.1109/ICMTS.1998.688025 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Evaluation of the scaling limit of a narrow U-groove isolation structure by using test structures Y. Tamaki, T. Hashimoto Device Development Center, Hitachi and Limited, Ome, Tokyo, Japan DOI: 10.1109/ICMTS.1998.688045 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | A new test structure for evaluation of extrinsic oxide breakdown K. Shiga, J. Komori, M. Katsumata, A. Teramoto, M. Sekine ULSI LaboratoryEvaluation Analysis Center, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1998.688068 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Anomalous geometry dependence of source/drain resistance in narrow-width MOSFETs A. J. Scholten, D. B. M. Klaassen Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1998.688046 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | A novel unified transient enhanced diffusion model on the basis of RSF with process database H. Sato, K. Tsuneno, H. Masuda Device Development Center, Hitachi and Limited, Ome, Tokyo, Japan DOI: 10.1109/ICMTS.1998.688067 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | The influence of SiN films on negative bias temperature instability and characteristics in MOSFET's K. Sasada, M. Arimoto, H. Nagasawa, A. Nishida, H. Aoe, T. Dan, S. Fujiwara, Y. Matsushita, K. Yodoshi Microelectronics Research Center, SANYO Electric Company Limited, Gifu, Japan DOI: 10.1109/ICMTS.1998.688072 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | A new method for electrical extraction of spacer width, poly sheet resistance, and poly CD in salicide process G. A. Rezvani, S. Bothra1, X. . -W. Lin1, A. Ho1 VLSI Technol. Inc., San Jose, CA, USA 1Technology Development Department, VLSI Technology, Inc., CA, USA DOI: 10.1109/ICMTS.1998.688034 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | A high density integrated test matrix of MOS transistors for matching study L. Portmann, C. Lallement1, F. Krummenacher Electronics Laboratory, Swiss Federal Institute of Technology, Lausanne, Switzerland 1ENSPT, ERM-PHASE, Illkirch-Graffenstaden, France DOI: 10.1109/ICMTS.1998.688028 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | New method for monitoring of analogue processes-evaluation of the impact of metalisation on the performance of precise analogue resistors A. Pergoot, P. Cox, P. Vercruysse, I. Wuyts, P. Raes Alcatel Mietec, Oudenaarde, Belgium DOI: 10.1109/ICMTS.1998.688026 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Electrical characteristics of 0°/±45°/90°-orientation CMOSFET with source/drain fabricated by various ion-implantation methods T. Ohzone, M. Okina, T. Matsuda Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan DOI: 10.1109/ICMTS.1998.688056 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | An analysis of hot-carrier-induced photoemission profiles in n-MOSFETs T. Ohzone, N. Matsuyama, N. Hosoi1, T. Matsuda Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan 1NA DOI: 10.1109/ICMTS.1998.688084 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Benchmark methodology of interconnect capacitance simulation using inter-digitated capacitors O. S. Nakagawa, S. . -Y. Oh, T. Hsu, S. Habu1 Hewlett-Packard Laboratories, ULSI Research Laboratories, Palo Alto, CA, USA 1Hachioji Semiconductor Test Division, Hewlett Packard Company, Tokyo, Japan DOI: 10.1109/ICMTS.1998.688103 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Test structure for characterizing capacitance matrix of multi-layer interconnections in VLSI T. Mido, H. Ito, K. Asada Department of Electronic Engineering, University of Tokyo, Bunkyo, Tokyo, Japan DOI: 10.1109/ICMTS.1998.688090 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Statistical characterization of 0.18 µm low-power CMOS process using efficient parameter extraction K. G. McCarthy, E. V. Saavedra Diaz, D. B. M. Klaassen, A. Mathewson National Microelectronics Research Centre, Cork, Ireland DOI: 10.1109/ICMTS.1998.688055 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Extraction of the Si-SiO2 interface trap layer parameters in MOS transistors using a new charge pumping analysis Y. Maneglia, D. Bauza LPCS, ENSERGDNPG, Grenoble, France DOI: 10.1109/ICMTS.1998.688069 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | | Detailed observation of small leak current in flash memories with thin tunnel oxides Y. Manabe, K. Okuyama1, K. Kubota1, A. Nozoe2, T. Karashima1, K. Ujiie3, H. Kanno3, M. Nakashima4, N. Ajika5 Hitachi Ltd, Tokyo, Japan 1Semiconductor & Integrated Circuits Div, Hitachi and Limited, Kodaira, Tokyo, Japan 2Device Development Center, Hitachi and Limited, Tokyo, Japan 3Hitachi ULSI Engineering Corporation, Tokyo, Japan 4Semiconductor Group Manufacturing Technology Div, Mitsubishi Electric Corporation Limited, Hyogo, Japan 5Mitsubishi Electric Corporation, ULSI Laboratory, Hyogo, Japan DOI: 10.1109/ICMTS.1998.688049 HOVER FOR ABSTRACT | PDF Xplore |
| 1998 | Test structures for MCM-D technology characterization M. Lozano, J. Santander, E. Cabruja, C. Perello, M. Ullan, E. Lora-Tamayo Centro Nacional de Microelectrtònica, Campus Universidad Autónoma de Barcelona, Barcelona, Spain DOI: 10.1109/ICMTS.1998.688065 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | A novel method for base and emitter resistance extraction in bipolar junction transistors from static and low frequency noise measurements P. Llinares, G. Ghibaudo1, N. Gambetta2, Y. Mourier3, A. Monroy2, G. Lecoy3, J. A. Chroboczek France Telecom, éCentre National d Etudes Télélcommunications, Meylan, France 1URA-CNRS, Laborsitoire Physique Composants à Semiconducteurs, Grenoble, France 2SGS-THOMSON Microelectronics, Crolles, France 3USTL, Centre d''Electronique Montpellier II, Montpellier, France DOI: 10.1109/ICMTS.1998.688043 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | On the use of test structures for the electro-mechanical characterization of a CMOS compatible MEMS technology L. Latorre, Y. Bertrand, P. Nouet Laboratoire dlnformatique, Universite Montpellier, Montpellier, France DOI: 10.1109/ICMTS.1998.688064 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Advanced characterization method for sub-micron DRAM cell transistors I. Kurachi Process Technology Center, OKI Electric Industry Company Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.1998.688048 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Prediction of AC performance of double-polysilicon bipolar transistors from e-test parameters: An experiment S. C. Kelly, E. C. Griffith, J. A. Power, M. O'Neill1 Analog Devices, Raheen Industrial Estate, Limerick, Ireland 1NA DOI: 10.1109/ICMTS.1998.688059 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | A new direct extraction algorithm for intrinsic Gummel-Poon BJT model parameters F. Ingvarson, K. O. Jeppson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1998.688061 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Wafer level defect density distribution using checkerboard test structures C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1998.688050 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Strategy to disentangle multiple faults to identify random defects within test structures C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1998.688058 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Monitoring method of the tunnel oxide degradation by MOS capacitor H. Hazama Microelectronics Engineering Laboratory, Toshiba Corporation, Yokohama, Japan DOI: 10.1109/ICMTS.1998.688051 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | A new method for extracting the capacitance coupling coefficients of sub-0.5-µm flash memory cells in the negative gate bias mode K. Haraguchi, H. Kume1, M. Ushiyama1, M. Ohkura1 Central Res. Lab., Hitachi Ltd., Kokubunji, Japan 1CenM Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan DOI: 10.1109/ICMTS.1998.688100 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | 300 mm evaluation activities in Selete K. Fujiwara Semiconductor Leading Edge Technologies, Inc., Yokohama, Japan DOI: 10.1109/ICMTS.1998.688022 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | New characterization methodology for flash memory cell using CAST structure M. Fan, U. C. Liu, J. C. Guo, M. T. Wang, F. Shone1 Device Department, Macronix International Company Limited, Hsinchu, Taiwan 1Product Development Division II, Macronix International Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.1998.688052 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Using test structures to assess the impact of critical process steps on MOS transistor matching H. Elzinga Philips Semiconductors, Nijmegen, Netherlands DOI: 10.1109/ICMTS.1998.688053 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Extraction of sheet resistance from four-terminal sheet resistors replicated in monocrystalline films with non-planar geometries M. W. Cresswell, N. M. P. Guillaume1, R. A. Allen, W. F. Guthrie, R. N. Ghoshtagore1, J. C. I. Owen, Z. Osborne, N. Sullivan1, L. W. Linholm National Institute of Standards and Technology, Gaithersburg, MD, US 1NA DOI: 10.1109/ICMTS.1998.688030 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Measurement of '1/f' noise in narrow poly-silicon emitter bipolar transistor structures S. D. Connor Bipolar Characterization Group, Central Research and Development, GEC Plessey Semiconductors Limited, Lancashire, UK DOI: 10.1109/ICMTS.1998.688060 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Characterization and application of interconnect process parameters A. Chou, K. . -J. Chang1, R. Mathews1, K. Wong1, T. Wang2, Y. . -H. Wei2, K. C. Su3, P. Hsue3 Frequency Technol. Inc., San Jose, CA, USA 1Frequency Technology, Inc., San Jose, CA, USA 2S3, Inc., Santa Clara, CA, USA 3United Microelectronics Corporation Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.1998.688066 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Requirements and challenges for lithography...beyond 193 nm optics J. Canning SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1998.688029 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | A new characterization method for accurate capacitor matching measurements using pseudo-floating gate test structures in submicron CMOS and BiCMOS technologies O. Roux dit Buisson, G. Morin, F. Paillardet, E. Mazaleyrat SGS-THOMSON Microelectronics, Crolles, France DOI: 10.1109/ICMTS.1998.688096 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Direct extraction of SPICE Gummel-Poon parameters for high frequency modeling J. W. Breti, J. D. Kendall, L. Nathawad1 Gennum Corporation, Burlington, ONT, Canada 1School of Engineering Science, Simon Fraser University, Burnaby, BC, Canada DOI: 10.1109/ICMTS.1998.688047 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Study of low frequency noise in scaled down silicon CMOS transistors T. Boutchacha, G. Ghibaudo1, B. Blmekki Algerie and Laboratoire de Physique des Composants à Semiconducteurs, Institute d'ElectrNonique USTO 1CNRS, France DOI: 10.1109/ICMTS.1998.688057 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Analysis of a new test pattern for measuring the carrier-carrier scattering mobilities versus injection level in silicon S. Bellone, G. V. Persiano, C. Parrella Dip. di Ingegneria dell' Informazione ed Ingegneria Elettrica, Università di Salerno, Benevento, Italy DOI: 10.1109/ICMTS.1998.688063 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Monitoring of SRAM gate patterns in KrF lithography by ellipsometry H. Arimoto, S. Nakamura, S. Miyata1, K. Nakagawa1 Fujitsu Laboratories Limited, Atsugi, Japan 1Fujitsu Laboratories Limited, Mie, Japan DOI: 10.1109/ICMTS.1998.688036 HOVER FOR ABSTRACT | PDF Xplore | |
| 1998 | Temperature dependence of the modulation of electrical linewidth of single-crystal critical dimension artifacts R. Allen, O. Oyebanjo, M. W. Cresswell1, L. W. Linholm Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1George Washington University, Washington D.C., DC, USA DOI: 10.1109/ICMTS.1998.688037 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Study of "on-chip" measurement methods of thin film mechanical properties for micromachining Quanbo Zou, Zhijian Li, Litian Liu Institute of Microelectronics, Tsinghua University, Beijing, China DOI: 10.1109/ICMTS.1997.589404 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Optimization of via contact test structure for electro-migration S. Yamamoto, J. Komori, Y. Takata, M. Sekine, H. Koyama ULSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1997.589338 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Lateral power MOSFET low-doped drain (LDD) misalignment test structure I. M. Vitomirov, S. N. Seabridge, A. D. Raisanen, T. Tellier Xerox Corporation, Webster, NY, USA DOI: 10.1109/ICMTS.1997.589321 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | On the oxide thickness extraction in deep-submicron technologies E. Vincent, G. Ghibaudo1, G. Morin, C. Papadas SGS THOMSON Microelectronics, Central R&D, Crolles, France 1Laboratorie de Physique des Composants à Semiconducteurs ENSERG, UMR CNRS 5531, Grenoble, France DOI: 10.1109/ICMTS.1997.589349 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | A digital test structure for simultaneous bird's beak length and misalignment measurement in polysilicon emitter bipolar technologies M. Ullan, M. Lozano, J. Santander, E. Lora-Tamayo, S. Nigrin1, P. H. Osborne1 Centro Nacional de Microelectrónica, Barcelona, Spain 1Cheney Manor, GEC Plessey Semiconductors Limited, Swindon, UK DOI: 10.1109/ICMTS.1997.589314 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | | Test structures for investigation of metal coverage effects on MOSFET matching H. P. Tuinhout, M. Vertregt1 Philips Res. Lab., Eindhoven, Netherlands 1Philips Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1997.589386 HOVER FOR ABSTRACT | PDF Xplore |
| 1997 | Evaluation of hFE fluctuation of high-performance IDP emitter transistors by using test structures Y. Tamaki, T. Hashimoto, K. Watanabe, T. Shiba1 Device Development Center, Hitachi and Limited, Imai, Tokyo, Japan 1Central Research Laboratory, Hitachi and Limited, Imai, Tokyo, Japan DOI: 10.1109/ICMTS.1997.589388 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Integrated test circuit to measure polarization characteristics of ferroelectric capacitors for development of mega-bit scale FeRAM M. Takeo, M. Azuma, T. Sumi, K. Tatsuuma Kyoto Research Laboratory, Matsushita Electronics Corporation, Kyoto, Japan DOI: 10.1109/ICMTS.1997.589352 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | A proposal for modeling substrate coupling in Si-MMICs and its experimental verification up to 40 GHz M. Pfost, H. . -M. Rein AG Halbleiterbauelemente, Ruhr University of Bochum, Bochum, Germany DOI: 10.1109/ICMTS.1997.589332 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Test structures for characterising a damascene CMP interconnect process C. M. Peyne, A. O'Hara, J. T. M. Stevenson, J. P. Elliott, A. J. Walton, M. Fallon Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589369 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | A compact monitoring circuit for real-time on-chip diagnosis of hot-carrier induced degradation H. Oner, B. Bayrakci, Y. Leblebici1 Department of Electrical and Electronics Engineering, Istanbul Technical University, Turkey 1Electronics Laboratory, Integrated Systems Center DOI: 10.1109/ICMTS.1997.589340 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Performance evaluation of CMOS ring-oscillators with source/drain regions fabricated by asymmetric/symmetric ion-implantation T. Ohzone, T. Miyakawa1, T. Matsuda1, T. Yabu1, S. Odanaka1 Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan 1Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan DOI: 10.1109/ICMTS.1997.589356 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | A new test structure for interconnect capacitance monitoring P. Nouet, A. Toulouse Laboratoire d'Informatique, de Robotique et ed Microéletronique de Montpellier LIRMM-U.M.R C55060, University of Montpellier 2, MONTPELLIER, France DOI: 10.1109/ICMTS.1997.589343 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Characterisation of the threshold voltage variation: a test chip and the results M. Niewczas Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, Poland DOI: 10.1109/ICMTS.1997.589378 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Test structures for the evaluation of air-bridge interconnection in GaAs IC's fabrication process M. Nakanishi, M. Noda, H. Nakano, T. Sonoda, M. Otsubo Optoelectronic and Microwave Devices Laboratory, Mitsubishi Electric Corporation Limited, Hyogo, Japan DOI: 10.1109/ICMTS.1997.589408 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | A DC voltage capacitance matching tester B. W. McNeill, C. Hanle1 Bell Labs, Lucent Technologies, Inc., Allentown, PA, USA 1Analog Devices, Inc., Wilmington, MA, USA DOI: 10.1109/ICMTS.1997.589394 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Reference-length shortening by Kelvin voltage taps in linewidth test structures replicated in monocrystalline silicon films W. E. Lee, W. F. Guthrie, M. W. Cresswell, R. A. Allen, J. J. Sniegowski, L. W. Linholm Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1997.589322 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Design and characterization of SiGe TFT devices and process using Stanford's test chip design environment M. V. Kumar, V. Subramanian, K. C. Saraswat, J. D. Plummer, W. Lukaszek Center for Integrated Systems, University of Stanford, Stanford, USA DOI: 10.1109/ICMTS.1997.589363 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Improved method for the extraction of oxide charge density and centroid from the current-voltage characteristic shifts in a MOS structure after uniform gate stress R. Kies, G. Ghibaudo, G. Pananakakis, C. Papadas1 Laboratoire de Physique des Composants à Semiconducteurs, UMR CNRS, ENSERG, Grenoble, France 1SGS-Thomson Microelectronics, Crolles, France DOI: 10.1109/ICMTS.1997.589350 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Separation of intrinsic and parasitic MOSFET parameters using a multiple built-in Kelvin test structure N. Kasai, H. Mori1, T. Matsuki, I. Yamamoto, K. Koyama ULSI Device Development Labs, NEC Corporation Limited, Sagamihara, Kanagawa, Japan 1Microelectronics Research Labs, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.1997.589396 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Test chip and data considerations for MOS parameter extraction P. R. Karlsson, K. O. Jeppson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1997.589375 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Digital test circuit design and optimization for AC hot-carrier reliability characterization and model calibration under realistic high frequency stress conditions W. Jiang, H. Le, S. A. Kim, J. E. Chung, Y. . -J. Wu1, P. Bendix1, J. Jensen1, R. Ardans1, S. Prasad1, A. Kapoor1, T. E. Kopley, T. Dungan, P. Marcoux EECS Department, Massachusetts Institute of Technology, Cambridge, MA, USA 1Research and Development, LSI Logic Corporation, Milpitas, USA DOI: 10.1109/ICMTS.1997.589335 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Error correction for finite semiconductor resistivity in Kelvin test structures A. S. Holland, G. K. Reeves, H. B. Harrison1 Royal Melbourne Institute of Technology, Melbourne, VIC, Australia 1Griffith University, Nathan, QLD, Australia DOI: 10.1109/ICMTS.1997.589347 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Issues on short circuits in large on-chip power MOS-transistors using a modified checkerboard test structure C. Hess, L. H. Weiland, R. Bornefeld1 Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany 1NA DOI: 10.1109/ICMTS.1997.589365 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Determination of defect size distributions based on electrical measurements at a novel harp test structure C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1997.589281 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | New method for the parameter extraction in Si MOSFETs after hot carrier injection S. Hardillier, C. Mourrain, M. J. Bouzid, G. Ghibaudo1 France Telecom, CNET, Meylan, France 1Laboratorie de Physique des Composants à Semiconducteurs, ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1997.589336 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | A new technique and a test structure for evaluating Vth distribution of flash memory cells K. Hakozaki, S. . -I. Sato, K. Iguchi, K. Sakiyama VLSI Development Laboratories, IC Tenri Group, Sharp Corporation, Tenri, Japan DOI: 10.1109/ICMTS.1997.589355 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Yield prediction using calibrated critical area modelling G. J. Gaston, G. A. Allan1 GEC Plessey Semiconductors Limited, Plymouth, Devon, UK 1Department of Elect Engineering, Edinburgh University, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589292 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Novel structure to measure emitter-base misalignment M. Fallon, M. Redford, K. Findlater1, M. Newsam1 National Semiconductor, Larkfield Industrial Estate, Greenock, UK 1Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589374 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Electrical assessment of planarisation for CMP [inter-layer dielectrics] J. P. Elliott, M. Fallon, A. J. Walton, J. T. M. Stevenson, A. O'Hara, A. Shaffi, C. M. Reeves Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589345 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Electrical linewidth test structures fabricated in mono-crystalline films for reference-material applications M. W. Cresswell, J. J. Sniegowski1, R. N. Ghoshtagore2, R. A. Allen2, W. F. Guthrie2, L. W. Linholm2 National Institute of Standards and Technology, Gaithersburg, MD, US 1Microelectronic Development Laboratories, Sandia National Laboratories, Albuquerque, NM, USA 2NA DOI: 10.1109/ICMTS.1997.589305 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Test structure for mismatch characterization of MOS transistors in subthreshold regime M. Conti, G. F. Dalla Betta1, S. Orcioni, G. Soncini1, C. Turchetti, N. Zorzi2 Department of Electronics, University of Ancona, Ancona, Italy 1Department of Materials Engineering, University of Trento, Trento, Italy 2Microelectronics Division, I.R.S.T., Trento, Italy DOI: 10.1109/ICMTS.1997.589380 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | On wafer noise measurement using bipolar transistor RF test structures S. D. Connor Bipolar Characterization Group, Central Research and Development, G. E. C. Plessey Semiconductors, Lancashire, UK DOI: 10.1109/ICMTS.1997.589329 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Measurement and characterization of multi-layered interconnect capacitance for deep submicron VLSI technology Dae-Hyung Cho, Man-Ho Seung, Nam-Ho Kim, Hun-Sup Park, Jae-Kyung Wee1, Young-June Park1, Hong-Shik Min1 Advanced Device Physics Laboratory, System IC R & D Laboratory, Hyundai Electronics Industries Company Limited, Icheon, Gyeonggi, South Korea 1Department of Electrical Engineering, Seoul National University, Seoul, South Korea DOI: 10.1109/ICMTS.1997.589346 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Test structure and methodology for experimental extraction of threshold voltage shifts due to quantum mechanical effects in MOS inversion layers G. Chindalore, S. Hareland, S. Jallepalli1, A. F. Fasch2, C. M. Maziar, V. K. F. Chia3, S. Smith3 Microelectronics Research Center, Department of Electrical and Computer Engineering, University of Technology, Austin, TX, USA 1Motorola, Austin, TX, USA 2NA 3Charles Evans and Associates, Red Wood, USA DOI: 10.1109/ICMTS.1997.589377 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution J. C. Chen, D. Sylvester, C. Hu, H. Aoki1, S. Nakagawa1, S. . -Y. Oh1 Department of EECS, University of California, Berkeley, USA 1Hewlett Packard Laboratories, Palo Alto, USA DOI: 10.1109/ICMTS.1997.589342 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Flicker noise characterization of polysilicon resistors in submicron BiCMOS technologies O. Roux dit Buisson, G. Morin SGS-Thomson Microelectronics, Crolles, France DOI: 10.1109/ICMTS.1997.589331 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Test structures applied to the rapid prototyping of sensors M. G. Buehler, L. . -J. Cheng, D. P. Martin1 Microdevices Laboratory, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, USA 1Halcyon Microelectronics, Inc., Irwindale, USA DOI: 10.1109/ICMTS.1997.589406 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | New approach for the extraction of gate voltage dependent series resistance and channel length reduction in CMOS transistors H. Brut, A. Juge1, G. Ghibaudo2 SGS-Thomson Microelectron., Crolles, France 1Central R&D-Modeling and characterization, SGS-Thomson Microelectronics, Crolles, France 2Laboratoire de Physique des Composants à Semiconducteurs, URA CNRS-ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1997.589391 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | GIDL-induced charge injection for characterization of plasma edge damage in CMOS devices T. Brozek, A. Sridharan, J. Werking1, S. R. Anderson1, Y. D. Chan1, C. R. Viswanathan Department of Electrical Engineering, University of California, Los Angeles, USA 1SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1997.589348 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Optical signal injection for high-speed wafer level function test of integrated circuits H. H. Berger, J. Sturm, F. Esfahani, A. Benedix, S. Von Aichberger, B. Muller, K. . -O. Hofacker1 Institute of Microelectronics and Solid State Electronics, Technical University Berlin, Berlin, Germany 1Thesys GmbH, Erfurt, Germany DOI: 10.1109/ICMTS.1997.589326 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Test structures for hillock growth, via filling and for measuring the quality of thin films D. J. Bennett, A. O'Hara1, I. Underwood1, A. J. Walton1 Dept. of Electr. Eng., Edinburgh Univ., UK 1Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589295 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Test structures to measure the heat capacity of CMOS layer sandwiches M. von Arx, O. Paul, H. Baltes ETH ZurichPhysical Electronics Laboratory, ETH Zurich, Zurich, Switzerland DOI: 10.1109/ICMTS.1997.589399 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | A statistical method for the analysis of CMOS process fluctuations on dynamic performance M. De Almeida, X. Regnier1, J. M. Daga2, M. Robert2, D. Auvergne2 Aerospatiale, Suresnes, France 1Louis Blériot Research Center, AEROSPATIALE, Suresnes, France 2LIRMM, UMR CNRS Université Montpellier, Montpellier, France DOI: 10.1109/ICMTS.1997.589361 HOVER FOR ABSTRACT | PDF Xplore | |
| 1997 | Wire-segment holographic test structures for statistical interconnect metrology S. A. AbuGhazaleh, J. T. M. Stevenson1, P. Christie, A. J. Walton1 Department of Electrical Engineering, University of Delaware, Newark, USA 1Department of Computer Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1997.589353 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | On matching properties and process factors for submicrometer CMOS Shyh-Chyi Wong, Kuo-Hua Pan1, Dye-Jyun Ma2, M. S. Liang3, P. N. Tseng3 Department of Electronics Engineering, Feng Chia University FCU, Taichung, Taiwan 1Institute of Electronics, National Chiao Tung University, HsinChu, Taiwan 2Department of Electrical Engineering, Chung-Hsing University, Taichung, Taiwan 3Taiwan Semiconductor Manufacturing Company Limited, HsinChu, Taiwan DOI: 10.1109/ICMTS.1996.535620 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A wafer level monitoring method for plasma-charging damage using antenna PMOSFET test structure H. Watanabe, J. Komori, K. Higashitani, Y. Mashiko, H. Koyama ULSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1996.535659 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Heating due to bias in GaAs MESFETs J. R. Tellez, R. W. Clarke Department of Electronic & Electrical Engineering, University of Bradford, UK DOI: 10.1109/ICMTS.1996.535638 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Test structure for thermal monitoring V. Szekely, Z. Kohari, C. Marta, M. Rencz, B. Courtois1 Department of Electron Devices, Technical University of Budapest, Budapest, Hungary 1TIMA Laboratory, Grenoble, France DOI: 10.1109/ICMTS.1996.535630 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | An improved test structure to characterize ultra-low hot carrier injection in homogeneous conditions L. Selmi, R. Bez1, E. Sangiorgi2 DEIS, University of Bologna, Bologna, Italy 1SGS-THOMSON Microelectronics, Italy 2DIEGM, University of Udine, Udine, Italy DOI: 10.1109/ICMTS.1996.535625 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Test structures for automated contactless inline wafer inspection A. V. S. Satya IBM Microelectronics, East Fishkill, NY, USA DOI: 10.1109/ICMTS.1996.535665 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A new method to determine effective channel length, series resistance and threshold voltage M. Sasaki, H. Ito, T. Horiuchi ULSI Device Development Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.1996.535635 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Universal surfaces for the accurate contact resistivity extraction on Kelvin structures with upper and lower resistive layers J. Santander, M. Lozano, A. Gotz, C. Cane, E. Lora-Tamayo Centro Nacional de Microelectrónica, Universidad Autónoma de Barcelona, Barcelona, Spain DOI: 10.1109/ICMTS.1996.535623 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Direct extraction method of SOI MOSFET transistors parameters J. P. Raskin, R. Gillon, D. Vanhoenacker, J. P. Colinge1 Laboratoire dE28099Hyperfreqluences, Universite Catholique de Louvain, Louvain-la-Neuve, Belgium 1NA DOI: 10.1109/ICMTS.1996.535644 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Measurement of interface states in the LDD region of a MOS transistor using a modified charge pumping technique V. Prabhakar, T. Broiek1, Y. D. Chan2, C. R. Viswanathan Electrical Engineering Department, UCLA, Los Angeles, CA, USA 1Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA 2Rockwell International SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1996.535626 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Electrical determination of the phosphorus content in thin phosphosilicate glass films O. Popa, C. Cobianu, D. Dascalu Institute of Microtechnology, Bucharest, Romania DOI: 10.1109/ICMTS.1996.535653 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | An electrical test structure to evaluate substrate compatibility with wafer cleaning C. M. Peyne, M. Fallon1, J. T. M. Stevenson1, A. J. Walton1 Newton Industrial Estate, EKC Technology Limited, UK 1Edinburgh Microfabrication Facility Department of Electrical Engineering Kings Buildings, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1996.535882 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A new test structure for the evaluation of the injection-level dependence of carrier mobilities G. V. Persiano, S. Bellone1 Department of Electronics Engineering, University of Naples, Naples, Italy 1Department of Information and Electrical Engineering, University of Salerno, Salerno, Italy DOI: 10.1109/ICMTS.1996.535624 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Test structures for HF characterization of fully differential building blocks E. Peeters, M. Steyaert, W. Sansen Department of Electrical Engineering,ESAT-MICAS, Katholieke Universiteit Leuven, Belgium DOI: 10.1109/ICMTS.1996.535642 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Use of test structures for a wafer-level-reliability monitoring A. Papp, F. Bieringer, D. Koch, H. Kammer, H. Pohle, A. Schlemm, M. Schneegans, H. Vogt Corporate Research and Development, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1996.535658 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Asymmetry and mismatch in CMOSFETs with source/drain regions fabricated by various ion-implantation methods T. Ohzone, T. Miyakawa, T. Yabu1, S. Odanaka1 Department of Electronics and Informatics, Toyama Prefectural University, Toyama, Japan 1Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Osaka, Japan DOI: 10.1109/ICMTS.1996.535640 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A test chip for interconnect capacitance modelling in a CMOS process P. Nouet, A. Toulouse Laboratoire dE28099Informatique, de Robotique et de Microélectronique de Montpellier LIRMM, Universite Montpellier II, Montpellier, France DOI: 10.1109/ICMTS.1996.535622 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Gate delay time evaluation structure for deep-submicron CMOS LSIs K. Nishimura, M. Urano, M. Ino, K. Takeya, T. Ishihara1, Y. Kado, H. Inokawa NTT LSI Laboratories, Atsugi, Kanagawa, Japan 1NTT LSI Labs., Atsugi, Japan DOI: 10.1109/ICMTS.1996.535634 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | CMOS IC transient radiation effects investigations, model verification and parameter extraction with the test structures laser simulation tests A. Y. Nikiforov, V. I. Chumakov, O. Skorobogatov Specialized Electronic Systems, Moscow, Russia DOI: 10.1109/ICMTS.1996.535656 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Numerical analysis of the effect of geometry on the performance of the Greek cross structure M. I. Newsam, A. J. Walton, M. Fallon Edinburgh Microfabrication Facility Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1996.535655 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Kelvin test structure for measuring contact resistance of shallow junctions L. K. Nanver, E. J. G. Goudena, J. Slabbekoorn1 Delft Institute of Microelectronics and Submicron TechnologyDIMES IC Process Research Sector, Delft University of Technnology, Delft, Netherlands 1Inst. of Microelectron. & Submicron Technol., Delft Univ. of Technol., Netherlands DOI: 10.1109/ICMTS.1996.535654 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Automatic test chip documentation synthesis W. Nagorski, W. McGee, E. G. Piccioli, L. A. Bair Digital Equipment Corporation, Hudson, MA, USA DOI: 10.1109/ICMTS.1996.535650 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Test structures for electromigration evaluation in submicron technology S. Morgan, I. De Munari1, A. Scorzoni1, F. Fantini, G. Magri2, C. Zaccherini2, C. Caprile2 Dipartimento di Ingegneria dell'hformazione, Universita degli Studi di Parma, Parma, Italy 1CNR Istituto LAMEL, Bologna, Italy 2SGS-Thomson Microelectronics, Milan, Italy DOI: 10.1109/ICMTS.1996.535661 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Test structure for investigating activated doping concentrations in polycrystalline silicon S. Moran, P. K. Hurley, A. Mathewson National Microelectronics Research Centre, University College, Prospect, Ireland DOI: 10.1109/ICMTS.1996.535649 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Simultaneous determination of threshold voltage, mobility, and parasitic resistance for short-channel MOSFETs Y. Mita, M. Fujishima, K. Hoh Univ. of Tokyo, Japan DOI: 10.1109/ICMTS.1996.535633 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Test structure to measure the gate-drain coupling capacitor using accelerated techniques T. Manku Technical University of Nova Scotia, Halifax, NS, Canada DOI: 10.1109/ICMTS.1996.535621 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A test chip for ISFET/CMNOS technology development A. Lui, B. Margesin, V. Zanini, M. Zen, G. Soncini, S. Martinoia1 Microsensors and System Integration Division, IRST, Italy 1DIBE-Department of Biophysical iind Electronic Engineering, University of Genova, Genoa, Italy DOI: 10.1109/ICMTS.1996.535632 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Characterizing the mismatch of submicron MOS transistors S. J. Lovett, R. Clancy, M. Welten, A. Mathewson, B. Mason1 National Microelectronics Research Centre, University College Cork, Cork, Ireland 1GEC Plessey Semiconductors Limited, Plymouth, UK DOI: 10.1109/ICMTS.1996.535619 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A new test structure methodology for MOS hot carrier reliability M. Lee Engineering, Department Information & Communication Engineering, Dong-shin University, Choongnam, South Korea DOI: 10.1109/ICMTS.1996.535657 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A test structure advisor and a coupled, library-based test structure layout and testing environment M. V. Kumar, J. D. Plummer, W. Lukaszek Center for Integrated Systems, University of Stanford, USA DOI: 10.1109/ICMTS.1996.535646 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A new method of determining the effective channel width and its dependence on the gate voltage K. O. Jeppson, A. W. Bogren, P. R. Karlsson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1996.535637 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A quick address detection of an anomalous memory cell for flash EEPROM T. Himeno, H. Hazama, K. Sakui, K. Kanda, Y. Itoh, J. Miyamoto Semiconductor Device Engineering Laboratory, Toshiba Corporation, Japan DOI: 10.1109/ICMTS.1996.535645 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Control of application specific interconnection on gate arrays using an active checkerboard test structure C. Hess, L. H. Weiland, G. Lau1, P. Simoncit2 Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany 1Thesys Gesellschaft für Mikroelektronik mbH, Erfurt, Germany 2NA DOI: 10.1109/ICMTS.1996.585568 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A new approach to determine active doping profiles of bipolar transistors using electrical measurements and a physical device simulator I. Hachicha, P. Fouillat, T. Zimmer, J. P. Dom Cours de la liberation, IXL Universite Bordeaux I, France DOI: 10.1109/ICMTS.1996.535662 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A test chip for the development of porous silicon light emitting diodes R. Guardini, P. Bellutti1, L. Pavesi, G. Soncini1, O. Bisi I.N.F.M. and Dipartimento di Fisica, Università di Trento, Trento, Italy 1Divisione Microsensori ed Integrazione di Sistemi, IRST, Trento, Italy DOI: 10.1109/ICMTS.1996.535651 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Optimum test structure design for CMOS parasitic transistor characterisation G. J. Gaston, P. Myler GEC Plessey Semiconductors Limited, UK DOI: 10.1109/ICMTS.1996.535663 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | On the impact of spatial parametric variations on MOS transistor mismatch H. Elzinga Philips Semiconductors, Centre Commun CNET-SGS-Thomson, Crolles, France DOI: 10.1109/ICMTS.1996.535641 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A test structure for the measurement of planarisation J. P. Elliott, M. Fallon1, A. J. Walton2, J. T. M. Stevenson, A. O'Hara2 Edinburgh Microfabricutiorl Facility Department of Electrical Engineering, Kings Buildings, University of Edinburgh, Edinburgh, UK 1The University of Edinburgh, Edinburgh, Edinburgh, GB 2Dept. of Electr. Eng., Edinburgh Univ., UK DOI: 10.1109/ICMTS.1996.535664 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Spatial distribution of recombination centers in electron irradiated silicon epitaxial layers S. Daliento, A. Sanseverino, P. Spirito, L. Zeni Dipartimento di Ingegneria Elettronica, Universita degli Studi di Napoli Federico II, Napoli, Italy DOI: 10.1109/ICMTS.1996.535639 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Parametric test engineering optimization: methodology and software system T. T. d'Ouville, F. Mendez, J. Bruines1, L. Zangara2, G. Durieu2 France Telecom CNET Grenoble, France 1Philips Semiconductors, Netherlands 2Dolphin Integration, Meylan, France DOI: 10.1109/ICMTS.1996.535643 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Electrical characterisation and reliability studies of thick film gas sensor structures I. Czech, J. Manea1, J. Roggen2, G. Huyberechts, L. Stals3, L. De Schepper Institute for Material ResearchMaterial Physics Division, Limburg University Centre, Belgium 1Mater. Phys. Div., Limburgs Univ. Centrum, Diepenbeek, Belgium 2Materials and Packaging Division, IMEC, Belgium 3Institute for Material Research, Material Physics Division, Limburg University Centre, Belgium DOI: 10.1109/ICMTS.1996.535628 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Hybrid optical-electrical overlay test structure [for CMOS] M. W. Cresswell, R. A. Allen, L. W. Linholm, W. F. Guthrie, A. W. Gurnell1 National Institute for Standards and Technology, Gaithersburg, MD, USA 1NA DOI: 10.1109/ICMTS.1996.535613 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Automated extraction of matching parameters for bipolar transistor technologies S. D. Connor, D. Evanson Microelectronics Centre, G. B. C. Plessey Semiconductoirs, Lancashire, UK DOI: 10.1109/ICMTS.1996.535618 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A test structure for monitoring micro-loading effect of MOSFET gate length Joe-Sun Choi, In-Sool Chung Semiconductor Research and Development Division I, Design Laboratory II, Hyundai Electronics Industries Company Limited, South Korea DOI: 10.1109/ICMTS.1996.535612 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A quasi-three-dimensional analysis of ESD failure mechanism and a new ESD structure with rounded drain corner Jae-Hoon Choi, Hyeong-Sun Hong, Yo-Hwan Koh, Gyoo-Yeong Lee, Han-Gu Kim, Han-Sub Yoon Memory Research and Development Division, Hyundai Electronics Industries Company Limited, South Korea DOI: 10.1109/ICMTS.1996.535647 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Gas sensor test chip M. G. Buehler, M. A. Ryan Jet Propulsion Laboratoiry, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1996.535629 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | An efficient parameter extraction methodology for the EKV MOST model M. Bucher, C. Lallement, C. C. Enz Electronics Laboratory, ELB-Ecublens, Swiss Federal Institute of Technology, Lausanne, Switzerland DOI: 10.1109/ICMTS.1996.535636 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Matching properties of MOS transistors and delay line chains with self-aligned source/drain contacts M. Bolt, E. Cantatore1, M. Socha, C. Aussems, J. Solo Philips Semiconductors Faselec AG, Zurich, Switzerland 1CERN ECP EDU, Geneva, Switzerland DOI: 10.1109/ICMTS.1996.535616 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Microwave frequency measurements and modeling of MOSFETs on low resistivity silicon substrates C. Biber, T. Morf, H. Benedickter, U. Lott, W. Bachtold Laboratory for Electromagnetic Fields and Microwave Electronics, Swiss Federal Institute of Technology, Zurich, Switzerland DOI: 10.1109/ICMTS.1996.535648 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | A test chip for the development of PIN-type silicon radiation detectors G. F. Dalla Betta, M. Boscardin1, G. Verzellesi, G. U. Pignatel, A. Fazzi2, G. Soncini1 Dipartimento di Ingegneria dei Materiali, Università di Trento, Trento, Italy 1IRST, Trento, Italy 2Dipartimento di Ingegneria Nucleare, Politecnico di Milano, Milan, Italy DOI: 10.1109/ICMTS.1996.535652 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Matching of MOS transistors with different layout styles J. Bastos, M. Steyaert, B. Graindourze1, W. Sansen ESAT-MICAS, Katholieke Universiteit Leuven, Belgium 1Alcatel Mietec, Belgium DOI: 10.1109/ICMTS.1996.535615 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Influence of die attachment on MOS transistor matching J. Bastos, M. Steyaert, B. Graindourze1, W. Sansen ESAT MICAS, Katholieke Universiteit Leuven, Belgium 1Alcatel Mietec, Oudenaarde, Belgium DOI: 10.1109/ICMTS.1996.535617 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Narrow width effects in CMOS n(p)-well resistors C. Auricchio, R. Bez, A. Grossi SGS-Thomson Microelectronics, Central Research and Development, Milan, Italy DOI: 10.1109/ICMTS.1996.535614 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | Analysis of charge storage in the base of bipolar transistors and its influence on the parasitic resistance adopting an eight terminal Kelvin test structure S. Asti, T. Cavioni1, A. Neviani, P. Pavan2, M. Stival, L. Vendrame, E. Zanoni2 Dipartimento di Elettronica e Informatica, Università di Padova, Padova, Italy 1Dedicated Products Group, SGS-THOMSON Microelectronics, Cornaredo, Italy 2Dipartimento di Scienze dell'Ingegneria, Università di Modena e Reggio Emila, Modena, Italy DOI: 10.1109/ICMTS.1996.535627 HOVER FOR ABSTRACT | PDF Xplore | |
| 1996 | | Test structures to measure the Seebeck coefficient of CMOS IC polysilicon M. von Arx, O. Paul, H. Baltes Physical Electronics Laboratory, Zurich, Switzerland DOI: 10.1109/ICMTS.1996.535631 HOVER FOR ABSTRACT | PDF Xplore |
| 1996 | Observation of light emissions from hot electrons and latch-up at the cleaved surface of CMOS structures T. Aoki NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1996.535660 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | An automatic implementation of dynamic electromigration tests Wei Zhang, Y. H. Cheng, Z. G. Li, W. L. Guo, Y. H. Sun, X. X. Li Electronic Engineering Department Reliability Physics La, Beijing Polytechnic University, Beijing, China DOI: 10.1109/ICMTS.1995.513980 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Characterization and modeling of MOS mismatch in analog CMOS technology Shyh-Chyi Wong, Jyh-Kang Ting, Shun-Liang Hsu Technology Development Division, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan DOI: 10.1109/ICMTS.1995.513967 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Wafer mapping using DOE and RSM techniques A. J. Walton, M. Fallon, D. Wilson1 Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK 1Motorola Limited, Glasgow, UK DOI: 10.1109/ICMTS.1995.513989 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Characterization and modeling of transistors embedded in a high performance bipolar logic array E. H. Tyler Applied Micro Circuits Corporation, San Diego, CA, USA DOI: 10.1109/ICMTS.1995.513969 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Accurate capacitor matching measurements using floating gate test structures H. P. Tuinhout, H. Elzinga1, J. T. Brugman2, F. Postma2 Philips Research, Philips Electronics N.V., Eindhoven, Netherlands 1Philips Semiconductors, Philips Electronics N.V., France 2Philips Semiconductors, Philips Electronics N.V., Nijmegen, Netherlands DOI: 10.1109/ICMTS.1995.513960 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Accurate determination of the main parameters from Vt(Vb) curves of fully-depleted SOI devices A. Toffoli, J. L. Pelloie, O. Faynot, C. Raynaud, B. Giffard, J. Hartmann LETI (CEA Technologies Avancees), Grenoble, France DOI: 10.1109/ICMTS.1995.513948 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Test structure and simplified distribution model for identification of base resistance components in self-aligned polysilicon base electrode bipolar transistors M. Tanabe, H. Shimamoto, T. Onai1, K. Washio1 Musashino Office, Hitachi Device Engineering Company Limited, Tokyo, Japan 1Central Research Laboratory, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1995.513958 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Characterization of density of trap states at the back interface of SIMOX wafers A. Takubo, T. Hanajiri, T. Sugano, K. Kajiyama1 EE Department, Toyo University, Kawagoe, Japan 1Advanced Semiconductor Technology Laboratory, Nippon Steel Corporation, Kanagawa, Japan DOI: 10.1109/ICMTS.1995.513949 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Influence of tilted high-energy ion-implantation upon scaled CMOS structure H. Takatsuka, H. Sato, T. Izawa, T. Hisaeda, H. Goto, S. Kawamura LSI Process Development Div, Fujitsu Laboratories of America, Inc., Kawasaki, Japan DOI: 10.1109/ICMTS.1995.513982 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Test structure for determining the charge distribution in the oxide of MOS structure Y. Takahashi, S. Imaki, K. Ohnishi, M. Yoshikawa1 Dcpartment of Electronic Engineering College of Science Technology, Nihon University, Funabashi, Chiba, Japan 1Takasaki Radiation Chemistry Research, Establishment Japan Atomic Energy Research Institute, Takasaki, Japan DOI: 10.1109/ICMTS.1995.513981 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | The charging and discharging of stress-generated traps inside thin silicon oxide R. S. Scott, D. J. Dumin1 Center for Semiconductor Device Reliability Research, Department of Electrical and Computer Engineering, Clemson University, Clemson, SC, USA 1Clemson University, Clemson, SC, US DOI: 10.1109/ICMTS.1995.513979 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Understanding clustering of defects in a sub-0.5 µm CMOS fabricator A. V. S. Satya Zip EMI, IBM Microelectronics, NY, USA DOI: 10.1109/ICMTS.1995.513990 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Stress induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics S. Satoh, G. J. Hemink, F. Hatakeyama1, S. Aritome ULSI Research Center, TOSHIBA Corporation, Kawasaki, Japan 1Microelectronics Center, ULSI Research Center, Kawasaki, Japan DOI: 10.1109/ICMTS.1995.513953 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Determination of solid solubility limit of In and Sb in Si using bonded silicon-on-insulator (SOI) substrate A. Sato, K. Suzuki, H. Horie, T. Sugii Fujitsu Laboratories of America, Inc., Atsugi, Japan DOI: 10.1109/ICMTS.1995.513984 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | A new hierarchical RSM for TCAD-based device design to predict CMOS development H. Sato, K. Tsuneno, K. Aoyama, T. Nakamura, H. Kunitomo1, H. Masuda Hitachi and Limited, Tokyo, Japan 1Hitachi Micro-computer Engineer, Tokyo, Japan DOI: 10.1109/ICMTS.1995.513991 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | A combined CBR-MOS gate structure for mobility and channel width extraction J. Santander, M. Lozano, C. Cane, E. Lora-Tamayo Campus UAB,Centro Nacional de Microelectróica, CSIC, Spain DOI: 10.1109/ICMTS.1995.513987 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Evidence of a correlation between process yields and reliability data for a rad-hard SOI technology V. Riviere, A. Touboul, S. B. Amor1, G. Gregoris2, J. L. Stevenson3, P. S. Yeung3 IXL, URA 846-CNRS, Université Bordeaux 1, Talence, France 1NA 2Alcatel ESpace, Toulouse, France 3Intelsat Limited, Washington D.C., DC, USA DOI: 10.1109/ICMTS.1995.513976 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | United methodology for pre-determination of bipolar transistor SPICE model parameters for low, middle and high power ICs K. O. Petrosjanc, I. A. Kharitonov1, N. I. Rjabov Moscow University of Electronics and Mathematics, Moscow, Russia 1Moscow Univ. of Electron. & Math., Russia DOI: 10.1109/ICMTS.1995.513975 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Statistics for matching A. Pergoot, B. Graindourze, E. Janssens, J. Bastos1, M. Steyaert1, P. Kinget1, R. Roovers1, W. Sansen1 Alcatel Mietec, Oudenaarde, Belgium 1Department of Electrical Engineering,ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1995.513971 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | An automated approach to wafer distribution analysis C. Perello, M. Lozano, J. Millan1, E. Lora-Tamayo Centre Nacional de Microelectrònica, Universitat Autònoma Barcelona, Barcelona, Spain 1Centre Nacional de Microelectron., Univ. Autonoma de Barcelona, Spain DOI: 10.1109/ICMTS.1995.513972 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Source/drain junction leakage current of LDD NMOSFET with various spacer materials Jae-Chul Om, Myung-Suk Jo1, Hyo-Sik Park, In-Sool Chung, Wi-Sik Min Semiconductor Research and Development Laboratory, Hyundai Electronics Industries Company Limited, South Korea 1Department of Electronic Engineering, Kangnung National University, Kangnung, Kangwon, South Korea DOI: 10.1109/ICMTS.1995.513968 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Electrical characteristics of CMOSFETs with gates crossing source/drain regions at 90° and 45° T. Ohzone, N. Matsuyama Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.1995.513970 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Gate antenna structures for monitoring oxide quality and reliability S. R. Nariani, C. T. Gabriel, D. Pramanik, K. Ng VLSI Technology, Inc., San Jose, CA, USA DOI: 10.1109/ICMTS.1995.513952 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Non-destructive method of shear stress test by new test structure H. Matsushima, T. Wada Matsushita Electronics Corporatio, Quality Laboratory Semiconductor Group, Kyoto, Japan DOI: 10.1109/ICMTS.1995.513938 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Three-port RF characterization of foundry dual-gate FETs using two-port test structures with on-chip loading resistors U. Lott, W. Baumberger, U. Gisiger1 Laboratory for Electromagnetic Fields and Microwave Electronics, Swiss Federal Institute of Technology, Zurich, Switzerland 1AFIF, Zurich, Switzerland DOI: 10.1109/ICMTS.1995.513966 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | A test chip for MOS transistor capacitance characterization R. Lorival, P. Nouet Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), Universite Montpellier II/CNRS, Montpellier, France DOI: 10.1109/ICMTS.1995.513961 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Measurement of patterned film linewidth for interconnect characterization L. W. Linholm, R. A. Allen, M. W. Cresswell, R. N. Ghoshtagore, S. Mayo, H. A. Schafft, J. A. Kramar1, E. C. Teague1 Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Precision Engineering Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1995.513939 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Direct determination of base transit time for heterojunction bipolar transistors without cutoff frequency measurement Seonghearn Lee Semiconductor Technology Division, Electronics and Telecommunications Research Institute, Taejon, South Korea DOI: 10.1109/ICMTS.1995.513957 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | A test structure for the measurement of fast internal signals in CMOS VLSI circuits B. Laquai, H. Richter, B. Hoefflinger IMS, Stuttgart, Germany DOI: 10.1109/ICMTS.1995.513943 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | A new test structure to study electromigration at grain boundaries using the single-crystal aluminum interconnection K. Kusuyama, Y. Nakajima, Y. Murakami Electronics and Information Systems Research Laboratory, Nissan Motor Company Limited, Yokosuka, Kanagawa, Japan DOI: 10.1109/ICMTS.1995.513977 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Evaluation of charge build-up in wafer processing by using MOS capacitors with charge collecting electrodes H. Kubo, T. Namura, K. Yoneda, H. Ohishi, Y. Todokoro Kyoto Research Laboratory, Matsushita Electronics Corporation, Kyoto, Japan DOI: 10.1109/ICMTS.1995.513936 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Test structures for the evaluation of Si substrates Y. Kokawa, M. Kimura, M. Kume, H. Yamamoto, A. Koyama ULSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1995.513950 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | On-chip measurement of interconnect capacitances in a CMOS process A. Khalkhal, P. Nouet Laboratoire dE28099Informatique, de Robotique et dc Microelectronique de Montpellier, Universite Montpellier II/CNRS, Montpellier, France DOI: 10.1109/ICMTS.1995.513962 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Reliability evaluation of thin gate oxide using a flat capacitor test structure M. Katsumata, J. Mitsuhashi, K. Kobayashi, Y. Mashiko, H. Koyama ULSI Laboratory Evaluation & Analysis Center, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1995.513954 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Electrical gate length measurement test structure for short channel MOSFET characteristics evaluation N. Kasai, I. Yamamoto, K. Koyama ULSI Device Development Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.1995.513942 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | The Wheatstone bridge as an alignment test structure U. Kaempf Hewlett-Packard SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1995.513940 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | A capacitance method to determine the metallurgical gate-to-source/drain overlap length of submicron LDD MOSFETs Myung-Suk Jo, Jin-Hyoung Kim1, Sung-Ki Kim1, Han-Sub Yoon1, Dai-Hoon Lee1 Department of Electronic Engineering, Kangnung National University, Kangwon, South Korea 1Semiconductor Research and Development Laboratories, Hyundai Electronics Industries Company Limited, Ichon, Kyonggi, South Korea DOI: 10.1109/ICMTS.1995.513963 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Leak current characterization in high frequency operation of CMOS circuits fabricated on SOI substrate H. Ito, K. Asada Department of Electronic Engineering, University of Tokyo, Hongo, Tokyo, Japan DOI: 10.1109/ICMTS.1995.513947 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Statistical modeling tools, methods and applications for integrated circuit manufacturability F. Iravani, M. Habu, E. Khalily Hewlett Packard Company, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1995.513973 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Precise measurement of P-N junction leakage current generated in Si subsurface M. Horikawa, T. Mizutani1, K. Noda, T. Kitano ULSI Device Development Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan 1Microelectronics Research Laboratories, NEC Corporation Limited, Tsukuba, Ibaraki, Japan DOI: 10.1109/ICMTS.1995.513956 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | | A new technique for measuring threshold voltage distribution in flash EEPROM devices T. Himeno, N. Matsukawa, H. Hazama, K. Sakui, M. Oshikiri, K. Masuda, K. Kanda, Y. Itoh, J. Miyamoto Semiconductor Device Engineering Laboratory, Toshiba Corporation, Japan DOI: 10.1109/ICMTS.1995.513988 HOVER FOR ABSTRACT | PDF Xplore |
| 1995 | Resistance modeling of test structures for accurate fault detection in backend process steps using a digital tester C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1995.513985 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Influence of short circuits on data of contact and via open circuits determined by a novel weave test structure C. Hess, L. H. Weiland Institute fo Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1995.513937 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Defect parameter extraction in backend process steps using a multilayer checkerboard test structure C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1995.513944 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Measurement of contact resistance distribution using a 4k contacts array T. Hamamoto, T. Ozaki, M. Aoki1, Y. Ishibashi2 Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP 1ULSI Res. Center, Toshiba Corp., Kawasaki, Japan 2ULSI Research Center, Toshiba Corporation, Kawasaki, Japan DOI: 10.1109/ICMTS.1995.513945 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Wafer-level electromigration tests on NIST and SWEAT structures F. Giroux, C. Gounelle, P. Mortini1, G. Ghibaudo2 Central Research and Development, SGS-Thomson Microelectronics, France 1Central R&D, SGS-Thomson Microelectron., Crolles, France 2LPCS-ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1995.513978 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Efficient extraction of metal parasitic capacitances G. J. Gaston, I. G. Daniels GEC Plessey Semiconductors Limited, Plymouth, UK DOI: 10.1109/ICMTS.1995.513964 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | A new extraction method for unit bipolar junction transistor capacitance parameters N. Gambetta, B. Cialdella, D. Celi, M. Depey1 SGS THOMSON Microelectronics, Central Research and Development Laboratory, France 1LPCS-ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1995.513965 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | An in-process monitoring method for electromigration resistance of multilayered metal interconnects T. Fujii, T. Itoh, H. Ishizuka, K. Okuyama, K. Kubota Semiconductor and Integrated Circuit Div, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1995.513951 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | An electrical test structure to evaluate linewidth variations due to proximity effects in optical lithography M. Fallon, J. T. M. Stevenson, A. Walton, A. M. Gundlach1 Edinburgh Microfabrication Facility Department of Electrical Engineerin, University of Edinburgh, Edinburgh, UK 1Dept. of Electr. Eng., Edinburgh Univ., UK DOI: 10.1109/ICMTS.1995.513941 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Soft error immunity of 1-Volt CMOS memory cells with MTCMOS technology T. Douseki, S. Mutoh, T. Ueki, J. Yamada NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1995.513955 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | An efficient method to predict drain current dispersion in MOS transistors from technological parameters fluctuations M. Conti, S. Orcioni, C. Turchetti, P. L. Bellutti1, M. Zen1, N. Zorzi1, G. Soncini2 Department of Electronics, University of Ancona, Ancona, Italy 1Microelectronics Division, IRST, Trento, Italy 2Department of Materials Engineering, University of Trento, Trento, Italy DOI: 10.1109/ICMTS.1995.513974 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Depth measurements using alpha particles and upsetable SRAMs M. G. Buehler, M. Reier, G. A. Soli Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1995.513983 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Mismatch characterization of small size MOS transistors J. Bastos, M. Steyaert, R. Roovers, P. Kinget, W. Sansen, B. Graindourze1, A. Pergoot1, E. Janssens1 Department of Electrical Engineering,ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee, Belgium 1Alcatel Mietec, Oudenaarde, Belgium DOI: 10.1109/ICMTS.1995.513986 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Use of SPIDER for the identification and analysis of process induced damage in 0.35 µm transistors P. Aum, Xiaoyu Li1, V. Prabhakar1, T. Brozek1, C. R. Viswanathan1 SEMATECH, Austin, TX, USA 1Electrical Engineering Department,School of Medicine, University of California, Los Angeles, Los Angeles, CA, USA DOI: 10.1109/ICMTS.1995.513935 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | Modified transmission line pulse system and transistor test structures for the study of ESD R. A. Ashton AT&T Bell Laboratories Engineering Research Center, Orlando, FL, USA DOI: 10.1109/ICMTS.1995.513959 HOVER FOR ABSTRACT | PDF Xplore | |
| 1995 | A new characterization of sub-µm parallel multilevel interconnects and its experimental verification K. Aoyama, K. Ise1, H. Sato, K. Tsuneno, H. Masuda Hitachi and Limited, Imai, Tokyo, Japan 1Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1995.513946 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Test structures for determining design rules for microelectromechanical-based sensors and actuators C. Zincke, M. Gaitan1, M. E. Zaghloul, L. W. Linholm1 School of Engineering and Applied Science, George Washington University, WA, USA 1Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1994.303505 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Reliability analysis of gate oxide using bi-Poisson model to evaluate the crystal defect effect J. Yugami, M. Ohkura Central Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan DOI: 10.1109/ICMTS.1994.303500 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Assessment of electro-static discharge robustness based on the monitoring of lattice temperature of silicon K. D. Yoo, G. H. Lim, J. H. Jin, K. H. Choi Samsung Electronics, Semiconductor R&D, Micro Process Development, Kyunggi, South Korea DOI: 10.1109/ICMTS.1994.303474 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Automatic in-line to end-of-line defect correlation using FSRAM test structure for quick killer defect identification D. Wilson, A. J. Walton1 Kelvin Industrial Estate East Kilbride, Motorola Limited, Glasgow, UK 1Department of Electrical Engineering, Edinburgh Microfabrication Facility, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1994.303484 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Error correction in high-frequency "on-wafer" measurements J. Weng School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore DOI: 10.1109/ICMTS.1994.303483 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | A modified Gaudi structure for the optimisation of the focus of wafer steppers A. J. Walton, M. Fallon, J. T. M. Stevenson, A. W. S. Ross, C. M. Reeves Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1994.303498 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Automated gated diode measurements for device characterization B. Verzi, P. Aum1 Semiconductor Test Business Unit, Hewlett-Packard U. S. Field Operations, Austin, TX, USA 1Hewlett-Packard SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1994.303487 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Design of matching test structures [IC components] H. P. Tuinhout Philips Research, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1994.303509 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Development of the test insert generating expert routine (TIGER) for BiCMOS technologies S. W. Tarasewicz, R. A. Horner1 Northern Telecom Limited, Ottawa, ONT, Canada 1Test Engineering Department, Mitel Corporation, Inc., Kanata, ONT, Canada DOI: 10.1109/ICMTS.1994.303480 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Methodology of process evaluation with wafer-mapping techniques for statistical process control T. Takeda NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1994.303497 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | | Self-stressing structures for electromigration testing to 500 MHz E. S. Snyder, D. G. Pierce, D. V. Campbell, S. E. Swanson Sandia National Laboratories, Electronics Quality Reliability Center, Albuquerque, USA DOI: 10.1109/ICMTS.1994.303502 HOVER FOR ABSTRACT | PDF Xplore |
| 1994 | Novel test structures for process development and monitoring of stack etches for high density FLASH and EPROM memories E. Shacham, G. Wolstenholme1, J. Perry, N. Narahai, A. Bergemont National Semiconductor Corporation, Santa Clara, CA, USA 1Micron Technology, Boise, ID, USA DOI: 10.1109/ICMTS.1994.303496 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | A test chip and an accurate measurement system to characterize hot hole injection in the gate oxide of p-MOSFETs L. Selmi, E. Sangiorgi, R. Bez1, B. Ricco DEIS, University of Bologna, Bologna, Italy 1SGS-Thomson, Italy DOI: 10.1109/ICMTS.1994.303501 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Series resistance and effective gate length extraction on short-channel PMOS devices at liquid nitrogen temperature F. J. Garcia Sanchez, A. Ortiz-Conde1, M. Garcia Nunez2, R. L. Anderson3 Departamento de Electrónica, Universidad Simón Bolävar, Caracas, Venezuela 1Dept. de Electron., Simon Bolivar Univ., Caracas, Venezuela 2Instituto de Ingenieria, Caracas, Venezuela 3Cryoelectronics Laboratory, University of Vermont, Burlington, VT, USA DOI: 10.1109/ICMTS.1994.303478 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | SOI device parameter investigation and extraction for VLSI radiation hardness modeling with SPICE K. O. Petrosjanc, A. S. Adonin1, I. A. Kharitonov, M. V. Sicheva Moscow University of Electronics and Mathematics, Moscow, Russia 1Scientific Research Institute Sapphire, Moscow, Russia DOI: 10.1109/ICMTS.1994.303490 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | A test structure of a MOSFET with Si-implanted gate-SiO2 for EEPROM applications T. Ohzone, T. Hori1 Department of Electronics and Infortmatics, Toyama Prefectural University, Toyama, Japan 1Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1994.303488 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Fault test structures for studying circuit performance M. A. Mitchell, T. Nguyen Solid State Electronics Center, Honeywell, Inc., Plymouth, MN, USA DOI: 10.1109/ICMTS.1994.303495 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Accurate characterization of MOSFET overlap/fringing capacitance for circuit design C. C. McAndrew, G. Zaneski1, P. A. Layman, S. G. Ayyar1 AT&T Bell Labaratories, Allentown, PA, USA 1AT and T Bell Laboratories, Allentown, PA, USA DOI: 10.1109/ICMTS.1994.303510 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Measurement and modeling of size and proximity effects in conductor linewidths U. Lieneweg, N. Zamani Center for Space Microelectronics Technology, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1994.303503 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Characterization of SOI-MOSFET with the channel conductance transient spectroscopy Gyoo-Yeong Lee Semiconductor R&D Laboratories, Hyundai Electronics Industries Company Limited, Kyunggi, South Korea DOI: 10.1109/ICMTS.1994.303506 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | A test pattern to investigate the effect of capping layers on the hot carrier induced photon spectra of MOSFETs M. Lanzoni, L. Selmi, R. Bez1, M. Manfredi2 DEIS, Università di Bologna, Bologna, Italy 1SGS-Thomson, Italy 2Department of Physics, University of Parma, Parma, Italy DOI: 10.1109/ICMTS.1994.303475 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | A global optimization of bipolar model parameters using simulated diffusion Moonho Kim, Deokro Yoon, Soongjoon Cha, Joohyun Jin, Soonkwon Lim, Kyuhyun Choi Semiconductor R&D Center, Samsung Electronics Company Limited, Bucheon, Kyunggi, South Korea DOI: 10.1109/ICMTS.1994.303513 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | SRAM-based extraction of defect characteristics J. Khare, W. Maly, S. Griep1, D. Schmitt-Landsiedel1 Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA 1Siemens AG Corporate Research and Development, Munchen, Germany DOI: 10.1109/ICMTS.1994.303494 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | New test structures for on-chip absolute and accurate measurement of capacitances in a CMOS process A. Khalkhal, P. Girard, P. Nouet Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), U. M. R. 9928 Universite Montpellier II/Cnrs, Montpellier, France DOI: 10.1109/ICMTS.1994.303489 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | A direct method to extract effective geometries and series resistances of MOS transistors P. R. Karlsson, K. O. Jeppson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1994.303479 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | A simple test structure for accurately monitoring channel doping variations in a MOSFET K. Joardar Motorola Semiconductor Products Sector, Mesa, AZ, USA DOI: 10.1109/ICMTS.1994.303499 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | A systematic test methodology for identifying defect-related failure mechanisms in an EEPROM technology D. M. Hoffstetter, M. H. Manley National Semiconductor, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1994.303492 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Modeling of test structures for efficient online defect monitoring using a digital tester C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance (Prof. Dr. D. Schmid), University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1994.303493 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Drop in process control checkerboard test structure for efficient online process characterization and defect problem debugging C. Hess, L. H. Weiland Institute of Computer Design and Fault Tolerance (Prof. Dr. D. Schmid), University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1994.303485 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Automatic process monitor generation W. Hansford The MOSIS Service Informtion Science Institute, USC, CA, USA DOI: 10.1109/ICMTS.1994.303481 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Current and temperature distribution impact on electromigration failure location in SWEAT structure F. Giroux, C. Gounelle, N. Vialle, P. Mortini, G. Ghibaudo1 Central R&D, SGS-Thomson Microelectronics, Crolles, France 1LPCS-ENSERG, Grenoble, France DOI: 10.1109/ICMTS.1994.303473 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | An automated wafermap fast test for bipolar induced breakdown in NMOS transistors G. J. Gaston, B. S. Bold, J. B. Mason GEC Plessey Semiconductors Limited, Plymouth, UK DOI: 10.1109/ICMTS.1994.303508 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Test structures for extraction of MOSFET capacitances H. Gaffur, Sukyoon Yoon Fairchild Research Center, National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1994.303511 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Sources of error in the extraction of ΔW [MOSFET models] M. Fallon, A. J. Walton Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1994.303507 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Fast and accurate on-wafer extraction of parasitic resistances in GaAs MESFET's P. Debie, L. Martens, D. De Zutter Department of Information Technology, University of Ghent, Ghent, Belgium DOI: 10.1109/ICMTS.1994.303512 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | An experimental investigation of EEPROM reliability issues using the progressional offset technique A. J. Chester, A. J. Walton, P. Tuohy1 GEC Plessey Semiconductors Limited, Plymouth, UK 1NA DOI: 10.1109/ICMTS.1994.303472 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | On-wafer high-frequency measurement improvements J. L. Carbonero, R. Joly, G. Morin, B. Cabon1 Central R&D, SGS-THOMSON Microelectronics, Crolles, France 1LEMO ENSERG LNPG-URA CNRS 833, Grenoble, France DOI: 10.1109/ICMTS.1994.303482 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Worst-case MOSFET parameter extraction for a 2 µm CMOS process K. Burke, J. A. Power1, B. Donnellan1, K. Moloney1, W. A. Lane1 Analog Devices B.V., Limerick, Ireland 1NA DOI: 10.1109/ICMTS.1994.303491 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Inverter matrix for the Clementine mission M. G. Buehler, B. R. Blaes, G. Tardio, G. A. Soli Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1994.303476 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Accuracy of channel resistance and current gain methods of Leff extraction S. S. Bhattacharya, E. R. Worley, R. A. Williams Digital Communications Division, Rockwell International Corporation, Newport Beach, CA, USA DOI: 10.1109/ICMTS.1994.303477 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Temperature-controlled wafer level Joule-heated constant-current EM tests of W/AlCuSi/W wires Y. Anata, Y. Fujisaki, M. Kawaji, H. Katto, M. Kubo Device Development Center, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1994.303486 HOVER FOR ABSTRACT | PDF Xplore | |
| 1994 | Application of the modified voltage-dividing potentiometer to overlay metrology in a CMOS/bulk process R. A. Allen, M. W. Cresswell, L. W. Linholm, J. C. Owen, C. H. Ellenwood, T. A. Hill1, J. D. Benecke1, S. R. Volk1, H. D. Stewart1 Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Silicon IC Patterning Department, Sandia National Laboratories, Albuquerque, NM, USA DOI: 10.1109/ICMTS.1994.303504 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Generic test chip formats for ASIC-oriented semiconductor process development C. Weber Silicon Process Laboratory (SPL), Hewlett-Packard Corporation, Palo Alto, CA, USA DOI: 10.1109/ICMTS.1993.292911 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Design considerations for a test structure which can be used to determine the optimum focus A. J. Walton, M. Fallon, J. T. M. Stevenson, A. W. S. Ross Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1993.292907 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Enhanced gate-controlled-diode current (EGCDC) measurement C. R. Viswanathan, J. . -T. Hsu, P. Aum1, D. Chan1 Electrical Engineering Department, University of California, Los Angeles, CA, USA 1SEMATECH, Austin, TX, USA DOI: 10.1109/ICMTS.1993.292895 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Latch-up test structures for reliability analysis of a floating well based smart power technology M. Puig Vidal, M. Bafleur1, J. Buxo1, G. Sarrabayrouse1 Diagonal 645-647, Universitat de Barcelona, Barcelona, Spain 1Laboratoire d''Automatique et d''Analyse des Systemes du C.N.R.S, Toulouse, France DOI: 10.1109/ICMTS.1993.292885 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Evaluation technique of gate oxide damage Y. Uraoka, K. Eriguchi, T. Tamaki, K. Tsuji Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1993.292878 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Metrology standards for advanced semiconductor lithography referenced to atomic spacings and geometry E. C. Teague, L. W. Linholm, M. W. Cresswell, W. B. Penzes, J. A. Kramar, F. E. Scire, J. S. Villarrubia1, J. S. Jun Precision Engineering Division and Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1993.292918 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Evaluating the graft base lateral diffusion depth of high-performance bipolar transistors by using test structures Y. Tamaki, T. Shiba, T. Kure, T. Nakamura Central Research Laboratory, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1993.292894 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | An investigation into the nonquasistatic effects in MOS devices with on-wafer S-parameter techniques R. Singh, A. Juge1, R. Joly, G. Mortin1 Central R&D, Device Modeling, SGS-Thomson Microelectronics, Grenoble, France 1SGS-Thomson Microelectron., Grenoble, France DOI: 10.1109/ICMTS.1993.292899 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Projecting oxide lifetime by a step voltage method using electric field correction (MOS VLSI) T. Shigenobu, H. Uchida, N. Hirashita VLSI Research and Development Center, Oki Electric Industry Company Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.1993.292882 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Prediction of dark currents in actual devices using new test structure K. Shibusawa, N. Murakami, T. Mori, T. Ajioka LSI Process Technology Center, OKI Electric Industry Company Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.1993.292925 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | High-voltage termination-structure design using a test chip and two-dimensional simulation R. D. Schrimpf, S. I. Kosier, B. Salik, K. F. Galloway, C. F. Wheatley1, D. J. Burton2 Electrical and Computer Engineering Department, University of Arizona Tucson, Tucson, AZ, USA 1Consultant, Drums, PA, USA 2Harris Semiconductor Company, Mountaintop, PA, USA DOI: 10.1109/ICMTS.1993.292896 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | The use of test masks in the analysis of device yields S. J. Rhodes, G. C. Day GEC Plessey Semiconductors Limited, Plymouth, UK DOI: 10.1109/ICMTS.1993.292920 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | An approach for relating model parameter variabilities to process fluctuations J. A. Power, A. Mathewson, W. A. Lane National Microelectronics Research Centre, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.1993.292892 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | VLSI device parameters extraction for radiation hardness modeling with SPICE K. O. Petrosjanc, I. A. Kharitonov Moscow Institute of Electronic Machine Building, Moscow, Russia DOI: 10.1109/ICMTS.1993.292901 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Test structure metrology of homogeneous contamination H. G. Parks, R. D. Schrimpf, R. Craigin, R. Jones1, P. Resnick1 Electrical and Computer Engineering Department, University of Arizona Tucson, Tucson, AZ, USA 1Microelectronics Development Laboratory, Sandia National Laboratories, Albuquerque, NM, USA DOI: 10.1109/ICMTS.1993.292919 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A new method for the experimental determination of the control gate and drain coupling ratios in FLOTOX EEPROM cells C. Papadas, B. Moison, G. Ghibaudo1, P. Mortini, G. Panankakis2 Central R&D, SGS-Thomson Microelectronics, Grenoble, France 1URA CNRS, ENSERG, Laboratories de Physique des Composants ä Semiconducteurs, Grenoble, France 2NA DOI: 10.1109/ICMTS.1993.292904 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | The use of test structures to identify leakage failure mechanisms in CMOS inputs J. H. Orchard-Webb Kanata, ONT, Canada DOI: 10.1109/ICMTS.1993.292884 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Photoemission characteristics of reverse-breakdown n+-diodes with LOCOS- and trench-isolation T. Ohzone, H. Iwata Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.1993.292924 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Channel-width measurements of LOCOS- and trench-isolated n-MOSFETs by photoemission T. Ohzone, H. Iwata Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.1993.292908 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A new test device for detecting very low leakage current using DRAM cell array T. Oasa, H. Inada1, M. Fujito, T. Matsumoto Advanced Research Laboratories, Sumitomo Metal Industries Limited, Amagasaki, Hyogo, Japan 1Sumitomo Metal Ind. Ltd., Hyogo, Japan DOI: 10.1109/ICMTS.1993.292879 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A test pattern for three-dimensional latch-up analysis I. De Munari, R. Menozzi, M. Davoli, F. Fantini Dipartimento di Ingegneria dell'Informazione, Università di Parma, Parma, Italy DOI: 10.1109/ICMTS.1993.292886 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A flexible test structure evaluation system for reliability data analysis M. Mori, Y. Kuriyama, N. Shiono LSI Laboratories, NTT, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1993.292921 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Junction evaluation by time dependent degradation due to high constant voltage stressing (DRAMs) J. Mitsuhashi, J. Komori, T. Eimori, H. Koyama Evaluation and Analysis Center, LSI Lab, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1993.292883 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Direct extraction of SPICE level 3 parameters without using optimization J. . -i. Matsuda LSI Division, Semiconductor Business Headquarters, Sanyo Electric Company Limited, Ora-Gun, Gunma, Japan DOI: 10.1109/ICMTS.1993.292902 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A test structure for E-beam testing J. Madrenas, J. Cabestany Departament dEnginyeria Electrbnica, UPC, UPC, Barcelona, Spain DOI: 10.1109/ICMTS.1993.292888 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | SPICE DC parameter extraction of MESFETs with diffused and grown channel A. S. Lujan, I. Chueiri, J. W. Swart, F. C. Prince, P. H. Tessari1 DSIF/FEE-Electrical Engineering and LPD/IFGW-Physics Institute,State University of Campinas, State University of Campinas-UNICAMP, Sao Paulo, Brazil 1UNICAMP, State Univ. of Campinas, Sao Paulo, Brazil DOI: 10.1109/ICMTS.1993.292927 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A direct, reliable, measurement-based technique for the extraction of an on-chip HBT dummy structure equivalent circuit K. Lu, P. Perry, T. J. Brazil Department of Electronic and Electrical Engineering, University College Dublin, Dublin, Ireland DOI: 10.1109/ICMTS.1993.292898 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A moveable shielding box adaptable to commercial automatic wafer probers M. Lozano, C. Cane, J. Santander, I. Gracia1, E. Lora-Tamayo Centre Nacional de Microelectrònica, Universitat Autonoma de Barcelona, Barcelona, Spain 1Centre Nacional de Microelectron., Univ. Auton. de Barcelona, Spain DOI: 10.1109/ICMTS.1993.292917 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | An implementation of CMOS design for testability techniques for non stuck-at faults M. Lanzoni, M. Favalli, P. Olivo, B. Ricco DEIS, University of Bologna, Bologna, Italy DOI: 10.1109/ICMTS.1993.292887 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A low frequency AC method to measure the doping profile in the channel region of a MOSFET with general extendability to the semiconductor surface J. D. Kendall, J. K. Kolk, A. R. Boothroyd1, D. A. Vincent2 Northern Telecom Limited, Ottawa, ONT, Canada 1Department of Electronics, Carleton University, Ottawa, ONT, Canada 2Northern Telecom Limited DOI: 10.1109/ICMTS.1993.292880 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A direct extraction algorithm for a submicron MOS transistor model P. R. Karlsson, K. O. Jeppson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1993.292928 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Limitations of electrical test information: a case study with polysilicon emitter contacts M. Johnson, A. J. Strojwas, D. W. Greve, R. A. Reuss1, A. Flowers2 Carnegie Mellon University, Pittsburgh, PA, USA 1Motorola, Inc., Phoenix, AZ, USA 2Texas Instrumenits, Inc., Houston, TX, USA DOI: 10.1109/ICMTS.1993.292913 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Power lateral DMOS transistor test structures S. Hidalgo, J. Fernandez, P. Godignon, J. Rebollo, J. Millan Centro Nacional de Microelectróica, Barcelona, Spain DOI: 10.1109/ICMTS.1993.292897 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Modeling of real defect outlines for defect size distribution and yield prediction C. Hess, A. Strole Institute of Computer Design and Fault Tolerance, University of Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1993.292890 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A testset for automatic characterisation of opamps in the frequency domain C. Van Grieken, W. Sansen Department Elektrotechniek, ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1993.292889 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Process windows for convenient in-process monitoring of oxide and polysilicon etches K. Golshan, H. Tigelaar, M. Harward1 Regional Technology Center and Semiconductor Process and Design Center, Texas Instruments, Inc., CA, USA 1Texas Instruments Inc., Irvine, CA, USA DOI: 10.1109/ICMTS.1993.292914 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Evaluations of leakage currents and capacitances on elementary CMOS devices P. Girard, P. Nouet, A. Khalkhal, F. M. Roche Laboratoire ÄInformatique, de Robotique et de Microelectronique de Montpellier (U.M.R. C09928 CNRS),Sciences et Techniques du Languedoc, Université de Montpellier II, Montpellier, France DOI: 10.1109/ICMTS.1993.292905 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Thermal measurements by use of a SBIMOS diode matrix B. Geeraerts, W. Van Petegem, W. Sansen Electrical Engineering ESAT/MICAS, Catholic University of Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1993.292923 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Proposal of standard characterization method for dynamic circuit performance M. Fujishima, K. Asada Department of Electronic Engineering, University of Tokyo, Tokyo, Japan DOI: 10.1109/ICMTS.1993.292915 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Characterization of SOI MOSFETs by gate capacitance measurements D. Flandre, B. Gentinne Laboratoire de Microélectronique, Louvain-la-Neuve, Belgium DOI: 10.1109/ICMTS.1993.292906 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Measurement of minimum line widths using Fallon ladders M. Fallon, A. J. Walton1 Department of Electrical Engineering, Napier University, Edinburgh, UK 1Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1993.292909 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | The use of low-level pre-tunneling currents to characterize thin oxide wearout and breakdown D. J. Dumin, J. R. Maddux, R. Subramoniam, R. S. Scott, D. . -P. Wong Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA DOI: 10.1109/ICMTS.1993.292922 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Evaluation of metallization systems with test structures and yield modeling C. A. DeLoach, H. G. Parks1, S. E. Beck2 Brooktree Corporation, San Diego, CA, USA 1H.G. Parks, ECE Bldg., University of Arizona Tucson, Tucson, AZ, USA 2Air Products and Chemicals, Inc., Allentown, PA, USA DOI: 10.1109/ICMTS.1993.292891 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | Test structure for the in-plane locations of project features with nanometer-level accuracy traceable to a coordinate measurement system M. W. Cresswell, R. A. Allen, L. W. Linholm, C. H. Ellenwood, W. B. Penzes, E. C. Teague Semiconductor Electronics Division and Precision Engineering Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1993.292910 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | An easy technique for determining diffusion and generation-recombination components of the current of pn junctions for better modelling C. Cane, M. Lozano, I. Gracia1, J. Santander, E. Lora-Tamayo Center Nacional de Microelectgrónica, Universitat Autònoma de Barcelòna, Barcelona, Spain 1Centre Nacional de Microelectron., Univ. Autonoma de Barcelona, Spain DOI: 10.1109/ICMTS.1993.292926 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A method for modeling the manufacturability of IC designs E. D. Boskin, C. J. Spanos, G. Korsh1 Department of Electrical Engineering & Computer Sciences, University of California, Berkeley, CA, USA 1ATMEL Corporation, San Jose, CA, USA DOI: 10.1109/ICMTS.1993.292912 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | SEU/SRAM as a process monitor B. R. Blaes, M. G. Buehler Jet Propulsion Laboratory, Pasadena, CA, USA DOI: 10.1109/ICMTS.1993.292893 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | | Modeling and characterization of MOSFET width dependencies R. A. Ashton, P. A. Layman1, C. C. McAndrew1 AT and T Bell Laboratories, Inc., Orlando, FL, USA 1AT and T Bell Laboratories, Inc., Allentown, PA, USA DOI: 10.1109/ICMTS.1993.292881 HOVER FOR ABSTRACT | PDF Xplore |
| 1993 | A test structure for transferring timing setup between digital IC testers L. Allodi, G. Chiorboli, G. Franco, C. Morandi, F. Venturi Dipartimento di Ingegneria dell' Informazione, Università di Parma, Parma, Italy DOI: 10.1109/ICMTS.1993.292916 HOVER FOR ABSTRACT | PDF Xplore | |
| 1993 | A methodology for pre-determination of bipolar SPICE model parameters in BiCMOS technology S. Aggarwal, A. Juge SGS-Thomson Microelectronics, Central Research and Development, Device Modeling, Grenoble, France DOI: 10.1109/ICMTS.1993.292900 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Capacitor insulator reliability prediction using three-dimensional test chips for submicron DRAMS J. Yugami, T. Mine, S. Iijima, A. Hiraiwa Central Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan DOI: 10.1109/ICMTS.1992.185924 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | A new method for electrically measuring thin-film thickness of SOI MOSFETs H. Yamazaki, S. Ando, H. Horie, S. Hijiya Fujitsu Laboratories Limited, Atsugi, Japan DOI: 10.1109/ICMTS.1992.185953 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | VLSI interconnect linewidth variation: a method to characterize depth of focus and proximity effects P. J. Wright, E. Burke, A. T. Appel Semiconductor Process and Design Center, Texas Instruments, Inc., Dallas, TX, USA DOI: 10.1109/ICMTS.1992.185966 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Measurement and parameter extraction of submicron VLSI MOSFET test structures C. S. Wen, M. Guldahl, L. P. Sadwick, R. Kent1, H. Gaffur2 Department of Electrical Engineering, University of Utah, Salt Lake, UT, USA 1Intel Corporation, Albuquerque, NM, USA 2National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1992.185969 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | The use of a digital multiplexer to reduce process control chip pad count D. Ward, A. J. Walton1, W. G. Gammie1, R. J. Holwill1 Philips Semiconductors, Southampton, UK 1Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1992.185954 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Test structures for analysis and parameter extraction of secondary photon-induced leakage currents in CMOS DRAM technology S. H. Voldman IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1992.185932 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | | New failure analysis technique of ULSIs using photon emission method Y. Uraoka, T. Maeda, I. Miyanaga, K. Tsuji Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1992.185947 HOVER FOR ABSTRACT | PDF Xplore |
| 1992 | Life time evaluation of MOSFET in ULSIs using photon emission method N. Tsutsu, Y. Uraoka, T. Morii, K. Tsuji Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1992.185946 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Suppression of measurement errors in effective-MOSFET-channel-length extraction K. Terada Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Japan DOI: 10.1109/ICMTS.1992.185971 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | The design, fabrication and measurement of asymmetrical LDD transistors R. C. Smith, A. J. Walton Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1992.185948 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Test structure and experimental analysis of bipolar hot-carrier degradation including stress field effect H. Shimamoto, M. Tanabe, T. Onai1, K. Washio1, T. Nakamura1 Musashino Office, Hitachi Device Engineering Company Limited, Kokubunji, Tokyo, Japan 1Central Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan DOI: 10.1109/ICMTS.1992.185949 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | A study of clustering using microelectronic defect monitors A. V. S. Satya East Fishkill Facility, IBM, Corporation, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.1992.185934 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | An investigation of MOSFET statistical and temperature effects J. A. Power, R. Clancy, W. A. Wall, A. Mathewson, W. A. Lane National Microelectronics Research Centre, University College Cork, Cork, Ireland DOI: 10.1109/ICMTS.1992.185970 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Dependence of SPICE Level 3 model parameters with transistor size C. Perello, M. Lozano, C. Cane, E. LoraTamayo1 Centre Nacional de Microelectrónica, Universitat Autònoma Barcelona, Barcelona, Spain 1Centre Nacional de Microelectron., Univ. Au,tonoma de Barcelona, Spain DOI: 10.1109/ICMTS.1992.185943 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | A new and simple test structure for evaluating the sectional photo-sensitivity distribution of pixels in a frame-transfer CCD image sensor M. Okigawa Semiconductor Business Headquarters LSI Division, Sanyo Electric Company Limited, Gifu, Japan DOI: 10.1109/ICMTS.1992.185955 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Two-dimensional current/voltage measurements of reverse-biased n+-diodes by photoemission T. Ohzone, H. Iwata Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.1992.185931 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Three-dimensional effects of latchup turn-on CMOS and forward-biased n+-diode measured by photoemission T. Ohzone, H. Iwata Department of Electronics and Informatics, Toyama Prefectural University, Imizu, Toyama, Japan DOI: 10.1109/ICMTS.1992.185951 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Effective channel length determination using punchthrough voltage S. Nakanishi, M. Hoijer, Y. Saitoh, Y. Katoh, Y. Kojima, M. Kamiya IC Device 1G Semiconductor division, Seiko Instruments, Inc., Matsudo, Chiba, Japan DOI: 10.1109/ICMTS.1992.185941 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Issues with contact defect test structures M. A. Mitchell, J. Huang, L. Forner1 Solid State Electronics Center, Honeywell, Inc., Plymouth, MN, USA 1Honeywell Inc., Plymouth, MN, USA DOI: 10.1109/ICMTS.1992.185936 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | A simple method to measure very low currents to evaluate the effect of damage caused by contact formation near the isolation edges in high-density LSIs J. Matsuda, Y. Oba Semiconductor Business Headquarters Research and Development Center, Sanyo Electric Company Limited, Ora-gun, Gunma, Japan DOI: 10.1109/ICMTS.1992.185930 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Yield test structures and their use for process development S. Magdo General Technology Division, IBM, Corporation, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.1992.185935 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Extracting contact misalignment from 4- and 6-terminal contact resistors U. Lieneweg, H. R. Sayah Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1992.185967 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | A new method and test structure for easy determination of femto-farad on-chip capacitances in a MOS process B. Laquai, H. Richter, B. Hofflinger Institute for Microelectronics, Stuttgart, Stuttgart, Germany DOI: 10.1109/ICMTS.1992.185939 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Accurate determination of CMOS capacitance parameters using multilayer structures W. de Lange Advanced Processor Division, Palo Alto, CA, USA DOI: 10.1109/ICMTS.1992.185938 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | A high-speed TEG evaluation system integrating parallel/continuous processing software and high-speed hardware K. Kubota, T. Takeda, T. Sakurai NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1992.185958 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | An analytical strategy for fast extraction of MOS transistor DC parameters applied to the SPICE M)53 and BSIM models P. R. Karlsson, K. O. Jeppson Department of Solid State Electronics, Chalmers University of Technology, Goteborg, Sweden DOI: 10.1109/ICMTS.1992.185942 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Inverse modeling for doping profile extraction in the presence of interface traps K. Iniewski Department of Electrical Engineering, University of Toronto, Toronto, ONT, Canada DOI: 10.1109/ICMTS.1992.185940 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Carrier transport test structure for characterization of poly/monosilicon interfaces B. Hu, N. H. Berger, A. Gauckler, B. Muller Institute of Microelectronics, Technical University Berlin, Berlin, Germany DOI: 10.1109/ICMTS.1992.185952 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Test structure for the detection, localization and identification of short circuits with a high speed digital tester C. Hess, L. H. Weiland Institut für Rechnerentwurf und Fehlertoleranz, Universitat di Karlsruhe, Karlsruhe, Germany DOI: 10.1109/ICMTS.1992.185956 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | An optical measurement method for PN junction depth Yie He, Yafa Shen1 Microelectronics Center, South-East University, Nanjing, China 1Microelectron. Center, Southeast Univ., Nanjing, China DOI: 10.1109/ICMTS.1992.185961 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Critical dimension measurements by electron and optical beams for the establishment of linewidth standards T. Hatsuzawa, K. Toyoda National Research Laboratory of Metrology, M.I.T.I., Tsukuba, Japan DOI: 10.1109/ICMTS.1992.185965 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Test structures and measurement techniques for the characterization of the dynamic behaviour of CMOS transistors on wafer in the GHz range J. Hanseler, H. Schinagel, H. L. Zapf Semiconductor Group, CAD Department, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1992.185944 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Test structures for ISFET chemical sensors I. Gracia, C. Cane, M. Lozano, J. Esteve Centre Nacional de Microelectrònica, Universitat Autònoma Barcelona, Bellaterra, Spain DOI: 10.1109/ICMTS.1992.185959 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | A note on designing a comprehensive scanning electron microscopy test structure (for VLSI) K. Golshan, M. Harward, H. Tigelaar Regional Technology Center and Semiconductor Process and Design Center, Texas Instruments, Inc., Irvine, CA, USA DOI: 10.1109/ICMTS.1992.185962 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | A novel test structure for monitoring technological mismatches in DRAM processes H. Geib, W. Weber, E. Wohlrab, L. Risch Munich, Germany DOI: 10.1109/ICMTS.1992.185929 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Finite element analysis of a SWEAT structure with a 3-D, nonlinear, coupled thermal-electric model M. J. Dion Sematech Inc., Austin, TX, USA DOI: 10.1109/ICMTS.1992.185926 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | Automatic test chip and test program generation: an approach to parametric test computer-aided design T. Ternisien d'Ouville, J. P. Jeanne, J. L. Leclercq, D. Caloud1, L. Zangara1 France Télécom CNET, Meylan, France 1Dolphin Integration, Meylan, France DOI: 10.1109/ICMTS.1992.185957 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | CMOS-ASIC life-predictions from test-coupon data M. G. Buehler, N. Zamani, J. A. Zoutendyk Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1992.185925 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | A modular 0.7 μm CMOS JESSI test chip for multi purpose applications T. Brenner, N. Maene1, S. Lindenkreuz2, J. le Ber3, H. Richter4, E. Janssens5, G. Morin6, J. Hanseler7 Alcatel Sel Research Center, Stuttgart, Germany 1Alcatel Bell, Belgium 2Robert Bosch GmbH, Germany 3Bull S.A., France 4NA 5Mietec, Belgium 6SGS-Thomson, France 7Siemens AG, Germany DOI: 10.1109/ICMTS.1992.185960 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | A new latch-up test structure for practical design methodology for internal circuits in the standard cell-based CMOS/BiCMOS LSIs T. Aoki NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1992.185927 HOVER FOR ABSTRACT | PDF Xplore | |
| 1992 | | Voltage-dividing potentiometer enhancements for high-precision feature placement metrology R. A. Allen, M. W. Cresswell, C. H. Ellenwood, L. W. Linholm National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1992.185964 HOVER FOR ABSTRACT | PDF Xplore |
| 1990 | Edge effect prediction in real MOS insulator using test chips J. Yugami, A. Hiraiwa Central Research Laboratory, Hitachi and Limited, Tokyo, Japan DOI: 10.1109/ICMTS.1990.161706 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Fully-automated line-width measurement system and its applications M. Yoshizawa, K. Wada NTT LSI Laboratories, Japan DOI: 10.1109/ICMTS.1990.161727 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Progress on model building and statistical analysis methodology of IC characteristics with process He Yie, Yao Jiannan Microelectronics Center, South-East University, Nanjing, Jiangsu, China DOI: 10.1109/ICMTS.1990.161739 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Standardization of test structure design C. Weber Circuit Technology Research and Development (CT Research and Development), Hewlett Packard Company, Palo Alto, CA, USA DOI: 10.1109/ICMTS.1990.161730 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A new method to determine effective channel widths of MOS transistors for VLSI device design C. . -P. Wan, H. Yang, B. J. Sheu Department of Electrical Engineenng/Electrophysics, University of Southern California, Los Angeles, CA, USA DOI: 10.1109/ICMTS.1990.67906 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A novel approach for reducing the area occupied by contact pads on process control chips A. J. Walton, W. Gammie, D. Morrow, J. T. M. Stevenson, R. J. Holwill Edinburgh Micro fabrication Facility Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1990.67883 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A methodology for evaluating the area of contacts to improve the accuracy of contact resistance measurements A. J. Walton, M. Fallon, J. T. M. Stevenson, A. Ross, R. J. Holwill Department of Electrical Engineering, Edinburgh Micro fabrication Facility, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1990.161707 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | The application of AI techniques to the control and interpretation of C-V measurements J. A. Walls, A. J. Walton, J. M. Robertson Department of Electrical Engineering, Edinburgh Microfabrication Facility, Edinburgh, UK DOI: 10.1109/ICMTS.1990.67904 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A parallel measurement system for the extraction of level 3 SPICE parameters A. A. Walker, P. Touhy, A. J. Walton, J. M. Robertson Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1990.67893 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Study of electromigration at interconnect vias T. Wada, I. Matsuo1, T. Umemoto2 Semiconductor Group, Matsushita Electronics Corporation, Nagaokakyo, Kyoto, Japan 1Quality Laboratory, Kyoto Research Laboratory, Matsushita Electronics Corporation, Nagaokakyo, Kyoto, Japan 2Matsushita Electron. Corp., Kyoto, Japan DOI: 10.1109/ICMTS.1990.161752 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Dependence of dielectric time to breakdown distributions on test structure area R. . -P. Vollertsen, W. G. Kleppmann Components Group, Semiconductor Division, Reliability Engineering, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1990.161716 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Trench DRAM structures for the analysis of two- and three-dimensional leakage phenomena S. H. Voldman IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1990.161720 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | TLM: a trench leakage monitor for a four megabit DRAM technology S. H. Voldman, C. W. Long IBM General Technology Division, IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1990.67910 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Material and process learning by noncontact characterization of minority carrier lifetime and surface recombination condition A. Usami Department of Electrical and Computer Engineering, Nagoya Institute of Technology, Nagoya, Japan DOI: 10.1109/ICMTS.1990.161704 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Evaluation of gate oxide reliability using luminescence method Y. Uraoka, H. Yoshikawa, N. Tsutsu, S. Akiyama Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1990.161715 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Lateral spread of high energy implanted ions studied by electronic test structures T. Ueda, H. Aoki, Y. Kinoshita, S. Wada, H. Miyatake, J. Kudo, T. Ashida1 VLSI Development Laboratories, Sharp Corporation, Tenri, Nara, Japan 1Sharp Corp., Nara, Japan DOI: 10.1109/ICMTS.1990.161737 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | An ovenless electromigration test system environment using test chips with on-chip heating and computer controlled testing V. C. Tyree USC Information Sciences Institute, Marina del Rey, CA, USA DOI: 10.1109/ICMTS.1990.161751 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | New detection method of hot-carrier degradation using photon spectrum analysis of weak luminescence on CMOS VLSI N. Tsutsu, Y. Uraoka, Y. Nakata, S. Akiyama, H. Esaki VLSI Technology Research Laboratory, Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1990.67894 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Sources of error in electrical measurements of dimensional offset and sheet resistance in the near- and sub-micron region J. Trager Semiconductor Group 1Technology, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1990.67887 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | An MOS test device with the gate electrode emphasized for dielectric breakdown Y. Tatewaki, K. Matsuda, K. Tanaka, K. Nishizawa, K. Sakiyama Integrated Circuit (Ic) Group Development Department 2, Sharp Corporation, Nara, Japan DOI: 10.1109/ICMTS.1990.161711 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A new effective channel length determination method for LDD MOSFETs K. Takeuchi, N. Kasai, K. Terada ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161744 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Reducing fabrication variability in analog IC technology by the statistical error propagation method using simple test structures S. L. Sundaram, A. C. Carlson1 Motorola Inc., Mesa, AZ, USA 1Analog Integrated Circuits Division, Motorola, Inc., Mesa, AZ, USA DOI: 10.1109/ICMTS.1990.67903 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A technique for measuring threshold mismatch in DRAM sense amplifier devices E. J. Sprogis IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1990.161721 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Gate chain structures with on-chip clock generators for realistic high-speed dynamic stress N. Shiono, T. Mizusawa NTT LSI Laboratories, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161755 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A novel circular structure for the extraction of the contact resistivity-application to the Pd2Si/n+Si, TiN/Ti/n+Si and TiN/Ti/p+Si interfaces A. Scorzoni, M. Vanzi1, C. Caprile2 CNR Istituto LAMEL, Bologna, Italy 1TELETTRA S.P.A, Bologna, Italy 2STMicroelectronics, Agrate-Brianza, Italy DOI: 10.1109/ICMTS.1990.67909 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Linewidth and step resistance distribution measurements using an addressable array H. Sayah, M. Buehler Jet Propulsion Laboratory, MS 3-329, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1990.67885 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Yield measurement tests sites A. V. S. Satya East Fishkill Facility, IBM, Corporation, Hopewell Junction, NY, USA DOI: 10.1109/ICMTS.1990.161728 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A wafer scale fail bit analysis system for VLSI memory yield improvement Y. Sakai, J. Sawada, W. Sakamoto, J. Murato1, H. Kawamoto, K. Sakai2, K. Nakamuta3 Device Development Center, Hitachi and Limited, Ome, Tokyo, Japan 1Hitachi Ltd., Tokyo, Japan 2Hitachi VLSI Engineering Corporation Limited, Tokyo, Japan 3NA DOI: 10.1109/ICMTS.1990.67899 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Reliability of latchup characterization procedures W. Reczek, F. Bonner, B. Murphy Components Group, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1990.67879 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Novel test structures for the investigation of the efficiency of guard rings used for I/O-latch-up prevention J. Quincke HL CAD 33, Siemens AG, Munchen, Germany DOI: 10.1109/ICMTS.1990.67876 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | MOSFET statistical parameter extraction using multivariate statistics J. A. Power, A. Mathewson, W. A. Lane National Microelectronics Research Centre, Cork, Ireland DOI: 10.1109/ICMTS.1990.161743 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Enhanced SPICE MOSFET model for analog applications including parameter extraction schemes J. A. Power, W. A. Lane National Microelectronics Research Center, Cork, Ireland DOI: 10.1109/ICMTS.1990.67892 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Test structures and finite element models for chip stress and plastic package reliability R. Pendse, J. Demmin National Semiconductor Corporation, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1990.67896 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Full and automated determination of MOS transistor parameters in the linear region J. L. Pelloie Letyirdi-Commissariat A L'energie Atomique Cenlg-85x, Letyirdi-Commissariat A L'energie Atomique Cenlg-85x, Grenoble, France DOI: 10.1109/ICMTS.1990.67891 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Yield modeling from SRAM failure analysis H. G. Parks General Electric Company, Corporate Research and Development, Schenectady, NY, USA DOI: 10.1109/ICMTS.1990.67898 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Measurement of minority carrier transport parameters in heavily doped shallow implanted layers Y. Pan, M. Kleefstra Department of Electrical Engineering, Electrical Materials Laboratory, Delft University of Technnology, Delft, Netherlands DOI: 10.1109/ICMTS.1990.67873 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Array diagnostic monitor-a DRAM technology development vehicle M. Paggi, E. Sprogis, G. Richard, R. E. Newhart IBM General Technology Division, IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1990.67897 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Electrical characterization of 2-D doping profiles G. J. L. Ouwerling, J. C. Staalenburg1, M. Kleefstra1 Philips Research Laboratories, Eindhoven, Netherlands 1Electrical Materials Laboratory, Delft University of Technnology, Delft, Netherlands DOI: 10.1109/ICMTS.1990.67871 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A new structure for measuring the thermal conductivity of integrated circuit dielectrics J. H. Orchard-Webb Mitel Semiconductor Limited, Kanata, ONT, Canada DOI: 10.1109/ICMTS.1990.161710 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Novel test structures for the characterization of latch-up tolerance in a bipolar and MOSFET merged device H. Momose, T. Maeda, K. Inoue1, Y. Urakawa, K. Maeguchi Semiconductor Device Engineering Laboratory, Toshiba Corporation, Japan 1Semiconductor Division, Toshiba Corporation, Kawasaki, Japan DOI: 10.1109/ICMTS.1990.161747 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A crossbridge for measurement of gate-limited source/drain diffusion M. A. Mitchell, C. Figura, L. Forner Solid State Electronics Center, Honeywell, Inc., Plymouth, MN, USA DOI: 10.1109/ICMTS.1990.67886 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A technique for characterizing AC performance with a DC parametric tester R. Merrill, E. Issaq, E. Gomersall1 National Semiconductor Fairchild Research Center, Santa Clara, CA, USA 1Nat. Semicond. Fairchild Res. Center, Santa Clara, CA, USA DOI: 10.1109/ICMTS.1990.67908 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A new set of electrical test structures for simultaneous single-wafer monitoring of ion implant shadowing, channeling, and dose uniformity A. M. McCarthy, W. Lukaszek Center for Integrated Systems, University of Stanford, Stanford, CA, USA DOI: 10.1109/ICMTS.1990.161733 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A new bipolar extraction tool for wide range of device behaviours E. Mazaleyrat, D. Celi, A. Juge, B. Cialdella Central Research and Development, SGS-Thomson Microelectronics, Grenoble, France DOI: 10.1109/ICMTS.1990.161741 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | | Investigation of self-heating in VLSI and ULSI MOSFETs P. G. Mautry, J. Trager Semiconductor Group, Technology, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1990.67907 HOVER FOR ABSTRACT | PDF Xplore |
| 1990 | Improvement of the triangular MOS transistor for misalignment measurement M. Lozano, C. Cane, C. Perello, J. Anguita, E. Lora-Tamayo Centro Nacional de Microelectrónica, Universidad Autónoma de Barcelona, Barcelona, Spain DOI: 10.1109/ICMTS.1990.161724 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Test structure for characterization of polycrystalline silicon as a diffusion source for advanced devices B. Lojek, B. Vasquez Advanced Technology Center, Motorola, Inc., Mesa, AZ, USA DOI: 10.1109/ICMTS.1990.67888 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Flange correction to four-terminal contact resistance measurements U. Lieneweg, D. J. Hannaman Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1990.67875 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Novel test structure for the measurement of electrostatic discharge pulses H. Lendenmann, R. D. Schrimpf, A. D. Bridges1 Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA 1AT&T, Microelectronics, Allentown, PA DOI: 10.1109/ICMTS.1990.67895 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | X-ray exposure mask accuracy evaluation using electrical test structures Y. Kuroki, S. Hasegawa, T. Honda, Y. Iida Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161725 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Novel measurement technique for trapped charge centroid in gate insulator (of DRAM) J. Kumagai, S. Sawada, K. Toita Semiconductor Device Engineering Laboratory, Toshiba Corporation, Kawasaki, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161718 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Measurement of lateral diffusion profiles for submicrometer MOSFETs K. Kubota, Y. Kawashima, S. Yoshida, M. Ishida Semiconductor Design & Development Center, Hitachi and Limited, Kodaira, Tokyo, Japan DOI: 10.1109/ICMTS.1990.161734 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A practical method for extracting impurity profiles and effective mobilities of MOSFET's with nonuniform channel doping K. Kubota, Y. Kawashima1, Y. Ohkura2, M. Nagao Semiconductor Design & Development Center, Hitachi and Limited, Tokyo, Japan 1Hitachi Microcomputer Engineering Company Limited, Tokyo, Japan 2TtCentral Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan DOI: 10.1109/ICMTS.1990.67872 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Semiconductor device parameter extraction based on reconfigurable ring oscillator frequency measurements F. Kovacs, G. Hosszu Department of Electronic Devices, Technical University of budapest, Budapest, Hungary DOI: 10.1109/ICMTS.1990.161745 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | | On-chip quasi-static floating-gate capacitance measurement method C. Kortekaas Device and Process Characterization Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1990.67889 HOVER FOR ABSTRACT | PDF Xplore |
| 1990 | A fast testing of electromigration immunity using noise measurement technique J. Komori, Y. Takata, J. Mitsuhashi, N. Tsubouchi LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan DOI: 10.1109/ICMTS.1990.161753 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Novel test structure to study junction leakage current N. Koike, K. Tominaga Kyoto Research Laboratory Yatsushita Electronics Corporation, Japan DOI: 10.1109/ICMTS.1990.67905 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A hot carrier parallel testing technique to give a reliable extrapolation N. Koike, M. Ito1, H. Kuriyama2 Kyoto Research Laboratory, Matsushita Electronics Corporation, Kyoto, Japan 1Memory Division, Matsushita Electronics Corporation, Kyoto, Japan 2Kyoto Research Laboratory and Memory Division, Matsushita Electronics Corporation, Kyoto, Japan DOI: 10.1109/ICMTS.1990.161749 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Self-multiplexing force-sense test structures for (MOS) IC applications K. L. M. van der Klauw, J. J. M. Joosten, L. A. Wall1 Device and Process Characterization Group, Philips Research Laboratories, Eindhoven, Netherlands 1National Microelectronics Research Centre, University College, Cork, Ireland DOI: 10.1109/ICMTS.1990.67884 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Using spatial information to analyze correlations between test structure data J. K. Kibarian, A. J. Strojwas Department of Electrical and Computer Engineering, Camegie Mellon University, Pittsburgh, PA, USA DOI: 10.1109/ICMTS.1990.67901 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Knowledge verification of machine-learning procedures based on test structure measurements D. Khera, L. W. Linholm, R. A. Allen, M. W. Cresswell, V. C. Tyree1, W. Hansford1, C. Pina1 Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1The MOSIS Service, USC Information Sciences Institute, Marina del Rey, CA, USA DOI: 10.1109/ICMTS.1990.161729 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Direct extraction of accurate DC bipolar parameters for the forward active region without using optimization J. Kendall Northern Telecom Electronics Limited, Nepean, ONT, Canada DOI: 10.1109/ICMTS.1990.161740 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Test structure for determining boron diffusion coefficient in tungsten silicide Y. Kataoka, K. Suzuki, H. Horie, Y. Yamashita, N. Nakayama, T. Kitakohji Fujitsu Laboratories Limited, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161736 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Test chip for the evaluation of surface-diffusion phenomena in sputtered aluminum planarization processes M. A. Jones, J. A. Roberts, C. H. Ellenwood1, M. W. Cresswell1, R. A. Allen1 Semiconductor Equipment Division, Eaton Corporation, Beverly, MA, USA 1National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1990.161709 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | The vertical test structure for measuring contact resistance between two kinds of metal S. Ido, M. Imai, T. Kumise, M. Satoh, H. Horir1, S. Ando2 Fujitsu Laboratories Limited, Atsugi, Kanagawa, Japan 1Fujitsu Labs. Ltd., Atsugi, Japan 2Submicron Development Center, Fujitsu Laboratories Limited, Atsugi, Kanagawa, Japan DOI: 10.1109/ICMTS.1990.161708 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A new extraction method for effective channel length on lightly doped drain MOSFET's J. Ida, A. Kita, F. Ichikawa VLSI R&D Center, OKI Electric Industry Company Limited, Hachioji, Japan DOI: 10.1109/ICMTS.1990.67890 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A measurement technique for analyzing bitline mode soft errors in half-micron design DRAMs N. Higaki, S. Ando, M. Taguchi Fujitsu Laboratories Limited, Atsugi, Japan DOI: 10.1109/ICMTS.1990.67900 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | The inverter matrix: a vehicle for assessing process quality through inverter parameter analysis of variance D. J. Hannaman, M. G. Buehler1, J. Chang1, H. R. Sayah1 Silicon Systems, Inc., Tustin, CA, USA 1Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1990.161722 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Fault chip defect characterization for wafer scale integration D. J. Hannaman, H. R. Sayah, R. A. Allen, M. G. Buehler, M. Yung1 Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA 1Hughes Research Laboratory, Malibu, CA, USA DOI: 10.1109/ICMTS.1990.67882 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Transmission line model test structure with four or more terminals: a novel method to characterize non-ideal planar ohmic contacts in presence of inhomogeneities L. Gutai Philips R&D Center for IC Technology, Sunnyvale, Philips Components-Signetics Company, Sunnyvale, CA, USA DOI: 10.1109/ICMTS.1990.67874 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Defect size distribution in VLSI chips R. Glang IBM Corp., Manassas, VA, USA DOI: 10.1109/ICMTS.1990.67880 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Simple evaluation of very low currents in process characterization P. Girard, P. Nouet, F. M. Roche Laboratoire dE28099Automatique et de Microelectronique de Montpellier (U.R.A. W3710 CNRS), Université de Montpellier II, Montpellier, France DOI: 10.1109/ICMTS.1990.161719 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Examination of LOCOS process parameters and the measurement of effective width M. Fallon, J. M. Robertson, A. J. Walton, R. J. Holwill Edinburgh Micro fabrication Facility Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1990.161731 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Test structures to investigate thin insulator dielectric wearout and breakdown D. J. Dumin, N. B. Heilemann, N. Husain Center for Semiconductor Device Reliability Research, Department of Electrical and Computer Engineering, Clemson University, Clemson, SC, USA DOI: 10.1109/ICMTS.1990.161714 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Extraction of the interfacial generation velocity in MOSFETs J. Dugas, R. Jerisian, J. Oualid1, D. Labrunye2, J. M. Mirabel3 Laboratolre des Matériaux et Composants Semi-Conducteurs de I'Ecoie Nationale Supérieure de Physique de Marseille, Domine Universitaire de Saint-Jérôme, Marseilles, France 1Laboratoire des Matériaux et Composants Semi-Conducteurs de I'Ecole Nationale Supérieure de Physique de Marseille, Domine Universitaire de Saint-Jérôme, Marseilles, France 2Central Research and Development DAIS, Rousset, France 3Rousset, France DOI: 10.1109/ICMTS.1990.161705 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Analysis of process-induced charges created in MOSFETs and related collection test structures P. Dars, R. Basset, G. Merckel CNS, CNET, Meylan, France DOI: 10.1109/ICMTS.1990.161712 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Test structure data classification using a directed graph approach M. W. Cresswell, D. Khera, L. W. Linholm, C. E. Schuster IC Technology Group, Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1990.67902 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A modified sliding wire potentiometer test structure for mapping nanometer-level distances M. W. Cresswell, M. Gaitan, R. A. Allen, L. W. Linholm National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1990.161726 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Photoemission identification of emitter resistance for CMOS latch-up hysteresis Ming-Jer Chen, Jeng-Kuo Jeng1, Ping-Nan Tseng2, Nun-Sian Tsai2, Ching-Yuan Wu Institute of Electronics, National Chiao Tung University, Taipei, Taiwan 1Industrial Technology Research Institute (ITRI), Taipei, Taiwan 2Taiwan Semiconductor Manufacturing Company Limited, Taipei, Taiwan DOI: 10.1109/ICMTS.1990.161748 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Latch-up characterization in standard and twin-tub test structures by electrical measurements, 2-D simulations and IR microscopy T. Cavioni, M. Cecchetti1, M. Muschitiello2, G. Spiazzi3, I. Vottre3, E. Zanoni3 SGS Thomson, SGS Thomson Research and Development, Milano, Italy 1SGS Thomson Research and Development, Milano, Italy 2Tecnopolis CSATA, Microelectronics Center, Bari, Italy 3Dipartimento di Elettronica e Informatica, Universita di Padova, Padova, Italy DOI: 10.1109/ICMTS.1990.67877 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Accelerated current test for fast tunnel oxide evaluation (of EPROMs) P. Cappelletti, P. Ghezzi, F. Pio, C. Riva Central Research and Development, SGS-Thomson Microelectronics, Milan, Italy DOI: 10.1109/ICMTS.1990.161717 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | A new test structure to characterize the latchup effect C. Cane, M. Lozano, E. Cabruja, E. Lora-Tamayo, F. Serra-Mestres Centre Nacional de Microelectrònica, Campus de Bellaterra, Barcelona, Spain DOI: 10.1109/ICMTS.1990.67878 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Test SRAMs for characterizing alpha particle tracks in CMOS/bulk memories M. G. Buehler, B. R. Blaes, G. A. Soli Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1990.161723 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | The spidermask: a new approach for yield monitoring using product adaptable test structures S. Beckers, C. Hiltrop Mietec NV, Oudenaarde, Belgium DOI: 10.1109/ICMTS.1990.67881 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Gate oxide thickness measurement using Fowler-Nordheim tunneling R. A. Ashton AT and T Bell Laboratories, Inc., Allentown, PA, USA DOI: 10.1109/ICMTS.1990.161713 HOVER FOR ABSTRACT | PDF Xplore | |
| 1990 | Measurement of lateral diffusion on technologies with polysilicon doping source with misalignment correction J. Anguita, C. Perello, M. Lozano, C. Cane, E. Lora-Tamayo Centro Nacional de Microelectrónica, Universidad Autónoma de Barcelona, Barcelona, Spain DOI: 10.1109/ICMTS.1990.161735 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | CMOS process uniformity evaluation through the characterisation of parasitic transistors D. Wilson, A. J. Walton, J. M. Robertson, R. J. Holwill Edinburgh Microfabrication Facility, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1989.39306 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Standardization of CMOS unit process development C. Weber Circuit Technology Research and Development (Research and Development), Hewlett Packard Corporation, Palo Alto, CA, USA DOI: 10.1109/ICMTS.1989.39278 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Automating and sequencing C-V measurements for process fault diagnosis using a pattern-recognition approach (MOS test structure) J. A. Walls, A. J. Walton, J. M. Robertson, T. M. Crawford1 Edinburgh Microfabrication Facility, Edinburgh, UK 1NA DOI: 10.1109/ICMTS.1989.39308 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | A fast measurement technique for the determination of small signal parameters of the bipolar transistor P. Vandeloo IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.1989.39287 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Evaluation technique of gate oxide reliability with electrical and optical measurements Y. Uraoka, N. Tsutsu, T. Morii, Y. Nakata, H. Esaki Semiconductor Research Center, Matsushita Elecrric Indusrrial Company Limited, Moriguchi, Osaka, Japan DOI: 10.1109/ICMTS.1989.39289 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Effects of interface traps and bulk traps in SiO2 on hot-carrier-induced degradation H. Uchida, S. Inomata, T. Ajioka VLSI Research and Development Laboratory, OKI Electric Industry Company Limited, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.1989.39292 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | MOSFET effective dimensions determination for VLSI process evaluation H. P. Tuinhout Device and Process Characterisation Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1989.39282 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Electrostatic discharge test structures for CMOS circuits H. Terletzki, L. Risch Corporate Research and Development, SIEMENS AG, Munich, Germany DOI: 10.1109/ICMTS.1989.39319 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Analysis of the determination of the dimensional offset of conducting layers and MOS transistors S. Swaving, K. L. M. van der Klauw, J. J. M. Joosten Device and Process Characterization Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1989.39274 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Fault simulation for fault-tolerant multi-Mbit RAMs C. H. Stapper Department A23 General Technology Division, IBM, Corporation, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1989.39288 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | An overlay vernier and process bias monitor measured by voltage contrast SEM E. J. Sprogis IBM General Technology Division, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1989.39296 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | A new test structure for in-depth lifetime profiling of thin Si epitaxial layers P. Spirito, S. Bellone, C. M. Ransom1, G. Busatto2, G. Cocorullo2 Electronic Department, University of Naples, Naples, Italy 1IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA 2I. R. E. C. E.-CNR, Naples, Italy DOI: 10.1109/ICMTS.1989.39305 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Thermal conductivity measurements of thin-film silicon dioxide H. A. Schafft, J. S. Suehle, P. G. A. Mirel Semiconductor Electronics Division, National Bureau of Standards, National Institute for Standards and Technology, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1989.39295 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | An opamp as a tool for testing W. Sansen, F. Op't Eynde, G. Gielen Department Elektrotechniek, ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1989.39316 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Critical charge model for transient latch-up in VLSI CMOS circuits W. Reczek, J. Winnerl1, W. Pribyl Components Group, Siemens AG, Munich, Germany 1Corporate Research & Development, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1989.39318 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Test masks for micromachining silicon B. Puers, W. Sansen Dept. of Electron., Catholic Univ. of Leuven, Heverlee, Belgium DOI: 10.1109/ICMTS.1989.39280 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Automatic parameter extraction system with process failure diagnostics for CMOS process J. Pieczynski, H. Vogt Fraunhofer Institute of Microelectronic Circuits and System, Duisburg, Germany DOI: 10.1109/ICMTS.1989.39310 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Full characterization of MOS transistors in CMOS technologies J. L. Pelloie LETI-IRDI-Commissariat à l''Energie Atomique CEN/G-85X, Grenoble, France DOI: 10.1109/ICMTS.1989.39284 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Design and implementation of channel mobility measurement modules G. J. L. Ouwerling, J. C. Staalenburg1 Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands 1Philips Components, Business Unit, Nijmegen, Netherlands DOI: 10.1109/ICMTS.1989.39303 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | A simple test structure for measuring substrate resistivity J. H. Orchard-Webb, R. Cloutier1 Mitel Semicond., Bromont, Que., Canada 1Mitel Semiconductor Limited, Bromont, QUE, Canada DOI: 10.1109/ICMTS.1989.39304 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | High speed measurement of FET Vth at low Id H. Norimatsu Yokogawa-Hewlett-Packard Company, Hachioji, Tokyo, Japan DOI: 10.1109/ICMTS.1989.39276 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Standard error in die yield projections from defect test structures M. A. Mitchell, J. Sullwold, C. Figura, L. Forner Solid State Electronics Division, Honeywell, Inc., Plymouth, MN, USA DOI: 10.1109/ICMTS.1989.39307 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | A new wafer surface charge monitor (CHARM) A. M. McCarthy, W. Lukaszek Integrated Circuits Laboratory, University of Stanford, Stanford, CA, USA DOI: 10.1109/ICMTS.1989.39301 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Measurement of misalignment using a triangular MOS transistor M. Lozano, C. Cane, E. Cabruja, I. Gracia, E. Lora-Tamayo, F. Serra-Mestres Centro Nacional de Microelectónica, Universided Autónoma de Barcelona, Barcelona, Spain DOI: 10.1109/ICMTS.1989.39298 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | A programmable-load CMOS ring oscillator/inverter chain for propagation-delay measurements K. Lippe, H. Kerkhoff, G. Kloppers, N. Morskieft IC-Technology and Electronics Group, University of Twente, Enschede, Netherlands DOI: 10.1109/ICMTS.1989.39313 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Novel test structure to study location of breakdown for trench capacitor K. Kishi, T. Yoshida1, T. Watanabe, T. Tanaka, S. Shinozaki Semiconductor Device Engineering Laboratory, Toshiba Corporation, Kawasaki, Japan 1Integrated Circuit Corporation, Toshiba Corporation, Kawasaki, Japan DOI: 10.1109/ICMTS.1989.39317 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | A neural network approach for classifying test structure results D. Khera, M. E. Zaghoul1, L. W. Linholm, C. L. Wilson Semiconductor Electronics Division, National Institute for Standards and Technology, Gaithersburg, MD, USA 1Nat. Inst. of Standards & Technol., Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1989.39309 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | A floating gate method for MOS transistor gate capacitance and Leff measurements and its implementation in a parametric test R. Kazerounian, A. Singh1, B. Eltan1 Waferscale Integration, Inc., Fremont, CA, USA 1WaferScale Integration Inc., Fremont, CA, USA DOI: 10.1109/ICMTS.1989.39275 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | MOSFET interface state densities of different technologies F. Hofmann, W. Krautschneider Corporate Research & Development, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1989.39293 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Test structure for measurement of conductive film thickness M. H. Hanes, M. W. Cresswell, D. N. Schmidt, R. J. Fiedor Westinghouse Research and Development Center, Pittsburgh, PA, USA DOI: 10.1109/ICMTS.1989.39300 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | An expert system for process diagnosis (MOS product testing) A. Hamilton, R. Schofield INMOS Limited, Newport, Gwent, UK DOI: 10.1109/ICMTS.1989.39281 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Analysis of intra-level isolation test structure data by multiple regression facilitate rule identification for diagnostic expert systems C. B. Freidhoff, M. W. Cresswell, L. R. Lowry, K. B. Irani1 Westinghouse Research and Development Center, Pittsburgh, PA, USA 1Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA DOI: 10.1109/ICMTS.1989.39312 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Gate dimension characterization using the inversion layer G. Freeman, W. Lukaszek Center of Integrated Systems, University of Stanford, Stanford, CA, USA DOI: 10.1109/ICMTS.1989.39271 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | The effect of contact geometry on the value of contact resistivity extracted from Kelvin structures K. W. J. Findlay, W. J. C. Alexander, A. J. Walton Edinburgh Microfabrication Facility, Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1989.39297 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Area-periphery partitioning of currents in self-aligned silicon bipolar transistors J. Fertsch, J. Weng, M. Miura-Mattausch Central Research and Development, Siemens AG, Munchen, Germany DOI: 10.1109/ICMTS.1989.39286 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Parameter extraction for a SPICE II VDMOS model J. Fernandez, S. Hidalgo1, F. Berta1, J. Paredes1, J. Rebollo1, J. Millan1, F. Serra-Mestres1 CSIC-UAB, Barcelona, Spain 1Centro Nacional de Microelectrónica, CSIC-UAB, Barcelona, Spain DOI: 10.1109/ICMTS.1989.39277 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | An experimental measurement technique of interconnection RC delay for integrated circuits using the step voltage response S. G. dos Santos F., J. W. Swart1 Sao Paulo Univ., Brazil 1FEEC Unicamp, Sao Paulo, Brazil DOI: 10.1109/ICMTS.1989.39315 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Drain and bulk symmetry factor: a statistical tool to improve device reliability P. Dars, T. T. d'ouville, G. Merckel, H. Mingam CNS, CNET, Meylan, France DOI: 10.1109/ICMTS.1989.39320 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Off-line photolithographic parameter extraction using electrical test structures C. M. Cork INMOS Limited, Newport, Gwent, UK DOI: 10.1109/ICMTS.1989.39272 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | The INMOS integrated parametric test and analysis system D. Cheung, A. Clark, R. Starr INMOS Limited, Newport, Gwent, UK DOI: 10.1109/ICMTS.1989.39279 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Test structure for evaluation of 1/f noise in CMOS technologies Z. Y. Chang, W. Sansen Department Elektrotechniek, ESAT-MICAS, KU Leuvęn, Heverlee, Belgium DOI: 10.1109/ICMTS.1989.39299 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Contact electromigration: a method to characterize test structures for reliability parameter estimation C. Caprile, G. Specchiulli1 STMicroelectronics, Agrate-Brianza, Italy 1TELETTRA S.P.A, Vimercate, Italy DOI: 10.1109/ICMTS.1989.39294 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Statistical worst-case MOS parameter extraction M. J. B. Bolt, A. Trip, H. J. Verhagen Device and Process Characterisation Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1989.39311 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | | Inverter propagation delay measurements using timing sampler circuits B. R. Blaes, M. G. Buehler Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1989.39314 HOVER FOR ABSTRACT | PDF Xplore |
| 1989 | Subtleties of SPICE MOSFET parameter extraction P. Bendix Semiconductor Optimization and Simulation, Inc., Redwood, CA, USA DOI: 10.1109/ICMTS.1989.39283 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Electrical characterization of minority carrier transport parameters in n-type heavily doped silicon S. Bellone, G. Busatto1, C. M. Ransom2 Electronic Department, University of Naples, Naples, Italy 1CNR, I. R. E. C. E., Naples, Italy 2Thomas J. Watson Research Center, IBM, Corporation, Yorktown Heights, NY, USA DOI: 10.1109/ICMTS.1989.39302 HOVER FOR ABSTRACT | PDF Xplore | |
| 1989 | Enhanced MOS parameter extraction and SPICE modelling for mixed analogue and digital circuit simulation B. Ankele, W. Holzl, P. O'Leary Schloss Premstätten, Austria Microsystems International Gmbh, Unterpremstatten, Austria DOI: 10.1109/ICMTS.1989.39285 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Temperature Control In Wafer-level Testing Of Large Multi-segment Electromigration Test Structures N. Zamani, Yu-sang Lin Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1988.672949 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Ring Oscillator Structure For realistic Dynamic Stress Of MOSFETS And Interconnects J. Winnerl, F. Neppl, A. Lill, G. Roska, W. Zatisch1 Corporate Research and Development, Microelectronics, Siemens AG, Munich, Germany 1NA DOI: 10.1109/ICMTS.1988.672929 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Evaluating Integrated Circuit Technologles For Space Application - The GVSC Test Chip K. T. Wilson, T. C. Zietlow1, T. C. Morse, T. K. Tsubota, J. G. Rollins, R. R. Herndon2 Aerospace Corporation, El Segundo, CA, USA 1NA 2Air Force Space Technology Center, Kirtland Air Force Base, Albuquerque, NM DOI: 10.1109/ICMTS.1988.672952 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Delta-L Extraction Using Parasitic Bipolar Transistors D. Wilson, A. J. Walton, J. M. Robertson, R. J. Holwill Edinburgh Microfabrication Facility, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1988.672940 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Standard Defect Monitor C. Weber Silicon Process Laboratory, Hewlett Packard Corporation, Palo Alto, CA, USA DOI: 10.1109/ICMTS.1988.672945 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Interpretation of capacitance-voltage curves for process fault diagnosis: a machine-learning expert system approach J. A. Walls, A. J. Walton, J. M. Robertson, T. M. Crawford Edinburgh Microfabrication Facility Department of Electrical Engineering, University of Edinburgh, UK DOI: 10.1109/ICMTS.1988.672956 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Determination Of The HF Model Parameters Of The MOS Transistor By Using Standard Dropin Test Structures P. Vandeloo, W. Sansen1 Elektrotechniek, KU Leuven, Leuven, Belgium 1IMEC, Leuven, Belgium DOI: 10.1109/ICMTS.1988.672942 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | A Fully Analytical MOSFET Model Parameter Extraction Approach H. P. Tuinhout, S. Swaving, J. J. M. Joosten Device and Process Characterization Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1988.672933 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Impact Of The Self-heating Effect On Circuit Performance Estimation Using DC Model Parameters D. Takace, J. Trager1, D. Schmitt-Landsiedel1 Siemens Ag 1Corporate Research and Development, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1988.672928 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | MOS-IC Process And Device Characterization Within Philips S. Swaving, A. Ketting, A. Trip1 Device and Process Characterization Group, Philips Research Laboratories, Eindhoven, Netherlands 1Eindhoven, Netherlands DOI: 10.1109/ICMTS.1988.672957 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Test Circuit Structures For Characterizing The Effects Of Localized Hot-carrier-induced Charge In VLSI Switching Circuits J. S. Suehle, K. F. Galloway1 Electrical Engineering Department, University of Maryland, College Park, MD, USA 1Electrical and Computer Engineering Department, University of Arizona Tucson, Tucson, AZ, USA DOI: 10.1109/ICMTS.1988.672947 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | An Objective Method Of Assessing Metal Patterning Quality J. T. M. Stevenson, J. Gow, J. Serack Edinburgh Microfabrication Facility, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1988.672924 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Determination Of Process-dependent Critical SPICE Parameters For Application-specific ICs B. J. Sheu, Chung-Ping Wan, Chih-Ching Shih, Wen-Jay Hsu, M. C. Hsu Department of Electrical Engineering and Information Sciences Institute, University of Southern California, Los Angeles, CA, USA DOI: 10.1109/ICMTS.1988.672932 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | A Novel Device Structure For Studying Gate And Channel Edge Effects In IGFET's J. A. Serack, A. J. Walton, J. M. Robertson Edinburgh Microfabrication Facility, University of Edinburgh, Edinburgh, UK DOI: 10.1109/ICMTS.1988.672931 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Thermal Interactions Between Electromigration Test Structures H. A. Schafft, J. Albers Semiconductor Electronics Division, National Bureau of Standards, Gaithersburg, MD, USA DOI: 10.1109/ICMTS.1988.672948 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Comb/serpentine/cross-bridge Test Structure For Fabrication Process Evaluation H. R. Sayah, M. G. Buehler Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1988.672923 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Guidelines For Latch-up Characterization Techniques W. Reczek, W. Pribyl Components Group, Siemens AG, Munich, Germany DOI: 10.1109/ICMTS.1988.672946 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Test Vehicle For The Measurement Of Charge Collection And Soft Error rate Prediction In high-density Memories due to alpha-particle strikes P. Oldiges, T. Furuyama1, J. Frey2 Department of Electrical Engineering, Cornell University, Ithaca, NY, USA 1Semiconductor Device Engineering Laboratory, Toshiba Corporation, Kawasaki, Japan 2Department of Electrical Engineering, University of Maryland, College Park, MD, USA DOI: 10.1109/ICMTS.1988.672951 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Defect Diagnostic Matrix -a Defect Learning Vehicle For Submicron Technologies R. E. Newhart, E. J. Sprogis General Technology Division, IBM, Essex Junction, VT, USA DOI: 10.1109/ICMTS.1988.672943 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Total Dose Radiation Respnse Of Test Structures And VLSI Lcqic Devices: An Analytical And Experimental Correlation D. M. Newberry, B. E. Peters Control Data Corporation, Bloomington, MN, USA DOI: 10.1109/ICMTS.1988.672930 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Expert System For Test Structure Data Interpretation F. N. H. Montijn-Dorgelo, H. J. ter Horst Device and Process Characterisation Group and Computer Science Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1988.672955 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | A developmental expert system for test structure ata evaluation L. W. Linholm, D. Khera1, C. P. Reeve2, M. W. Cresswell3 National Bureau of Standards, Gaithersburg, MD, USA 1Electrical Engineering Department, University of Maryland, College Park, MD, USA 2Gaithersburg, MD, USA 3Westinghouse Research and Development Center, Pittsburgh, PA, USA DOI: 10.1109/ICMTS.1988.672953 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Experiences In Extraction Of Contact Parameters From Process Evaluation Test-structures U. Lieneweg Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1988.672921 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Interconnect capacitance characterization for mos-ic process and circuit design C. Kortekaas Device and Process Characterization Group, Philips Research Laboratories, Eindhoven, Netherlands DOI: 10.1109/ICMTS.1988.672926 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | A Microelectronic Test Structure For Thickness Determination Of Homogeneous Conducting Thin Films In VLSI Processing J. S. Kim, L. W. Linholm, B. L. Barley, M. H. Hanes1, M. W. Cresswell1 National Bureau of Standards, Gaithersburg, MD, USA 1Westinghouse Research and Development Center, Pittsburgh, PA, USA DOI: 10.1109/ICMTS.1988.672925 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Statistical Significance Of Defect density Estimates U. Kaempf Circuit Technology Group, Hewlett Packard Company, Palo Alto, CA, USA DOI: 10.1109/ICMTS.1988.672944 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | A Test Structure To Measure The misalignment between Poly-si And Diffusion layers Mi Jian Electronic Engineering Department, Tianjin University, TJU, Tianjin, China DOI: 10.1109/ICMTS.1988.672962 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Automatic test structure modification K. Golshan, S. S. M. Shetti, M. Howard1 Semiconductor Process and Design Center VLSI Design Laboratory, Texas Instruments, Inc., Dallas, TX, USA 1NA DOI: 10.1109/ICMTS.1988.672959 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | The Design And Calibration Of A Semiconductor Strain Gauge Array S.A. Gee, V. R. Akylas, W. F. van den Bogert Philips Research Laboratories Sunnyvale, Signetics Corporation, Sunnyvale, CA, USA DOI: 10.1109/ICMTS.1988.672958 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | An Electrical Test Structure For Measuring Contact Size G. Freeman, W. Lukaszek Center For Integrated Systems, University of Stanford, USA DOI: 10.1109/ICMTS.1988.672920 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Spatially Non-uniform, Time Varying Thermal Characterization Of VlSI Chips B. J. Cooke, J. L. Prince, Z. J. Staszak, D. Shope, W. J. Fahey Department of Electrical and Computer Engineering, Electronic Packaging Laboratory, University of Arizona Tucson, Tucson, AZ, USA DOI: 10.1109/ICMTS.1988.672950 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Measurement Of Static Noise Immunity For STL And ISL Bipolar Logics J. M. Chateau, M. Depey Thomson Semiconductors, Grenoble, France DOI: 10.1109/ICMTS.1988.672960 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Method For Accurate Determinaton Of The Intrinsic Cut-off Frequency of IC Bipolar Transistors D. Celi Thomson Semiconductors, Saint Egreve, France DOI: 10.1109/ICMTS.1988.672961 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Comparison Of Results From Simple Expressions For MOSFET Parameter Extraction M. G. Buemer, Y. -S. Lin1 California Institute Of Technology 1Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1988.672941 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | CMOS Process Monitor M. G. Buehler, L. W. Linholm1, V. C. Tyree2, R. A. Allen3, B. R. Blaes, G. A. Jennings, K. A. Hicks Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA 1National Bureau of Standards, WA, USA 2Information Sciences Institute, University of Southern California, CA, USA 3NA DOI: 10.1109/ICMTS.1988.672954 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | A Direct Method For Measuring The Gate Oxide Capwi-hnces Of MOSFETS R. A. Allen, C. A. Pina, M. G. Buehler Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA DOI: 10.1109/ICMTS.1988.672927 HOVER FOR ABSTRACT | PDF Xplore | |
| 1988 | Sources Of Error In Extracting The Specific Contact Resistance From Kelvin Device Measurements W. J. C. Alexander, A. J. Walton Edinburgh Microfabrication Facility Department of Electrical Engineering, Edinburgh University, Edinburgh, UK DOI: 10.1109/ICMTS.1988.672922 HOVER FOR ABSTRACT | PDF Xplore | |
| 1984 | 4.6 | HOVER FOR ABSTRACT | |
| 1984 | 4.5 | HOVER FOR ABSTRACT | |
| 1984 | 4.4 | HOVER FOR ABSTRACT | |
| 1984 | 4.3 | HOVER FOR ABSTRACT | |
| 1984 | 4.2 | Pre-Processor Geometry, Temperature and Parameter Modelling of Short and Narrow MOSFETs for LVSI Circuit Simulation, Optimization and Statistics with SPICE G. T. Wright, H. M. Gaffur University of Birmingham, UK HOVER FOR ABSTRACT | |
| 1984 | 4.1 | Latch-Up Test Structures and Their Characterization W. J. Craig IBM Corporation HOVER FOR ABSTRACT | |
| 1984 | 3.7 | HOVER FOR ABSTRACT | |
| 1984 | 3.6 | HOVER FOR ABSTRACT | |
| 1984 | 3.5 | Test Structures for Examining Electromigration H. A. Schafft, A. N. Saxena1, C. -Y. Kao1 National Bureau of Standards 1AMI HOVER FOR ABSTRACT | |
| 1984 | 3.4 | HOVER FOR ABSTRACT | |
| 1984 | 3.3 | HOVER FOR ABSTRACT | |
| 1984 | 3.2 | HOVER FOR ABSTRACT | |
| 1984 | 3.1 | Pinhole Array Cpacitor for Oxide Integrity Analysis M. G. Buehler Jet Propulsion Labs HOVER FOR ABSTRACT | |
| 1984 | 2.3 | Test Chip Strategy for a High Volume VLSI Design Laboratory M. E. Potter Bell Labs HOVER FOR ABSTRACT | |
| 1984 | 2.2 | An Integrated Approach to Technology Characterization R. E. Tremain, P. J. Martin, Y. J. Oki, M. Y. T. Young, D. L. Scharfetter Xerox Palo Alto Research Center HOVER FOR ABSTRACT | |
| 1984 | 2.1 | Test Device for CMOS/SOS Parameter Testing J. H. Nelson, H. L. Chew Rockwell International Corporation HOVER FOR ABSTRACT | |
| 1984 | 1.6 | Isolation Test Structures for CMOS J. Y. Chen Hughes Research Laboratories HOVER FOR ABSTRACT | |
| 1984 | 1.5 | Layer to Layer Interconnects in VLSI Circuits G. K. Reeves, H. B. Harrison1, G. Sai-Halasz1 Telecom Australia 1RMIT, Australia HOVER FOR ABSTRACT | |
| 1984 | 1.4 | Electrical Characterization of Epitaxial Silicon K. P. Roenker, T. J. Morthorst, C. Baylis1 University of Cincinnati 1Cincinnati Milacron HOVER FOR ABSTRACT | |
| 1984 | 1.3 | Lifetime Interpretation from Silicon Test Structures D. K. Schroder Arizona State University HOVER FOR ABSTRACT | |
| 1984 | 1.2 | Integrated Circuit Test Structure for Measuring Mask/Reticle Misalignment B. Henderson Burroughs Micro Components Group HOVER FOR ABSTRACT | |
| 1984 | 1.1 | The Application of Microelectronic Test Structures for Linewidth Measurement in the Near and Submicron Region L. W. Linholm, D. Yen, M. W. Cresswell1 National Bureau of Standards 1Westinghouse Electric Corporation HOVER FOR ABSTRACT |
