ICMTS 2026 Schedule
Tutorials: Monday, Mar 23
| 08:30 | Registration Desk Opens | |
| 08:55 | Tutorials Welcome Takayuki Mori (Tutorial Chair) Kanazawa Institute of Technology | |
| 09:00 | T1 | Fundamentals of Test Structures and Measurement Stewart Smith The University of Edinburgh ABSTRACT: William Thomson (Lord Kelvin) made many statements applicable to measurement as well as having his name applied to test structures and measurement techniques widely used by ICMTS attendees. Whether or not he actually said “If you can not measure it, you cannot improve it” is unclear but it definitely applies to the field of microelectronic test structures. This tutorial will begin with a short review of test structures detailing their history and hot topics over the past 40+ years. Test structures, instrumentation and measurement techniques for the resistive, capacitive and active devices will be introduced and discussed, as well as some of the measurement issues you may encounter. |
| 09:50 | T2 | Device and Process technologies for advanced logic semiconductor Masaharu Kobayashi The University of Tokyo ABSTRACT: High performance computing enabled by semiconductor integrated circuits is the infrastructure for AI technologies. Recent advancement of generative AI technologies demand high computing performance than ever before. On the other hand, power composition accompanied by AI technologies becomes the challenge for sustainable society. Scaling of the semiconductor technology is expected to contribute to higher performance and lower power computing. In this presentation, I will overview the device and process technologies in advanced logic semiconductor, which will be the key for tackling the challenges. |
| 10:40 | Break | |
| 11:00 | T3 | Advanced Packaging Technologies Enabling Chiplet-Based Systems Fumihiro Inoue Yokohama National University ABSTRACT: The rapid growth of cloud AI has driven extreme requirements for compute density, memory bandwidth, and energy efficiency, exposing the physical and economic limits of monolithic system-on-chip (SoC) scaling. Chiplet-based architectures have therefore emerged as a scalable integration approach, enabling functional partitioning and heterogeneous system design. In this context, advanced packaging technologies, particularly hybrid bonding, play a central role. Hybrid bonding provides ultra-fine-pitch, low-resistance interconnects with energy efficiency approaching on-die wiring, making it a key enabler for tightly coupled logic–memory integration and high-performance AI systems. This tutorial introduces advanced packaging technologies with a focus on hybrid bonding for chiplet-based integration. Core concepts of 2.5D and 3D integration are outlined, followed by discussion of hybrid bonding processes, design considerations, and reliability challenges. The impact of bonding technology on power delivery, thermal management, and system scalability is examined through examples from cloud AI accelerators. The tutorial also extends the discussion from cloud AI to edge AI systems, where power efficiency, form factor, and cost constraints further emphasize the importance of fine-pitch, low-overhead interconnect technologies. Future trends toward die-to-wafer hybrid bonding and system-level co-design are briefly discussed. |
| 11:50 | Lunch | |
| 13:20 | T4 | Fundamentals of RF measurements, modeling, and test structure design Shuhei Amakawa Hiroshima University ABSTRACT: This tutorial will cover basic concepts in RF, related to measurements, modeling, and test structure design. It will first introduce the basic physical picture of wave propagation along a transmission line in a way understandable to IC designers not necessarily specializing in RF. It will then discuss the concept of S-parameters and how measurement/simulation reference planes should be defined. Some practical measurement and modeling issues will be presented that the speaker encountered and dealt with when working with frequencies above 100 GHz, together with design recommendations. |
| 14:10 | T5 | Next Generation Power Electronics Technologies Based on Wide Bandgap Semiconductors Yasunori Tanaka National Institute of Advanced Industrial Science and Technology ABSTRACT: The advancement of next-generation power electronics technologies based on wide-bandgap semiconductors has accelerated dramatically over the past two to three years. In particular, SiC power semiconductors, owing to their superior material properties, have been rapidly put into practical use as key devices that significantly contribute to higher efficiency and reduced size and weight of power converters in the field of electric mobility, including railway systems and electric vehicles (EVs). As a result, SiC power devices are steadily establishing their position as a fundamental technology underpinning an electrified society. In this presentation, an overview will be provided of the characteristics of next-generation power semiconductor devices, focusing on SiC, as well as related device process and design technologies. |
| 15:00 | Break | |
| 15:20 | T6 | Key Device Technologies and Challenges for 3D Non-Volatile Memory Masumi Saitoh Kioxia Corporation ABSTRACT: This tutorial provides an overview of recent research trends in 3D non-volatile memory. Non-volatile memory is moving to 3D stacking for increasing the bit density to meet the demand for large datasets of AI. There are two main 3D approaches: vertical stacking (e.g. 3D flash memory) and horizontal stacking (e.g. cross-point memory). 3D flash memory has been leading aggressive multi-layer stacking of non-volatile memory. Stacked ReRAM (Resistive RAM) and PCM (Phase Change Memory) have been proposed for various applications including in-memory computing. Ferroelectric memory with ferroelectric HfO film has been widely studied for various 3D structures such as FeFET (Ferroelectric FET), FeRAM (Ferroelectric RAM), and FTJ (Ferroelectric Tunnel Junction). MRAM (Magnetic RAM) with advanced MTJ has been developed for high-speed and high-density cross-point memory. There remain key challenges such as process integration, reliability, and device variability, requiring tight collaboration between basic research and manufacturing to deliver low-cost and high-performance 3D non-volatile memory. |
| 16:10 | T7 | Silicon quantum computer and cryo-CMOS technologies Takahiro Mori National Institute of Advanced Industrial Science and Technology ABSTRACT: Quantum computers aim to solve some computational problems that are difficult for conventional technologies to solve. There are currently some candidates for their hardware, and we can use some prototype machines. However, their performance is insufficient to solve practical problems, so no clear winners have emerged yet, because the number of available qubits is still low. Therefore, large-scale integration is highly desired. From this perspective, silicon qubit technology is promising because we can use mature fabrication technologies developed for LSI technology. This talk introduces silicon quantum computer technology, its research trends, and its outlook. It also introduces cryo-CMOS technology, which will be used to control qubits to realize quantum gate operation. |
| 17:00 | Close of Tutorials | |
| 17:30 | Welcome Reception for All ICMTS Attendees |
Day 1: Tuesday, Mar 24
| 08:30 | Registration Desk Opens | |
| 09:00 | Opening Remarks Y. Fukuzaki (General Chair), K. Xia (Technical Program Chair)1, T. Ohguro (Technical Program Chair)2 Rapidus US, LLC, USA 1TSMC 2Toshiba Electric Devices & Storage Corporation | |
Session 1: Circuits for Test and Computation | ||
| Session Chairs: | Brad SMITH, BeeSmith, LLC Larg WEILAND, PDF Solutions, Inc. | |
| 09:10 | 1.1 | Ultra-low leakage power switch for RO array characterization in 18nm FD-SOI technology platform validation C. Cagli, H. Degoirat, M. Lamy, F. Pourchon, J. B. Moulard, F. Granoux, M. Dahmani, R. Wilson STMicroelectronics, 850 Rue Jean Monnet, Crolles, France |
| 09:30 | 1.2 | Statistical Capacitance Measurement of Si Trench Capacitors Using 3D Stacked Array Test Circuit Ryoya Nishimaki, Koga Saito, Takezo Mawaki, Rihito Kuroda Graduate School of Engineering, Tohoku University |
| 09:50 | 1.3 | Influence of solder bumps-induced mechanical constraint on the performance of BJT ring oscillators M. Dahmani, S. Gallois-Garreignot, M. Dugor, B. Van-Haaren, L. Broussous, F. Belfils, C. Cagli STMicroelectronics, 850 Rue Jean Monnet, Crolles, France |
| 10:10 | 1.4 | Improving Robustness of Leakage-Based MOSFET Reservoir Computing Using Adaptive Pulse-Width Control Ryuto Seki, Masami Utsunomiya, Yu-Guang Chen1, Hiromitsu Awano, Takashi Sato Graduate School of Informatics, Kyoto University Yoshida-hon-machi, Sakyo, Kyoto, Japan 1Department of Electrical Engineering, National Central University, Taiwan |
| 10:30 | Break | |
Session 2: AI and Machine Learning | ||
| Session Chairs: | Takayuki MORI, Kanazawa Institute of Technology Tatsuya OHGURO, Toshiba Electric Devices & Storage Corporation | |
| 10:50 | 2.1 | Machine Learning-Based Failure Mode Detection in 3D-DRAM Gate-All-Around Select Transistors Jerome Mitard, Husnu Murat Kocak, Romain Ritzenthaler, Nouredine Rassoul, Eren Canga, A. Belmonte Compute Technology Device Department, IMEC, Belgium |
| 11:10 | 2.2 | Speeding Up Capacitance-Voltage Measurements Using Gaussian Processes and Active Learning Husnu Murat Kocak, Hiroaki Arimura1, Jerome Mitard1, Jesse Davis Department of Computer Science, KU Leuven, Celestijnenlaan 200A, Leuven, Belgium 1Compute Technology Device Department, IMEC, Remisebosweg 1, Leuven, Belgium |
| 11:30 | 2.3 | Accelerating Load-Pull Measurements Using Attentive Neural Processes Jui-Yang Hsu, Yu-Ting Chen, Bo-Yuan Chen, Chao-Wen Lin, Chia-Wei Chuang, Chuang-Ju Lin, Kun-Ming Chen, Guo-Wei Huang Taiwan Semiconductor Research Institute, National Institutes of Applied Research |
| 11:50 | 2.4 | VQ-VAE–Based Test Structure Generation for Constructing Design-Fabrication Surrogate Models Ryugo Shimamura, Shun Yasunaga, Tomoya Nakamura, Chen Wang1, Michael Kraft1, Yoshio Mita The University of Tokyo, EEIS 1KU Leuven, ESAT/MNS |
| 12:10 | Lunch | |
Session 3: Device Characterization | ||
| Session Chairs: | Jerome MITARD, imec Francesco DRIUSSI, Università degli Studi di Udine | |
| 13:30 | 3.1 | On-Wafer Golden Devices and Layout Structures for Long-term Prober Chuck Temperature Verification and Monitoring Wuxia Li, Kejun Xia1, Lei Chao, Shimeng Zhang NXP Semiconductors, Front End Innovation 1TSMC, Power Management Business Development |
| 13:50 | 3.2 | Monte Carlo simulation method for distance-dependent mismatch and comparison of common-centroid and dispersion layouts Kejun Xia TSMC, Power Management Business Development |
| 14:10 | 3.3 | Optimum Setting of 1/f Noise System towards Ultra-low- noise Floor and Best Practice for Multi-finger MOSFET Noise Characterization Lei Chao, Shimeng Zhang, Jeroen van Beurden, Andries Scholten, Wuxia Li NXP Semiconductors, Front End Innovation |
| 14:30 | 3.4 | Evaluation of Dummy Biasing on Leakage and Noise Performance in 4-nm FinFET Process Seunghyun Noh, Jinho Choi, Yoongeun Seun, SungJoon Park, Jooyoung Song Samsung Electronics, Giheung-gu, Yongin-si, Republic of Korea |
| 14:50 | Break | |
| 15:10 | Exhibitors | |
Session 4: Process Characterization | ||
| Session Chairs: | Wuxia LI, NXP Semiconductors Jerome MITARD, imec | |
| 15:50 | 4.1 | Defect profiling of Al2O3-passivated InGaP layers via planar test structures Paolo La Torraca, Pavel Kirilienko1, Rajan Bharti, Muskan Jain, Satish Bonam, Lida Ansari, Farzan Gity, Karim Cherkaoui2, Alexander Tonkikh2, Dmitry Sizov2, Paul Gore2, Michael Grundmann, Paul K. Hurley Tyndall National Institute, Cork, Ireland 1Tyndall National Institute, Cork, Ireland Tyndall National Institute, Cork, Ireland 2Meta Reality Labs |
| 16:10 | 4.2 | Extraction of Shockley-Read-Hall lifetime at the InGaP/Al2O3 interface using transient capacitance relaxation Pavel Kirilienko, Paolo La Torraca, Rajan Bharti, Muskan Jain, Satish Bonam, Lida Ansari, Farzan Gity, Karim Cherkaoui, Emanuele Pelucchi, Gediminas Juska, Alexander Tonkikh, Andreas Arnlind, Dmitry Sizov, Paul Gore, Michael Grundmann, Paul K. Hurley Tyndall National Institute, Cork, Ireland |
| 16:30 | 4.3 | Accuracy Limits of TLM and CTLM Test Structures for Ultra- Low Contact Resistance Extraction in InGaAs/InP Technologies Anouk Lubben, Yi Wang, Yuqing Jiao, Johan Klootwijk Eindhoven Hendrick Casimir Institute, Eindhoven University of Technology, Eindhoven, the Netherlands |
| 16:50 | End of Day 1 | |
Day 2: Wednesday, Mar 25
| 08:30 | Registration Desk Opens | |
| 09:00 | Invited Talk 1 Chih-Ting Lin Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan | |
Session 5: MEMS and Sensors | ||
| Session Chairs: | Yoshio MITA, The University of Tokyo Stewart SMITH, The University of Edinburgh | |
| 10:00 | 5.1 | A Contact-Closing Test Structure for Electrical In-Chamber Release Endpoint Detection During Vapor HF Etching Akihiko Yoshida, Shun Yasunaga, Ryosho Nakane, Akio Higo, Yoshio Mita The University of Tokyo |
| 10:20 | 5.2 | Comparative Study of Transducer Materials for Sodium- Selective EGISFETs: Stability Improvement and Interference Rejection Kai-Chun Huang, Yan-You Zhou, Chih-Ting Lin Graduate Institute of Electronic Engineering, National Taiwan University |
| 10:40 | 5.3 | An Ultra-Thin Indium Oxide FET Test Structure for Sweat Ion Sensing Jheng-Ru Wu, Yu-Ta Chen1, Chien-Fu Chen Graduate School of Advanced Technology, National Taiwan University 1Nano Electromechanical Systems Research Center, National Taiwan University |
| 11:00 | Break | |
Session 6: Memory | ||
| Session Chairs: | Carlo CAGLI, STMicroelectronics N.V. Yuzo FUKUZAKI, Rapidus US, LLC, USA | |
| 11:20 | 6.1 | Read Current in Ferroelectric Tunnel Junctions: Transient versus DC Contributions and Trap Related Effects F. Driussi, M. Segatto, M. Massarotto, L. Carpentieri1, S. Slesazeck1, D. Esseni DPIA, Università degli Studi di Udine, Via delle Scienze 206, Udine, Italy 1NaMLab gGmbH, Nothnitzer Str. 64a, 01187 Dresden, Germany |
| 11:40 | 6.2 | MRAM Wafer Level Adaptative Edge Testing for E icient Yield and Reliability Control Maximilian Liehr, Sean Ogden, Mark Raymond, Kyle Funk, Herve Elemva, Kilho Lee, Gen Feng, Karsten Beckmann, Antoine Chavent1, Tien Dang Ngoc1, Daniel Grout1, Steven Lequeux1, Siamak SALIMY1 NY CREATES, 253 Fuller Road, Albany, NY 12203, USA 1Hprobe Mycronic, 4 rue Joliot Curie, 38320 Eybens, France |
| 12:00 | 6.3 | Comparison of Addressing Methods for Memory Array Characterization Martin Arteaga Castillo, Vincenzo Della Marca1, Marc Bocquet1, Jeremy Postel-Pellerin1, Olivier Paulet, Loic Welter, Matthias Vidal-Dho, Baptiste Chatelier, Brice Arrazat Department of Technology and Design Platforms, STMicroelectronics, Rousset, France 1Aix-Marseille University, IM2NP, CNRS, UMR 7334, Marseille, France |
| 12:20 | 6.4 | On-Chip Learning with EEPROM Based Synapses: Reliability and Performance Assessment Thibault BERGAMASCHI, Bastien IMBERT, Vincenzo DELLA-MARCA, Sebastien PERRIN, Arnaud REGNIER1, Madjid AKBAL1, Christian RIVERO1, Nicolas ZAMMIT1, Thibault KEMPF1, Jorge-Daniel AGUIRRE-MORALES, Jean-Michel PORTAL, Marc BOCQUET Aix-Marseille Univ, Université de Toulon, CNRS, IM2NP, Marseille, France 1STMicroelectronics Rousset, France |
| 12:40 | Lunch | |
Session 7: Reliability | ||
| Session Chairs: | Francesco DRIUSSI, Università degli Studi di Udine Carlo CAGLI, STMicroelectronics N.V. | |
| 14:00 | 7.1 | Characterization of Non-conducting RF Hot Carrier Stress Impact on transistor noise from 10 MHz to 26.5 GHz in 5-nm FinFETs G. Niu, X. Ding, H. Zhang1, W. Wang1, K. Imura1 ECE Department, Auburn University, Auburn, AL, USA 1Maxlinear Inc., Carlsbad, CA, USA |
| 14:20 | 7.2 | Impact of Fluorine Incorporation on Boron Diffusion and Reliability in Advanced High Voltage FinFETs Jia-Hong Lin, Po-Hsun Chen1, Ling, Tang2, Meng-Xuan Feng3, Ting-Chang Chang4 Department of Physics, National Sun Yat-sen University, Kaohsiung, 80424, Taiwan 1Department of Electronic Engineering, I-Shou University, Kaohsiung 840, Taiwan 2Institute of Advanced Semiconductor Packaging and Testing, National Sun Yat-sen University, Kaohsiung, 80424, Taiwan 3Department of Microelectronics Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, 811213, Taiwan 4Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan |
| 14:40 | 7.3 | Parasitic Characterization of Hot-Carrier-Induced Degradation using Experimental S-Parameters for RF- MOSFETs Chika Tanaka, Tatsuya Suzuki, Atsushi Sueoka, Fumie Fujii, Kazuya Matsuzawa Memory Division, Kioxia Corporation, Japan |
| 15:00 | 7.4 | Reliability Comparison under Drain Bias Stress for N- and P-Type LTPS Thin-Film Transistors Meng-Xuan Feng, Po-Wen Chang, Sheng-Po Chang, Jia-Hong Lin1, Tsung-Ming Tsai2 Microelectronics Engineering, National Kaohsiung University of Science and Technology, Taiwan 1Department of Physics, National Sun Yat-sen University, Taiwan 2Department of Materials and Optoelectronic Science, National Sun Yat-Sen University,Taiwan |
| 15:20 | Break | |
| 15:40 | ICMTS 2027 Presentation Francesco Driussi Università degli Studi di Udine | |
Session 8: ESD | ||
| Session Chairs: | Kejun XIA, TSMC Jun TANIGUCHI, Keysight Technologies, Japan | |
| 15:50 | 8.1 | Test Structures to Study Interconnection Metal/Via/Contact Reliability under Transient Pulse Stresses of ESD and Surge Events Pi-Yuan Hsiao, Chia-Tsen Dai1, Tung-Yang Chen1, Ming-Dou Ker Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan 1AIP Technology Corporation, Taiwan Branch |
| 16:10 | 8.2 | The Influence of Skin Effect on Metal Lines in ESD Protection Circuit Cheng-Han Chiang, Chun-Yu Lin Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan |
| 16:30 | 8.3 | Investigation on ESD Robustness of SiC Devices by Transmission Line Pulse Measurement for Monolithic Integration Applications Hung-Yu Huang, Ya-Zhi Hu1, Ming-Dou Ker1 Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University, Hsinchu, Taiwan 1Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan |
| 16:50 | End of Day 2 | |
| 17:30 | Banquet | |
Day 3: Thursday, Mar 26
| 08:45 | Invited Talk 2 Ken Uchida The University of Tokyo | |
Session 9: Cryogenics | ||
| Session Chairs: | Stewart SMITH, The University of Edinburgh Wuxia LI, NXP Semiconductors | |
| 09:35 | 9.1 | Impact of Contacts and Heatsinks on Heat Accumulation in Cryogenic SOI MOSFETs Kosuke Hatta, Takayuki Mori, Shota Kondo, Hiroshi Oka1, Takahiro Mori1, Jiro Ida Kanazawa Institute of Technology, Ishikawa, Japan 1National Institute of Advanced Industrial Science and Technology, Ibaraki, Japan |
| 09:55 | 9.2 | Maintaining Constant Vth from 1.7 K to 390 K Using adaptive back gate bias in 22 FDX technology Ergen Tao, Guofu Niu, Anni Zhang, Yili Wang ECE Department, Auburn University, Auburn, AL, USA |
| 10:15 | 9.3 | Characteristics of P-type Polysilicon Resistors from Cryogenic to High Temperatures and Modeling Yili Wang, Kejun Xia1, Guofu Niu, Jim Xia2, Michael Hamilton ECE Department, Auburn University, Auburn, AL, USA 1TSMC, Hsinchu, Taiwan 2BASIS Chandler, Arizona, USA |
| 10:35 | Break | |
Session 10: Power Devices | ||
| Session Chairs: | Kohei OASA, Toshiba Electric Devices & Storage Corporation Kejun XIA, TSMC | |
| 10:50 | 10.1 | Investigation of Crystal-Face-Resolved Gate Switching Instability in 4H-SiC UMOSFETs Enabled by a Source-Separated Single-Cell Structure Wei-Jhe Liao, Chia-Lung Hung1, Yi-Kai Hsiao1, Bing-Yue Tsui Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan 1Semiconductor Research Center, Hon Hai Research Institute, Hsinchu, Taiwan |
| 11:10 | 10.2 | Evaluation of Rise-Time Effects on AC-TDDB Characteristics in SiC MOSFETs Using an In-Situ Gate Leakage Measurement Technique S. NAKATA, T. SATO Kanazawa Institute of Technology, Japan |
| 11:30 | 10.3 | Application of a three-terminal TCAD model for designing shielded field-limiting ring edge termination Kiyoshi Takeuchi, Munetoshi Fukui, Takuya Saraya, Kazuo Itou, Toshihiko Takakura, Shinichi Suzuki, Hiroyuki Takase, Toshiro Hiramoto Institute of Industrial Science, The University of Tokyo, Tokyo, Japan |
| 11:50 | 10.4 | Optimizing LDMOS Device Performance and Reliability Through Drift-Region Engineering Po-Wen Chang, Jia-Hong Lin1, Meng-Xuan Feng, Sheng-Po Chang, Po-Hsun Chen2 Department of Microelectronics Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan 1Department of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan 2Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan |
| 12:10 | Best Paper Award, Closing | |
| 12:20 | Lunch and Excursion | |